drv_qei.c 8.0 KB

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  1. /**************************************************************************//**
  2. *
  3. * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: Apache-2.0
  6. *
  7. * Change Logs:
  8. * Date Author Notes
  9. * 2021-10-21 Wayne First version
  10. *
  11. ******************************************************************************/
  12. #include <rtconfig.h>
  13. #if defined(BSP_USING_QEI)
  14. #include <rtdevice.h>
  15. #include "drv_sys.h"
  16. #include "drv_common.h"
  17. /* Private define ---------------------------------------------------------------*/
  18. enum
  19. {
  20. QEI_START = -1,
  21. #if defined(BSP_USING_QEI0)
  22. QEI0_START,
  23. #endif
  24. #if defined(BSP_USING_QEI1)
  25. QEI1_START,
  26. #endif
  27. #if defined(BSP_USING_QEI2)
  28. QEI2_START,
  29. #endif
  30. QEI_CNT
  31. };
  32. /* Private typedef --------------------------------------------------------------*/
  33. struct nu_qei
  34. {
  35. struct rt_pulse_encoder_device dev;
  36. char *name;
  37. QEI_T *base;
  38. IRQn_Type irqn;
  39. uint32_t rstidx;
  40. uint32_t modid;
  41. rt_uint32_t max_cntval;
  42. rt_uint32_t cmp_val;
  43. rt_uint8_t qei_flag;
  44. };
  45. typedef struct nu_qei *nu_qei_t;
  46. /* Private functions ------------------------------------------------------------*/
  47. static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder);
  48. static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder);
  49. static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder);
  50. static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder);
  51. static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args);
  52. /* Public functions -------------------------------------------------------------*/
  53. rt_int32_t nu_qei_get_maxval(struct rt_pulse_encoder_device *pulse_encoder);
  54. rt_int32_t nu_qei_get_cmpval(struct rt_pulse_encoder_device *pulse_encoder);
  55. rt_int32_t nu_qei_get_type(struct rt_pulse_encoder_device *pulse_encoder);
  56. void nu_qei_set_maxval_type(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val, rt_uint8_t u8type);
  57. void nu_qei_set_cmpval(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val);
  58. /* Private variables ------------------------------------------------------------*/
  59. static struct nu_qei nu_qei_arr [] =
  60. {
  61. #if defined(BSP_USING_QEI0)
  62. {
  63. .name = "qei0",
  64. .base = QEI0,
  65. .irqn = QEI0_IRQn,
  66. .rstidx = QEI0_RST,
  67. .modid = QEI0_MODULE,
  68. .max_cntval = 1000,
  69. .cmp_val = 100,
  70. },
  71. #endif
  72. #if defined(BSP_USING_QEI1)
  73. {
  74. .name = "qei1",
  75. .base = QEI1,
  76. .irqn = QEI1_IRQn,
  77. .rstidx = QEI1_RST,
  78. .modid = QEI1_MODULE,
  79. .max_cntval = 1000,
  80. .cmp_val = 100,
  81. },
  82. #endif
  83. #if defined(BSP_USING_QEI2)
  84. {
  85. .name = "qei2",
  86. .base = QEI2,
  87. .irqn = QEI2_IRQn,
  88. .rstidx = QEI2_RST,
  89. .modid = QEI2_MODULE,
  90. .max_cntval = 1000,
  91. .cmp_val = 100,
  92. },
  93. #endif
  94. };
  95. static const struct rt_pulse_encoder_ops nu_qei_ops =
  96. {
  97. .init = nu_qei_init,
  98. .get_count = nu_qei_get_count,
  99. .clear_count = nu_qei_clear_count,
  100. .control = nu_qei_control,
  101. };
  102. /* Public variables -------------------------------------------------------------*/
  103. static rt_uint32_t nu_qei_type(struct rt_pulse_encoder_device *pulse_encoder)
  104. {
  105. rt_uint32_t u32type;
  106. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  107. RT_ASSERT(pulse_encoder != RT_NULL);
  108. switch (pulse_encoder->type)
  109. {
  110. case SINGLE_PHASE_PULSE_ENCODER:
  111. u32type = (psNuQei->cmp_val) ? QEI_CTL_X2_COMPARE_COUNTING_MODE : QEI_CTL_X2_FREE_COUNTING_MODE;
  112. break;
  113. case UNKNOWN_PULSE_ENCODER_TYPE:
  114. case AB_PHASE_PULSE_ENCODER:
  115. default:
  116. u32type = (psNuQei->cmp_val) ? QEI_CTL_X4_COMPARE_COUNTING_MODE : QEI_CTL_X4_FREE_COUNTING_MODE;
  117. break;
  118. }
  119. return u32type;
  120. }
  121. void nu_qei_set_cmpval(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val)
  122. {
  123. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  124. RT_ASSERT(pulse_encoder != RT_NULL);
  125. QEI_SET_CNT_CMP(psNuQei->base, u32val);
  126. if (u32val > 0)
  127. {
  128. QEI_EnableInt(psNuQei->base, QEI_CTL_CMPIEN_Msk);
  129. QEI_ENABLE_CNT_CMP(psNuQei->base);
  130. rt_hw_interrupt_umask(psNuQei->irqn);
  131. }
  132. else
  133. {
  134. QEI_DisableInt(psNuQei->base, QEI_CTL_CMPIEN_Msk);
  135. QEI_DISABLE_CNT_CMP(psNuQei->base);
  136. rt_hw_interrupt_mask(psNuQei->irqn);
  137. }
  138. }
  139. static rt_err_t nu_qei_init(struct rt_pulse_encoder_device *pulse_encoder)
  140. {
  141. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  142. RT_ASSERT(pulse_encoder != RT_NULL);
  143. /* enable noise filter */
  144. QEI_ENABLE_NOISE_FILTER(psNuQei->base, QEI_CTL_NFCLKSEL_DIV2);
  145. /* set compare value and interrupt */
  146. nu_qei_set_cmpval(pulse_encoder, psNuQei->cmp_val);
  147. /* set qei mode */
  148. QEI_Open(psNuQei->base, nu_qei_type(pulse_encoder), psNuQei->max_cntval);
  149. return RT_EOK;
  150. }
  151. static rt_int32_t nu_qei_get_count(struct rt_pulse_encoder_device *pulse_encoder)
  152. {
  153. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  154. RT_ASSERT(pulse_encoder != RT_NULL);
  155. return (rt_int32_t)QEI_GET_CNT_VALUE(psNuQei->base);
  156. }
  157. static rt_err_t nu_qei_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
  158. {
  159. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  160. RT_ASSERT(pulse_encoder != RT_NULL);
  161. QEI_Stop(psNuQei->base);
  162. QEI_SET_CNT_VALUE(psNuQei->base, 0);
  163. QEI_Start(psNuQei->base);
  164. return RT_EOK;
  165. }
  166. static rt_err_t nu_qei_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
  167. {
  168. rt_err_t result = RT_EOK;
  169. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  170. RT_ASSERT(pulse_encoder != RT_NULL);
  171. switch (cmd)
  172. {
  173. case PULSE_ENCODER_CMD_ENABLE:
  174. /* set compare value and interrupt */
  175. QEI_Start(psNuQei->base);
  176. nu_qei_set_cmpval(pulse_encoder, psNuQei->cmp_val);
  177. break;
  178. case PULSE_ENCODER_CMD_DISABLE:
  179. QEI_Stop(psNuQei->base);
  180. nu_qei_set_cmpval(pulse_encoder, 0);
  181. break;
  182. default:
  183. result = -RT_ENOSYS;
  184. break;
  185. }
  186. return result;
  187. }
  188. static void nu_qei_isr(int vector, void *param)
  189. {
  190. nu_qei_t psNuQei = (nu_qei_t)param;
  191. if (QEI_GET_INT_FLAG(psNuQei->base, QEI_STATUS_CMPF_Msk))
  192. {
  193. QEI_CLR_INT_FLAG(psNuQei->base, QEI_STATUS_CMPF_Msk);
  194. rt_kprintf("%s: CMP flag rising\n", psNuQei->name) ;
  195. }
  196. }
  197. rt_int32_t nu_qei_get_maxval(struct rt_pulse_encoder_device *pulse_encoder)
  198. {
  199. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  200. RT_ASSERT(pulse_encoder != RT_NULL);
  201. return psNuQei->max_cntval;
  202. }
  203. rt_int32_t nu_qei_get_cmpval(struct rt_pulse_encoder_device *pulse_encoder)
  204. {
  205. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  206. RT_ASSERT(pulse_encoder != RT_NULL);
  207. return psNuQei->cmp_val;
  208. }
  209. rt_int32_t nu_qei_get_type(struct rt_pulse_encoder_device *pulse_encoder)
  210. {
  211. RT_ASSERT(pulse_encoder != RT_NULL);
  212. return nu_qei_type(pulse_encoder);
  213. }
  214. void nu_qei_set_maxval_type(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t u32val, enum rt_pulse_encoder_type eType)
  215. {
  216. nu_qei_t psNuQei = (nu_qei_t)pulse_encoder;
  217. RT_ASSERT(pulse_encoder != RT_NULL);
  218. RT_ASSERT(eType <= AB_PHASE_PULSE_ENCODER);
  219. psNuQei->dev.type = eType;
  220. psNuQei->max_cntval = u32val;
  221. QEI_Open(psNuQei->base, nu_qei_type(&psNuQei->dev), u32val);
  222. }
  223. int rt_hw_qei_init(void)
  224. {
  225. int i;
  226. rt_err_t result = RT_EOK;
  227. for (i = (QEI_START + 1); i < QEI_CNT; i++)
  228. {
  229. nu_qei_t psNuQei = &nu_qei_arr[i];
  230. psNuQei->dev.type = AB_PHASE_PULSE_ENCODER;
  231. psNuQei->dev.ops = &nu_qei_ops;
  232. /* Enable QEI module */
  233. CLK_EnableModuleClock(psNuQei->modid);
  234. SYS_ResetModule(psNuQei->rstidx);
  235. /* register isr */
  236. rt_hw_interrupt_install(psNuQei->irqn, nu_qei_isr, psNuQei, psNuQei->name);
  237. result = rt_device_pulse_encoder_register((struct rt_pulse_encoder_device *)&nu_qei_arr[i].dev, nu_qei_arr[i].name, RT_NULL);
  238. RT_ASSERT(result == RT_EOK);
  239. }
  240. return (int)result;
  241. }
  242. INIT_APP_EXPORT(rt_hw_qei_init);
  243. #endif /* BSP_USING_QEI */