drv_smc911x.c 14 KB

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  1. #include <board.h>
  2. #include <rtthread.h>
  3. #include <netif/ethernetif.h>
  4. #include <lwipopts.h>
  5. #include <automac.h>
  6. #define MAX_ADDR_LEN 6
  7. #define SMC911X_EMAC_DEVICE(eth) (struct eth_device_smc911x*)(eth)
  8. #include "drv_smc911x.h"
  9. #define DRIVERNAME "EMAC"
  10. struct eth_device_smc911x
  11. {
  12. /* inherit from Ethernet device */
  13. struct eth_device parent;
  14. /* interface address info. */
  15. rt_uint8_t enetaddr[MAX_ADDR_LEN]; /* MAC address */
  16. uint32_t iobase;
  17. uint32_t irqno;
  18. };
  19. static struct eth_device_smc911x _emac;
  20. int udelay(int value)
  21. {
  22. return 0;
  23. }
  24. int mdelay(int value)
  25. {
  26. return 0;
  27. }
  28. #if defined (CONFIG_SMC911X_32_BIT)
  29. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  30. {
  31. return *(volatile uint32_t*)(dev->iobase + offset);
  32. }
  33. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  34. {
  35. *(volatile uint32_t*)(dev->iobase + offset) = val;
  36. }
  37. #elif defined (CONFIG_SMC911X_16_BIT)
  38. rt_inline uint32_t smc911x_reg_read(struct eth_device_smc911x *dev, uint32_t offset)
  39. {
  40. volatile uint16_t *addr_16 = (uint16_t *)(dev->iobase + offset);
  41. return ((*addr_16 & 0x0000ffff) | (*(addr_16 + 1) << 16));
  42. }
  43. rt_inline void smc911x_reg_write(struct eth_device_smc911x *dev, uint32_t offset, uint32_t val)
  44. {
  45. *(volatile uint16_t *)(dev->iobase + offset) = (uint16_t)val;
  46. *(volatile uint16_t *)(dev->iobase + offset + 2) = (uint16_t)(val >> 16);
  47. }
  48. #else
  49. #error "SMC911X: undefined bus width"
  50. #endif /* CONFIG_SMC911X_16_BIT */
  51. struct chip_id
  52. {
  53. uint16_t id;
  54. char *name;
  55. };
  56. static const struct chip_id chip_ids[] =
  57. {
  58. { CHIP_89218,"LAN89218" },
  59. { CHIP_9115, "LAN9115" },
  60. { CHIP_9116, "LAN9116" },
  61. { CHIP_9117, "LAN9117" },
  62. { CHIP_9118, "LAN9118" },
  63. { CHIP_9211, "LAN9211" },
  64. { CHIP_9215, "LAN9215" },
  65. { CHIP_9216, "LAN9216" },
  66. { CHIP_9217, "LAN9217" },
  67. { CHIP_9218, "LAN9218" },
  68. { CHIP_9220, "LAN9220" },
  69. { CHIP_9221, "LAN9221" },
  70. { 0, RT_NULL },
  71. };
  72. static uint32_t smc911x_get_mac_csr(struct eth_device_smc911x *dev, uint8_t reg)
  73. {
  74. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  75. smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg);
  76. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  77. return smc911x_reg_read(dev, MAC_CSR_DATA);
  78. }
  79. static void smc911x_set_mac_csr(struct eth_device_smc911x *dev, uint8_t reg, uint32_t data)
  80. {
  81. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  82. smc911x_reg_write(dev, MAC_CSR_DATA, data);
  83. smc911x_reg_write(dev, MAC_CSR_CMD, MAC_CSR_CMD_CSR_BUSY | reg);
  84. while (smc911x_reg_read(dev, MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY) ;
  85. }
  86. static int smc911x_detect_chip(struct eth_device_smc911x *dev)
  87. {
  88. unsigned long val, i;
  89. val = smc911x_reg_read(dev, BYTE_TEST);
  90. if (val == 0xffffffff)
  91. {
  92. /* Special case -- no chip present */
  93. return -1;
  94. }
  95. else if (val != 0x87654321)
  96. {
  97. rt_kprintf(DRIVERNAME ": Invalid chip endian 0x%08lx\n", val);
  98. return -1;
  99. }
  100. val = smc911x_reg_read(dev, ID_REV) >> 16;
  101. for (i = 0; chip_ids[i].id != 0; i++)
  102. {
  103. if (chip_ids[i].id == val) break;
  104. }
  105. if (!chip_ids[i].id)
  106. {
  107. rt_kprintf(DRIVERNAME ": Unknown chip ID %04lx\n", val);
  108. return -1;
  109. }
  110. return 0;
  111. }
  112. static void smc911x_reset(struct eth_device_smc911x *dev)
  113. {
  114. int timeout;
  115. /*
  116. * Take out of PM setting first
  117. * Device is already wake up if PMT_CTRL_READY bit is set
  118. */
  119. if ((smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY) == 0)
  120. {
  121. /* Write to the bytetest will take out of powerdown */
  122. smc911x_reg_write(dev, BYTE_TEST, 0x0);
  123. timeout = 10;
  124. while (timeout-- && !(smc911x_reg_read(dev, PMT_CTRL) & PMT_CTRL_READY))
  125. udelay(10);
  126. if (timeout < 0)
  127. {
  128. rt_kprintf(DRIVERNAME
  129. ": timeout waiting for PM restore\n");
  130. return;
  131. }
  132. }
  133. /* Disable interrupts */
  134. smc911x_reg_write(dev, INT_EN, 0);
  135. smc911x_reg_write(dev, HW_CFG, HW_CFG_SRST);
  136. timeout = 1000;
  137. while (timeout-- && smc911x_reg_read(dev, E2P_CMD) & E2P_CMD_EPC_BUSY)
  138. udelay(10);
  139. if (timeout < 0)
  140. {
  141. rt_kprintf(DRIVERNAME ": reset timeout\n");
  142. return;
  143. }
  144. /* Reset the FIFO level and flow control settings */
  145. smc911x_set_mac_csr(dev, FLOW, FLOW_FCPT | FLOW_FCEN);
  146. smc911x_reg_write(dev, AFC_CFG, 0x0050287F);
  147. /* Set to LED outputs */
  148. smc911x_reg_write(dev, GPIO_CFG, 0x70070000);
  149. }
  150. static void smc911x_handle_mac_address(struct eth_device_smc911x *dev)
  151. {
  152. unsigned long addrh, addrl;
  153. uint8_t *m = dev->enetaddr;
  154. addrl = m[0] | (m[1] << 8) | (m[2] << 16) | (m[3] << 24);
  155. addrh = m[4] | (m[5] << 8);
  156. smc911x_set_mac_csr(dev, ADDRL, addrl);
  157. smc911x_set_mac_csr(dev, ADDRH, addrh);
  158. }
  159. static int smc911x_eth_phy_read(struct eth_device_smc911x *dev,
  160. uint8_t phy, uint8_t reg, uint16_t *val)
  161. {
  162. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
  163. smc911x_set_mac_csr(dev, MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY);
  164. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY) ;
  165. *val = smc911x_get_mac_csr(dev, MII_DATA);
  166. return 0;
  167. }
  168. static int smc911x_eth_phy_write(struct eth_device_smc911x *dev,
  169. uint8_t phy, uint8_t reg, uint16_t val)
  170. {
  171. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
  172. ;
  173. smc911x_set_mac_csr(dev, MII_DATA, val);
  174. smc911x_set_mac_csr(dev, MII_ACC,
  175. phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE);
  176. while (smc911x_get_mac_csr(dev, MII_ACC) & MII_ACC_MII_BUSY)
  177. ;
  178. return 0;
  179. }
  180. static int smc911x_phy_reset(struct eth_device_smc911x *dev)
  181. {
  182. uint32_t reg;
  183. reg = smc911x_reg_read(dev, PMT_CTRL);
  184. reg &= ~0xfffff030;
  185. reg |= PMT_CTRL_PHY_RST;
  186. smc911x_reg_write(dev, PMT_CTRL, reg);
  187. mdelay(100);
  188. return 0;
  189. }
  190. static void smc911x_phy_configure(struct eth_device_smc911x *dev)
  191. {
  192. int timeout;
  193. uint16_t status;
  194. smc911x_phy_reset(dev);
  195. smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET);
  196. mdelay(1);
  197. smc911x_eth_phy_write(dev, 1, MII_ADVERTISE, 0x01e1);
  198. smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
  199. timeout = 5000;
  200. do
  201. {
  202. mdelay(1);
  203. if ((timeout--) == 0)
  204. goto err_out;
  205. if (smc911x_eth_phy_read(dev, 1, MII_BMSR, &status) != 0)
  206. goto err_out;
  207. }
  208. while (!(status & BMSR_LSTATUS));
  209. return;
  210. err_out:
  211. rt_kprintf(DRIVERNAME ": autonegotiation timed out\n");
  212. }
  213. static void smc911x_enable(struct eth_device_smc911x *dev)
  214. {
  215. /* Enable TX */
  216. smc911x_reg_write(dev, HW_CFG, 8 << 16 | HW_CFG_SF);
  217. smc911x_reg_write(dev, GPT_CFG, GPT_CFG_TIMER_EN | 10000);
  218. smc911x_reg_write(dev, TX_CFG, TX_CFG_TX_ON);
  219. /* no padding to start of packets */
  220. smc911x_reg_write(dev, RX_CFG, 0);
  221. smc911x_set_mac_csr(dev, MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN |
  222. MAC_CR_HBDIS);
  223. }
  224. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  225. /* wrapper for smc911x_eth_phy_read */
  226. static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
  227. int reg)
  228. {
  229. uint16_t val = 0;
  230. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  231. if (dev)
  232. {
  233. int retval = smc911x_eth_phy_read(dev, phy, reg, &val);
  234. if (retval < 0)
  235. return retval;
  236. return val;
  237. }
  238. return -ENODEV;
  239. }
  240. /* wrapper for smc911x_eth_phy_write */
  241. static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
  242. int reg, uint16_t val)
  243. {
  244. struct eth_device_smc911x *dev = eth_get_dev_by_name(bus->name);
  245. if (dev)
  246. return smc911x_eth_phy_write(dev, phy, reg, val);
  247. return -ENODEV;
  248. }
  249. #endif
  250. static void smc911x_isr(int vector, void *param)
  251. {
  252. uint32_t status;
  253. struct eth_device_smc911x *emac;
  254. emac = SMC911X_EMAC_DEVICE(param);
  255. status = smc911x_reg_read(emac, INT_STS);
  256. if (status & INT_STS_RSFL)
  257. {
  258. eth_device_ready(&emac->parent);
  259. }
  260. smc911x_reg_write(emac, INT_STS, status);
  261. return ;
  262. }
  263. static rt_err_t smc911x_emac_init(rt_device_t dev)
  264. {
  265. // uint32_t value;
  266. struct eth_device_smc911x *emac;
  267. emac = SMC911X_EMAC_DEVICE(dev);
  268. RT_ASSERT(emac != RT_NULL);
  269. smc911x_reset(emac);
  270. /* Configure the PHY, initialize the link state */
  271. smc911x_phy_configure(emac);
  272. smc911x_handle_mac_address(emac);
  273. /* Turn on Tx + Rx */
  274. smc911x_enable(emac);
  275. #if 1
  276. /* Interrupt on every received packet */
  277. smc911x_reg_write(emac, FIFO_INT, 0x01 << 8);
  278. smc911x_reg_write(emac, INT_EN, INT_EN_RDFL_EN | INT_EN_RSFL_EN);
  279. /* enable interrupt */
  280. smc911x_reg_write(emac, INT_CFG, INT_CFG_IRQ_EN | INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
  281. #else
  282. /* disable interrupt */
  283. smc911x_reg_write(emac, INT_EN, 0);
  284. value = smc911x_reg_read(emac, INT_CFG);
  285. value &= ~INT_CFG_IRQ_EN;
  286. smc911x_reg_write(emac, INT_CFG, value);
  287. #endif
  288. rt_hw_interrupt_install(emac->irqno, smc911x_isr, emac, "smc911x");
  289. rt_hw_interrupt_umask(emac->irqno);
  290. return RT_EOK;
  291. }
  292. static rt_err_t smc911x_emac_control(rt_device_t dev, int cmd, void *args)
  293. {
  294. struct eth_device_smc911x *emac;
  295. emac = SMC911X_EMAC_DEVICE(dev);
  296. RT_ASSERT(emac != RT_NULL);
  297. switch(cmd)
  298. {
  299. case NIOCTL_GADDR:
  300. /* get MAC address */
  301. if(args) rt_memcpy(args, emac->enetaddr, 6);
  302. else return -RT_ERROR;
  303. break;
  304. default :
  305. break;
  306. }
  307. return RT_EOK;
  308. }
  309. /* Ethernet device interface */
  310. /* transmit packet. */
  311. static uint8_t tx_buf[2048];
  312. rt_err_t smc911x_emac_tx(rt_device_t dev, struct pbuf* p)
  313. {
  314. struct eth_device_smc911x *emac;
  315. uint32_t *data;
  316. uint32_t tmplen;
  317. uint32_t status;
  318. uint32_t length;
  319. emac = SMC911X_EMAC_DEVICE(dev);
  320. RT_ASSERT(emac != RT_NULL);
  321. /* copy pbuf to a whole ETH frame */
  322. pbuf_copy_partial(p, tx_buf, p->tot_len, 0);
  323. /* send it out */
  324. data = (uint32_t*)tx_buf;
  325. length = p->tot_len;
  326. smc911x_reg_write(emac, TX_DATA_FIFO, TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length);
  327. smc911x_reg_write(emac, TX_DATA_FIFO, length);
  328. tmplen = (length + 3) / 4;
  329. while (tmplen--)
  330. {
  331. smc911x_reg_write(emac, TX_DATA_FIFO, *data++);
  332. }
  333. /* wait for transmission */
  334. while (!((smc911x_reg_read(emac, TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16));
  335. /* get status. Ignore 'no carrier' error, it has no meaning for
  336. * full duplex operation
  337. */
  338. status = smc911x_reg_read(emac, TX_STATUS_FIFO) &
  339. (TX_STS_LOC | TX_STS_LATE_COLL | TX_STS_MANY_COLL |
  340. TX_STS_MANY_DEFER | TX_STS_UNDERRUN);
  341. if (!status) return 0;
  342. rt_kprintf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n",
  343. status & TX_STS_LOC ? "TX_STS_LOC " : "",
  344. status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "",
  345. status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "",
  346. status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "",
  347. status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : "");
  348. return -RT_EIO;
  349. }
  350. /* reception packet. */
  351. struct pbuf *smc911x_emac_rx(rt_device_t dev)
  352. {
  353. struct pbuf* p = RT_NULL;
  354. struct eth_device_smc911x *emac;
  355. emac = SMC911X_EMAC_DEVICE(dev);
  356. RT_ASSERT(emac != RT_NULL);
  357. /* take the emac buffer to the pbuf */
  358. if ((smc911x_reg_read(emac, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED) >> 16)
  359. {
  360. uint32_t status;
  361. uint32_t pktlen, tmplen;
  362. status = smc911x_reg_read(emac, RX_STATUS_FIFO);
  363. /* get frame length */
  364. pktlen = (status & RX_STS_PKT_LEN) >> 16;
  365. smc911x_reg_write(emac, RX_CFG, 0);
  366. tmplen = (pktlen + 3) / 4;
  367. /* allocate pbuf */
  368. p = pbuf_alloc(PBUF_RAW, tmplen * 4, PBUF_RAM);
  369. if (p)
  370. {
  371. uint32_t *data = (uint32_t *)p->payload;
  372. while (tmplen--)
  373. {
  374. *data++ = smc911x_reg_read(emac, RX_DATA_FIFO);
  375. }
  376. }
  377. if (status & RX_STS_ES)
  378. {
  379. rt_kprintf(DRIVERNAME ": dropped bad packet. Status: 0x%08x\n", status);
  380. }
  381. }
  382. return p;
  383. }
  384. #ifdef RT_USING_DEVICE_OPS
  385. const static struct rt_device_ops smc911x_emac_ops =
  386. {
  387. smc911x_emac_init,
  388. RT_NULL,
  389. RT_NULL,
  390. RT_NULL,
  391. RT_NULL,
  392. smc911x_emac_control
  393. };
  394. #endif
  395. int smc911x_emac_hw_init(void)
  396. {
  397. _emac.iobase = VEXPRESS_ETH_BASE;
  398. _emac.irqno = IRQ_VEXPRESS_A9_ETH;
  399. if (smc911x_detect_chip(&_emac))
  400. {
  401. rt_kprintf("no smc911x network interface found!\n");
  402. return -1;
  403. }
  404. /* set INT CFG */
  405. smc911x_reg_write(&_emac, INT_CFG, INT_CFG_IRQ_POL | INT_CFG_IRQ_TYPE);
  406. /* test MAC address */
  407. _emac.enetaddr[0] = AUTOMAC0;
  408. _emac.enetaddr[1] = AUTOMAC1;
  409. _emac.enetaddr[2] = AUTOMAC2;
  410. _emac.enetaddr[3] = AUTOMAC3;
  411. _emac.enetaddr[4] = AUTOMAC4;
  412. _emac.enetaddr[5] = AUTOMAC5;
  413. #ifdef RT_USING_DEVICE_OPS
  414. _emac.parent.parent.ops = &smc911x_emac_ops;
  415. #else
  416. _emac.parent.parent.init = smc911x_emac_init;
  417. _emac.parent.parent.open = RT_NULL;
  418. _emac.parent.parent.close = RT_NULL;
  419. _emac.parent.parent.read = RT_NULL;
  420. _emac.parent.parent.write = RT_NULL;
  421. _emac.parent.parent.control = smc911x_emac_control;
  422. #endif
  423. _emac.parent.parent.user_data = RT_NULL;
  424. _emac.parent.eth_rx = smc911x_emac_rx;
  425. _emac.parent.eth_tx = smc911x_emac_tx;
  426. /* register ETH device */
  427. eth_device_init(&(_emac.parent), "e0");
  428. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  429. {
  430. int retval;
  431. struct mii_dev *mdiodev = mdio_alloc();
  432. if (!mdiodev)
  433. return -ENOMEM;
  434. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  435. mdiodev->read = smc911x_miiphy_read;
  436. mdiodev->write = smc911x_miiphy_write;
  437. retval = mdio_register(mdiodev);
  438. if (retval < 0)
  439. return retval;
  440. }
  441. #endif
  442. eth_device_linkchange(&_emac.parent, RT_TRUE);
  443. return 0;
  444. }
  445. INIT_APP_EXPORT(smc911x_emac_hw_init);