phytium_cpu_id.S 2.8 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023-07-26 huanghe first commit
  11. * 2024-07-02 zhangyan modify
  12. *
  13. */
  14. #include "fparameters.h"
  15. #include "rtconfig.h"
  16. #ifndef __aarch64__
  17. .globl cpu_id_mapping
  18. cpu_id_mapping:
  19. #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
  20. cmp r0, #0 // compare cpu_id with 0
  21. beq map_cpu_id_0
  22. cmp r0, #1 // compare cpu_id with 1
  23. beq map_cpu_id_1
  24. cmp r0, #2 // compare cpu_id with 2
  25. beq map_cpu_id_2
  26. cmp r0, #3 // compare cpu_id with 3
  27. beq map_cpu_id_3
  28. mov pc, lr // no mapping needed
  29. #endif
  30. mov pc, lr // no mapping needed
  31. // Mapping for E2000Q
  32. map_cpu_id_0:
  33. mov r0, #2
  34. mov pc, lr
  35. map_cpu_id_1:
  36. mov r0, #3
  37. mov pc, lr
  38. map_cpu_id_2:
  39. mov r0, #0
  40. mov pc, lr
  41. map_cpu_id_3:
  42. mov r0, #1
  43. mov pc, lr
  44. .globl rt_hw_cpu_id_early
  45. rt_hw_cpu_id_early:
  46. // read MPIDR
  47. mov r9, lr
  48. mrc p15, 0, r0, c0, c0, 5
  49. ubfx r0, r0, #0, #12
  50. ldr r1,= CORE0_AFF
  51. cmp r0, r1
  52. beq core0
  53. #if defined(CORE1_AFF)
  54. ldr r1,= CORE1_AFF
  55. cmp r0, r1
  56. beq core1
  57. #endif
  58. #if defined(CORE2_AFF)
  59. ldr r1,= CORE2_AFF
  60. cmp r0, r1
  61. beq core2
  62. #endif
  63. #if defined(CORE3_AFF)
  64. ldr r1,= CORE3_AFF
  65. cmp r0, r1
  66. beq core3
  67. #endif
  68. b default
  69. core0:
  70. mov r0, #0
  71. b return
  72. core1:
  73. mov r0, #1
  74. b return
  75. core2:
  76. mov r0, #2
  77. b return
  78. core3:
  79. mov r0, #3
  80. b return
  81. default:
  82. and r0, r0, #15
  83. return:
  84. bl cpu_id_mapping
  85. mov pc, r9
  86. #else
  87. .globl cpu_id_mapping
  88. cpu_id_mapping:
  89. #if defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
  90. cmp x0, #0 // compare cpu_id with 0
  91. beq map_cpu_id_0
  92. cmp x0, #1 // compare cpu_id with 1
  93. beq map_cpu_id_1
  94. cmp x0, #2 // compare cpu_id with 2
  95. beq map_cpu_id_2
  96. cmp x0, #3 // compare cpu_id with 3
  97. beq map_cpu_id_3
  98. RET // no mapping needed
  99. #endif
  100. RET // no mapping needed
  101. // Mapping for E2000Q
  102. map_cpu_id_0:
  103. mov x0, #2
  104. RET
  105. map_cpu_id_1:
  106. mov x0, #3
  107. RET
  108. map_cpu_id_2:
  109. mov x0, #0
  110. RET
  111. map_cpu_id_3:
  112. mov x0, #1
  113. RET
  114. .globl rt_hw_cpu_id_set
  115. rt_hw_cpu_id_set:
  116. mov x9, lr
  117. mrs x0,MPIDR_EL1
  118. and x1, x0, #15
  119. msr tpidr_el1, x1
  120. mov lr, x9
  121. RET
  122. .globl rt_hw_cpu_id
  123. rt_hw_cpu_id:
  124. mrs x0,MPIDR_EL1
  125. ubfx x0, x0, #0, #12
  126. ldr x1,= CORE0_AFF
  127. cmp x0, x1
  128. beq core0
  129. #if defined(CORE1_AFF)
  130. ldr x1,= CORE1_AFF
  131. cmp x0, x1
  132. beq core1
  133. #endif
  134. #if defined(CORE2_AFF)
  135. ldr x1,= CORE2_AFF
  136. cmp x0, x1
  137. beq core2
  138. #endif
  139. #if defined(CORE3_AFF)
  140. ldr x1,= CORE3_AFF
  141. cmp x0, x1
  142. beq core3
  143. #endif
  144. core0:
  145. mov x0, #0
  146. b return
  147. core1:
  148. mov x0, #1
  149. b return
  150. core2:
  151. mov x0, #2
  152. b return
  153. core3:
  154. mov x0, #3
  155. b return
  156. return:
  157. b cpu_id_mapping
  158. RET
  159. #endif