sdhci.h 32 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815
  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-16 zhujiale first version
  9. */
  10. #ifndef __SDHCI_HW_H
  11. #define __SDHCI_HW_H
  12. #include "sdhci_host.h"
  13. #include "sdhci_misc.h"
  14. #include "sdhci_dma.h"
  15. #include "sdhci-platform.h"
  16. #include <drivers/mmcsd_cmd.h>
  17. #include <drivers/mmcsd_host.h>
  18. #include <rtdevice.h>
  19. /*
  20. * Controller registers
  21. */
  22. #define lower_32_bits(n) ((rt_uint32_t)((n) & 0xffffffff))
  23. #define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
  24. #define MAX_TUNING_LOOP 40
  25. #define SDHCI_DMA_ADDRESS 0x00
  26. #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
  27. #define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS
  28. #define SDHCI_BLOCK_SIZE 0x04
  29. #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  30. #define SDHCI_BLOCK_COUNT 0x06
  31. #define SDHCI_ARGUMENT 0x08
  32. #define SDHCI_TRANSFER_MODE 0x0C
  33. #define SDHCI_TRNS_DMA 0x01
  34. #define SDHCI_TRNS_BLK_CNT_EN 0x02
  35. #define SDHCI_TRNS_AUTO_CMD12 0x04
  36. #define SDHCI_TRNS_AUTO_CMD23 0x08
  37. #define SDHCI_TRNS_AUTO_SEL 0x0C
  38. #define SDHCI_TRNS_READ 0x10
  39. #define SDHCI_TRNS_MULTI 0x20
  40. #define SDHCI_COMMAND 0x0E
  41. #define SDHCI_CMD_RESP_MASK 0x03
  42. #define SDHCI_CMD_CRC 0x08
  43. #define SDHCI_CMD_INDEX 0x10
  44. #define SDHCI_CMD_DATA 0x20
  45. #define SDHCI_CMD_ABORTCMD 0xC0
  46. #define SDHCI_CMD_RESP_NONE 0x00
  47. #define SDHCI_CMD_RESP_LONG 0x01
  48. #define SDHCI_CMD_RESP_SHORT 0x02
  49. #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
  50. #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  51. #define SDHCI_GET_CMD(c) ((c >> 8) & 0x3f)
  52. #define SDHCI_RESPONSE 0x10
  53. #define SDHCI_BUFFER 0x20
  54. #define SDHCI_PRESENT_STATE 0x24
  55. #define SDHCI_CMD_INHIBIT 0x00000001
  56. #define SDHCI_DATA_INHIBIT 0x00000002
  57. #define SDHCI_DOING_WRITE 0x00000100
  58. #define SDHCI_DOING_READ 0x00000200
  59. #define SDHCI_SPACE_AVAILABLE 0x00000400
  60. #define SDHCI_DATA_AVAILABLE 0x00000800
  61. #define SDHCI_CARD_PRESENT 0x00010000
  62. #define SDHCI_CARD_PRES_SHIFT 16
  63. #define SDHCI_CD_STABLE 0x00020000
  64. #define SDHCI_CD_LVL 0x00040000
  65. #define SDHCI_CD_LVL_SHIFT 18
  66. #define SDHCI_WRITE_PROTECT 0x00080000
  67. #define SDHCI_DATA_LVL_MASK 0x00F00000
  68. #define SDHCI_DATA_LVL_SHIFT 20
  69. #define SDHCI_DATA_0_LVL_MASK 0x00100000
  70. #define SDHCI_CMD_LVL 0x01000000
  71. #define SDHCI_HOST_CONTROL 0x28
  72. #define SDHCI_CTRL_LED 0x01
  73. #define SDHCI_CTRL_4BITBUS 0x02
  74. #define SDHCI_CTRL_HISPD 0x04
  75. #define SDHCI_CTRL_DMA_MASK 0x18
  76. #define SDHCI_CTRL_SDMA 0x00
  77. #define SDHCI_CTRL_ADMA1 0x08
  78. #define SDHCI_CTRL_ADMA32 0x10
  79. #define SDHCI_CTRL_ADMA64 0x18
  80. #define SDHCI_CTRL_ADMA3 0x18
  81. #define SDHCI_CTRL_8BITBUS 0x20
  82. #define SDHCI_CTRL_CDTEST_INS 0x40
  83. #define SDHCI_CTRL_CDTEST_EN 0x80
  84. #define SDHCI_POWER_CONTROL 0x29
  85. #define SDHCI_POWER_ON 0x01
  86. #define SDHCI_POWER_180 0x0A
  87. #define SDHCI_POWER_300 0x0C
  88. #define SDHCI_POWER_330 0x0E
  89. /*
  90. * VDD2 - UHS2 or PCIe/NVMe
  91. * VDD2 power on/off and voltage select
  92. */
  93. #define SDHCI_VDD2_POWER_ON 0x10
  94. #define SDHCI_VDD2_POWER_120 0x80
  95. #define SDHCI_VDD2_POWER_180 0xA0
  96. #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  97. #define SDHCI_WAKE_UP_CONTROL 0x2B
  98. #define SDHCI_WAKE_ON_INT 0x01
  99. #define SDHCI_WAKE_ON_INSERT 0x02
  100. #define SDHCI_WAKE_ON_REMOVE 0x04
  101. #define SDHCI_CLOCK_CONTROL 0x2C
  102. #define SDHCI_DIVIDER_SHIFT 8
  103. #define SDHCI_DIVIDER_HI_SHIFT 6
  104. #define SDHCI_DIV_MASK 0xFF
  105. #define SDHCI_DIV_MASK_LEN 8
  106. #define SDHCI_DIV_HI_MASK 0x300
  107. #define SDHCI_PROG_CLOCK_MODE 0x0020
  108. #define SDHCI_CLOCK_CARD_EN 0x0004
  109. #define SDHCI_CLOCK_PLL_EN 0x0008
  110. #define SDHCI_CLOCK_INT_STABLE 0x0002
  111. #define SDHCI_CLOCK_INT_EN 0x0001
  112. #define SDHCI_TIMEOUT_CONTROL 0x2E
  113. #define SDHCI_SOFTWARE_RESET 0x2F
  114. #define SDHCI_RESET_ALL 0x01
  115. #define SDHCI_RESET_CMD 0x02
  116. #define SDHCI_RESET_DATA 0x04
  117. #define SDHCI_INT_STATUS 0x30
  118. #define SDHCI_INT_ENABLE 0x34
  119. #define SDHCI_SIGNAL_ENABLE 0x38
  120. #define SDHCI_INT_RESPONSE 0x00000001
  121. #define SDHCI_INT_DATA_END 0x00000002
  122. #define SDHCI_INT_BLK_GAP 0x00000004
  123. #define SDHCI_INT_DMA_END 0x00000008
  124. #define SDHCI_INT_SPACE_AVAIL 0x00000010
  125. #define SDHCI_INT_DATA_AVAIL 0x00000020
  126. #define SDHCI_INT_CARD_INSERT 0x00000040
  127. #define SDHCI_INT_CARD_REMOVE 0x00000080
  128. #define SDHCI_INT_CARD_INT 0x00000100
  129. #define SDHCI_INT_RETUNE 0x00001000
  130. #define SDHCI_INT_CQE 0x00004000
  131. #define SDHCI_INT_ERROR 0x00008000
  132. #define SDHCI_INT_TIMEOUT 0x00010000
  133. #define SDHCI_INT_CRC 0x00020000
  134. #define SDHCI_INT_END_BIT 0x00040000
  135. #define SDHCI_INT_INDEX 0x00080000
  136. #define SDHCI_INT_DATA_TIMEOUT 0x00100000
  137. #define SDHCI_INT_DATA_CRC 0x00200000
  138. #define SDHCI_INT_DATA_END_BIT 0x00400000
  139. #define SDHCI_INT_BUS_POWER 0x00800000
  140. #define SDHCI_INT_AUTO_CMD_ERR 0x01000000
  141. #define SDHCI_INT_ADMA_ERROR 0x02000000
  142. #define SDHCI_INT_NORMAL_MASK 0x00007FFF
  143. #define SDHCI_INT_ERROR_MASK 0xFFFF8000
  144. #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | SDHCI_INT_AUTO_CMD_ERR)
  145. #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | SDHCI_INT_BLK_GAP)
  146. #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
  147. #define SDHCI_CQE_INT_ERR_MASK ( \
  148. SDHCI_INT_ADMA_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)
  149. #define SDHCI_CQE_INT_MASK (SDHCI_CQE_INT_ERR_MASK | SDHCI_INT_CQE)
  150. #define SDHCI_AUTO_CMD_STATUS 0x3C
  151. #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
  152. #define SDHCI_AUTO_CMD_CRC 0x00000004
  153. #define SDHCI_AUTO_CMD_END_BIT 0x00000008
  154. #define SDHCI_AUTO_CMD_INDEX 0x00000010
  155. #define SDHCI_HOST_CONTROL2 0x3E
  156. #define SDHCI_CTRL_UHS_MASK 0x0007
  157. #define SDHCI_CTRL_UHS_SDR12 0x0000
  158. #define SDHCI_CTRL_UHS_SDR25 0x0001
  159. #define SDHCI_CTRL_UHS_SDR50 0x0002
  160. #define SDHCI_CTRL_UHS_SDR104 0x0003
  161. #define SDHCI_CTRL_UHS_DDR50 0x0004
  162. #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
  163. #define SDHCI_CTRL_VDD_180 0x0008
  164. #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
  165. #define SDHCI_CTRL_DRV_TYPE_B 0x0000
  166. #define SDHCI_CTRL_DRV_TYPE_A 0x0010
  167. #define SDHCI_CTRL_DRV_TYPE_C 0x0020
  168. #define SDHCI_CTRL_DRV_TYPE_D 0x0030
  169. #define SDHCI_CTRL_EXEC_TUNING 0x0040
  170. #define SDHCI_CTRL_TUNED_CLK 0x0080
  171. #define SDHCI_CMD23_ENABLE 0x0800
  172. #define SDHCI_CTRL_V4_MODE 0x1000
  173. #define SDHCI_CTRL_64BIT_ADDR 0x2000
  174. #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
  175. #define SDHCI_CAPABILITIES 0x40
  176. #define SDHCI_TIMEOUT_CLK_MASK RT_GENMASK(5, 0)
  177. #define SDHCI_TIMEOUT_CLK_SHIFT 0
  178. #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
  179. #define SDHCI_CLOCK_BASE_MASK RT_GENMASK(13, 8)
  180. #define SDHCI_CLOCK_BASE_SHIFT 8
  181. #define SDHCI_CLOCK_V3_BASE_MASK RT_GENMASK(15, 8)
  182. #define SDHCI_MAX_BLOCK_MASK 0x00030000
  183. #define SDHCI_MAX_BLOCK_SHIFT 16
  184. #define SDHCI_CAN_DO_8BIT 0x00040000
  185. #define SDHCI_CAN_DO_ADMA2 0x00080000
  186. #define SDHCI_CAN_DO_ADMA1 0x00100000
  187. #define SDHCI_CAN_DO_HISPD 0x00200000
  188. #define SDHCI_CAN_DO_SDMA 0x00400000
  189. #define SDHCI_CAN_DO_SUSPEND 0x00800000
  190. #define SDHCI_CAN_VDD_330 0x01000000
  191. #define SDHCI_CAN_VDD_300 0x02000000
  192. #define SDHCI_CAN_VDD_180 0x04000000
  193. #define SDHCI_CAN_64BIT_V4 0x08000000
  194. #define SDHCI_CAN_64BIT 0x10000000
  195. #define SDHCI_CAPABILITIES_1 0x44
  196. #define SDHCI_SUPPORT_SDR50 0x00000001
  197. #define SDHCI_SUPPORT_SDR104 0x00000002
  198. #define SDHCI_SUPPORT_DDR50 0x00000004
  199. #define SDHCI_DRIVER_TYPE_A 0x00000010
  200. #define SDHCI_DRIVER_TYPE_C 0x00000020
  201. #define SDHCI_DRIVER_TYPE_D 0x00000040
  202. #define SDHCI_RETUNING_TIMER_COUNT_MASK RT_GENMASK(11, 8)
  203. #define SDHCI_USE_SDR50_TUNING 0x00002000
  204. #define SDHCI_RETUNING_MODE_MASK RT_GENMASK(15, 14)
  205. #define SDHCI_CLOCK_MUL_MASK RT_GENMASK(23, 16)
  206. #define SDHCI_CAN_DO_ADMA3 0x08000000
  207. #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
  208. #define SDHCI_MAX_CURRENT 0x48
  209. #define SDHCI_MAX_CURRENT_LIMIT RT_GENMASK(7, 0)
  210. #define SDHCI_MAX_CURRENT_330_MASK RT_GENMASK(7, 0)
  211. #define SDHCI_MAX_CURRENT_300_MASK RT_GENMASK(15, 8)
  212. #define SDHCI_MAX_CURRENT_180_MASK RT_GENMASK(23, 16)
  213. #define SDHCI_MAX_CURRENT_MULTIPLIER 4
  214. /* 4C-4F reserved for more max current */
  215. #define SDHCI_SET_ACMD12_ERROR 0x50
  216. #define SDHCI_SET_INT_ERROR 0x52
  217. #define SDHCI_ADMA_ERROR 0x54
  218. /* 55-57 reserved */
  219. #define SDHCI_ADMA_ADDRESS 0x58
  220. #define SDHCI_ADMA_ADDRESS_HI 0x5C
  221. /* 60-FB reserved */
  222. #define SDHCI_PRESET_FOR_HIGH_SPEED 0x64
  223. #define SDHCI_PRESET_FOR_SDR12 0x66
  224. #define SDHCI_PRESET_FOR_SDR25 0x68
  225. #define SDHCI_PRESET_FOR_SDR50 0x6A
  226. #define SDHCI_PRESET_FOR_SDR104 0x6C
  227. #define SDHCI_PRESET_FOR_DDR50 0x6E
  228. #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
  229. #define SDHCI_PRESET_DRV_MASK RT_GENMASK(15, 14)
  230. #define BIT(nr) ((1) << (nr))
  231. #define SDHCI_PRESET_CLKGEN_SEL BIT(10)
  232. #define SDHCI_PRESET_SDCLK_FREQ_MASK RT_GENMASK(9, 0)
  233. #define SDHCI_SLOT_INT_STATUS 0xFC
  234. #define SDHCI_HOST_VERSION 0xFE
  235. #define SDHCI_VENDOR_VER_MASK 0xFF00
  236. #define SDHCI_VENDOR_VER_SHIFT 8
  237. #define SDHCI_SPEC_VER_MASK 0x00FF
  238. #define SDHCI_SPEC_VER_SHIFT 0
  239. #define SDHCI_SPEC_100 0
  240. #define SDHCI_SPEC_200 1
  241. #define SDHCI_SPEC_300 2
  242. #define SDHCI_SPEC_400 3
  243. #define SDHCI_SPEC_410 4
  244. #define SDHCI_SPEC_420 5
  245. /*
  246. * End of controller registers.
  247. */
  248. #define SDHCI_MAX_DIV_SPEC_200 256
  249. #define SDHCI_MAX_DIV_SPEC_300 2046
  250. /*
  251. * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
  252. */
  253. #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
  254. #define ilog2(v) __rt_ffs(v)
  255. #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
  256. /* ADMA2 32-bit DMA descriptor size */
  257. #define SDHCI_ADMA2_32_DESC_SZ 8
  258. /* ADMA2 32-bit descriptor */
  259. struct sdhci_adma2_32_desc
  260. {
  261. rt_uint16_t cmd;
  262. rt_uint16_t len;
  263. rt_uint16_t addr;
  264. } rt_align(4);
  265. /* ADMA2 data alignment */
  266. #define SDHCI_ADMA2_ALIGN 4
  267. #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
  268. /*
  269. * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte
  270. * alignment for the descriptor table even in 32-bit DMA mode. Memory
  271. * allocation is at least 8 byte aligned anyway, so just stipulate 8 always.
  272. */
  273. #define SDHCI_ADMA2_DESC_ALIGN 8
  274. /*
  275. * ADMA2 64-bit DMA descriptor size
  276. * According to SD Host Controller spec v4.10, there are two kinds of
  277. * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
  278. * Descriptor, if Host Version 4 Enable is set in the Host Control 2
  279. * register, 128-bit Descriptor will be selected.
  280. */
  281. #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
  282. /*
  283. * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
  284. * aligned.
  285. */
  286. struct sdhci_adma2_64_desc
  287. {
  288. rt_uint16_t cmd;
  289. rt_uint16_t len;
  290. rt_uint16_t addr_lo;
  291. rt_uint16_t addr_hi;
  292. };
  293. #define ADMA2_TRAN_VALID 0x21
  294. #define ADMA2_NOP_END_VALID 0x3
  295. #define ADMA2_END 0x2
  296. /*
  297. * Maximum segments assuming a 512KiB maximum requisition size and a minimum
  298. * 4KiB page size. Note this also allows enough for multiple descriptors in
  299. * case of PAGE_SIZE >= 64KiB.
  300. */
  301. #define SDHCI_MAX_SEGS 128
  302. /* Allow for a command request and a data request at the same time */
  303. #define SDHCI_MAX_MRQS 2
  304. /*
  305. * 48bit command and 136 bit response in 100KHz clock could take upto 2.48ms.
  306. * However since the start time of the command, the time between
  307. * command and response, and the time between response and start of data is
  308. * not known, set the command transfer time to 10ms.
  309. */
  310. #define MMC_CMD_TRANSFER_TIME (10 * 1000000L) /* max 10 ms */
  311. enum sdhci_cookie
  312. {
  313. COOKIE_UNMAPPED,
  314. COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
  315. COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */
  316. };
  317. struct sdhci_host
  318. {
  319. /* Data set by hardware interface driver */
  320. const char *hw_name; /* Hardware bus name */
  321. unsigned int quirks; /* Deviations from spec. */
  322. void *data_buf;
  323. /* Controller doesn't honor resets unless we touch the clock register */
  324. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0)
  325. /* Controller has bad caps bits, but really supports DMA */
  326. #define SDHCI_QUIRK_FORCE_DMA (1 << 1)
  327. /* Controller doesn't like to be reset when there is no card inserted. */
  328. #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 2)
  329. /* Controller doesn't like clearing the power reg before a change */
  330. #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1 << 3)
  331. /* Controller has an unusable DMA engine */
  332. #define SDHCI_QUIRK_BROKEN_DMA (1 << 5)
  333. /* Controller has an unusable ADMA engine */
  334. #define SDHCI_QUIRK_BROKEN_ADMA (1 << 6)
  335. /* Controller can only DMA from 32-bit aligned addresses */
  336. #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 7)
  337. /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
  338. #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 8)
  339. /* Controller can only ADMA chunks that are a multiple of 32 bits */
  340. #define SDHCI_QUIRK_32BIT_ADMA_SIZE (1 << 9)
  341. /* Controller needs to be reset after each request to stay stable */
  342. #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 10)
  343. /* Controller needs voltage and power writes to happen separately */
  344. #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 11)
  345. /* Controller provides an incorrect timeout value for transfers */
  346. #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 12)
  347. /* Controller has an issue with buffer bits for small transfers */
  348. #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1 << 13)
  349. /* Controller does not provide transfer-complete interrupt when not busy */
  350. #define SDHCI_QUIRK_NO_BUSY_IRQ (1 << 14)
  351. /* Controller has unreliable card detection */
  352. #define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1 << 15)
  353. /* Controller reports inverted write-protect state */
  354. #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1 << 16)
  355. /* Controller has unusable command queue engine */
  356. #define SDHCI_QUIRK_BROKEN_CQE (1 << 17)
  357. /* Controller does not like fast PIO transfers */
  358. #define SDHCI_QUIRK_PIO_NEEDS_DELAY (1 << 18)
  359. /* Controller does not have a LED */
  360. #define SDHCI_QUIRK_NO_LED (1 << 19)
  361. /* Controller has to be forced to use block size of 2048 bytes */
  362. #define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1 << 20)
  363. /* Controller cannot do multi-block transfers */
  364. #define SDHCI_QUIRK_NO_MULTIBLOCK (1 << 21)
  365. /* Controller can only handle 1-bit data transfers */
  366. #define SDHCI_QUIRK_FORCE_1_BIT_DATA (1 << 22)
  367. /* Controller needs 10ms delay between applying power and clock */
  368. #define SDHCI_QUIRK_DELAY_AFTER_POWER (1 << 23)
  369. /* Controller uses SDCLK instead of TMCLK for data timeouts */
  370. #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 24)
  371. /* Controller reports wrong base clock capability */
  372. #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1 << 25)
  373. /* Controller cannot support End Attribute in NOP ADMA descriptor */
  374. #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1 << 26)
  375. /* Controller uses Auto CMD12 command to stop the transfer */
  376. #define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1 << 28)
  377. /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
  378. #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 29)
  379. /* Controller treats ADMA descriptors with length 0000h incorrectly */
  380. #define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1 << 30)
  381. /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
  382. #define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1 << 31)
  383. unsigned int quirks2; /* More deviations from spec. */
  384. #define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1 << 0)
  385. #define SDHCI_QUIRK2_HOST_NO_CMD23 (1 << 1)
  386. /* The system physically doesn't support 1.8v, even if the host does */
  387. #define SDHCI_QUIRK2_NO_1_8_V (1 << 2)
  388. #define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1 << 3)
  389. #define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1 << 4)
  390. /* Controller has a non-standard host control register */
  391. #define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1 << 5)
  392. /* Controller does not support HS200 */
  393. #define SDHCI_QUIRK2_BROKEN_HS200 (1 << 6)
  394. /* Controller does not support DDR50 */
  395. #define SDHCI_QUIRK2_BROKEN_DDR50 (1 << 7)
  396. /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
  397. #define SDHCI_QUIRK2_STOP_WITH_TC (1 << 8)
  398. /* Controller does not support 64-bit DMA */
  399. #define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1 << 9)
  400. /* need clear transfer mode register before send cmd */
  401. #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1 << 10)
  402. /* Capability register bit-63 indicates HS400 support */
  403. #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1 << 11)
  404. /* forced tuned clock */
  405. #define SDHCI_QUIRK2_TUNING_WORK_AROUND (1 << 12)
  406. /* disable the block count for single block transactions */
  407. #define SDHCI_QUIRK2_SUPPORT_SINGLE (1 << 13)
  408. /* Controller broken with using ACMD23 */
  409. #define SDHCI_QUIRK2_ACMD23_BROKEN (1 << 14)
  410. /* Broken Clock divider zero in controller */
  411. #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1 << 15)
  412. /* Controller has CRC in 136 bit Command Response */
  413. #define SDHCI_QUIRK2_RSP_136_HAS_CRC (1 << 16)
  414. /*
  415. * Disable HW timeout if the requested timeout is more than the maximum
  416. * obtainable timeout.
  417. */
  418. #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1 << 17)
  419. /*
  420. * 32-bit block count may not support eMMC where upper bits of CMD23 are used
  421. * for other purposes. Consequently we support 16-bit block count by default.
  422. * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
  423. * block count.
  424. */
  425. #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1 << 18)
  426. /* Issue CMD and DATA reset together */
  427. #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1 << 19)
  428. int irq; /* Device IRQ */
  429. void *ioaddr; /* Mapped address */
  430. char *bounce_buffer; /* For packing SDMA reads/writes */
  431. rt_uint64_t bounce_addr;
  432. unsigned int bounce_buffer_size;
  433. const struct sdhci_ops *ops; /* Low level hw interface */
  434. /* Internal data */
  435. struct mmc_host *mmc; /* MMC structure */
  436. struct mmc_host_ops mmc_host_ops; /* MMC host ops */
  437. rt_uint64_t dma_mask; /* custom DMA mask */
  438. rt_spinlock_t lock;
  439. int flags; /* Host attributes */
  440. #define SDHCI_USE_SDMA (1 << 0) /* Host is SDMA capable */
  441. #define SDHCI_USE_ADMA (1 << 1) /* Host is ADMA capable */
  442. #define SDHCI_REQ_USE_DMA (1 << 2) /* Use DMA for this req. */
  443. #define SDHCI_DEVICE_DEAD (1 << 3) /* Device unresponsive */
  444. #define SDHCI_SDR50_NEEDS_TUNING (1 << 4) /* SDR50 needs tuning */
  445. #define SDHCI_AUTO_CMD12 (1 << 6) /* Auto CMD12 support */
  446. #define SDHCI_AUTO_CMD23 (1 << 7) /* Auto CMD23 support */
  447. #define SDHCI_PV_ENABLED (1 << 8) /* Preset value enabled */
  448. #define SDHCI_USE_64_BIT_DMA (1 << 12) /* Use 64-bit DMA */
  449. #define SDHCI_HS400_TUNING (1 << 13) /* Tuning for HS400 */
  450. #define SDHCI_SIGNALING_330 (1 << 14) /* Host is capable of 3.3V signaling */
  451. #define SDHCI_SIGNALING_180 (1 << 15) /* Host is capable of 1.8V signaling */
  452. #define SDHCI_SIGNALING_120 (1 << 16) /* Host is capable of 1.2V signaling */
  453. unsigned int version; /* SDHCI spec. version */
  454. unsigned int max_clk; /* Max possible freq (MHz) */
  455. unsigned int timeout_clk; /* Timeout freq (KHz) */
  456. rt_uint8_t max_timeout_count; /* Vendor specific max timeout count */
  457. unsigned int clk_mul; /* Clock Muliplier value */
  458. unsigned int clock; /* Current clock (MHz) */
  459. rt_uint8_t pwr; /* Current voltage */
  460. rt_uint8_t drv_type; /* Current UHS-I driver type */
  461. rt_bool_t reinit_uhs; /* Force UHS-related re-initialization */
  462. rt_bool_t runtime_suspended; /* Host is runtime suspended */
  463. rt_bool_t bus_on; /* Bus power prevents runtime suspend */
  464. rt_bool_t preset_enabled; /* Preset is enabled */
  465. rt_bool_t pending_reset; /* Cmd/data reset is pending */
  466. rt_bool_t irq_wake_enabled; /* IRQ wakeup is enabled */
  467. rt_bool_t v4_mode; /* Host Version 4 Enable */
  468. rt_bool_t use_external_dma; /* Host selects to use external DMA */
  469. rt_bool_t always_defer_done; /* Always defer to complete requests */
  470. struct rt_mmcsd_req *mrqs_done[SDHCI_MAX_MRQS]; /* Requests done */
  471. struct rt_mmcsd_cmd *cmd; /* Current command */
  472. struct rt_mmcsd_cmd *data_cmd; /* Current data command */
  473. struct rt_mmcsd_cmd *deferred_cmd; /* Deferred command */
  474. struct rt_mmcsd_data *data; /* Current data request */
  475. unsigned int data_early : 1; /* Data finished before cmd */
  476. unsigned int blocks; /* remaining PIO blocks */
  477. int sg_count; /* Mapped sg entries */
  478. int max_adma; /* Max. length in ADMA descriptor */
  479. void *adma_table; /* ADMA descriptor table */
  480. void *align_buffer; /* Bounce buffer */
  481. size_t adma_table_sz; /* ADMA descriptor table size */
  482. size_t align_buffer_sz; /* Bounce buffer size */
  483. rt_uint64_t adma_addr; /* Mapped ADMA descr. table */
  484. rt_uint64_t align_addr; /* Mapped bounce buffer */
  485. unsigned int desc_sz; /* ADMA current descriptor size */
  486. unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
  487. struct rt_workqueue *complete_wq; /* Request completion wq */
  488. struct rt_work complete_work; /* Request completion work */
  489. struct rt_workqueue *irq_wq;
  490. struct rt_work irq_work;
  491. struct rt_timer timer; /* Timer for timeouts */
  492. struct rt_timer data_timer; /* Timer for data timeouts */
  493. rt_uint32_t caps; /* CAPABILITY_0 */
  494. rt_uint32_t caps1; /* CAPABILITY_1 */
  495. rt_bool_t read_caps; /* Capability flags have been read */
  496. rt_bool_t sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */
  497. unsigned int ocr_avail_sdio; /* OCR bit masks */
  498. unsigned int ocr_avail_sd;
  499. unsigned int ocr_avail_mmc;
  500. rt_uint32_t ocr_mask; /* available voltages */
  501. unsigned timing; /* Current timing */
  502. rt_uint32_t thread_isr;
  503. /* cached registers */
  504. rt_uint32_t ier;
  505. rt_bool_t cqe_on; /* CQE is operating */
  506. rt_uint32_t cqe_ier; /* CQE interrupt mask */
  507. rt_uint32_t cqe_err_ier; /* CQE error interrupt mask */
  508. rt_wqueue_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
  509. unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
  510. unsigned int tuning_count; /* Timer count for re-tuning */
  511. unsigned int tuning_mode; /* Re-tuning mode supported by host */
  512. unsigned int tuning_err; /* Error code for re-tuning */
  513. #define SDHCI_TUNING_MODE_1 0
  514. #define SDHCI_TUNING_MODE_2 1
  515. #define SDHCI_TUNING_MODE_3 2
  516. /* Delay (ms) between tuning commands */
  517. int tuning_delay;
  518. int tuning_loop_count;
  519. /* Host SDMA buffer boundary. */
  520. rt_uint32_t sdma_boundary;
  521. /* Host ADMA table count */
  522. rt_uint32_t adma_table_cnt;
  523. rt_uint64_t data_timeout;
  524. unsigned long private[];
  525. };
  526. struct sdhci_ops
  527. {
  528. rt_uint32_t (*read_l)(struct sdhci_host *host, int reg);
  529. rt_uint16_t (*read_w)(struct sdhci_host *host, int reg);
  530. rt_uint8_t (*read_b)(struct sdhci_host *host, int reg);
  531. void (*write_l)(struct sdhci_host *host, rt_uint32_t val, int reg);
  532. void (*write_w)(struct sdhci_host *host, rt_uint16_t val, int reg);
  533. void (*write_b)(struct sdhci_host *host, rt_uint8_t val, int reg);
  534. void (*set_clock)(struct sdhci_host *host, unsigned int clock);
  535. void (*set_power)(struct sdhci_host *host, unsigned char mode,
  536. unsigned short vdd);
  537. rt_uint32_t (*irq)(struct sdhci_host *host, rt_uint32_t intmask);
  538. int (*set_dma_mask)(struct sdhci_host *host);
  539. int (*enable_dma)(struct sdhci_host *host);
  540. unsigned int (*get_max_clock)(struct sdhci_host *host);
  541. unsigned int (*get_min_clock)(struct sdhci_host *host);
  542. /* get_timeout_clock should return clk rate in unit of Hz */
  543. unsigned int (*get_timeout_clock)(struct sdhci_host *host);
  544. unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
  545. void (*set_timeout)(struct sdhci_host *host,
  546. struct rt_mmcsd_cmd *cmd);
  547. void (*set_bus_width)(struct sdhci_host *host, int width);
  548. void (*platform_send_init_74_clocks)(struct sdhci_host *host,
  549. rt_uint8_t power_mode);
  550. unsigned int (*get_ro)(struct sdhci_host *host);
  551. void (*reset)(struct sdhci_host *host, rt_uint8_t mask);
  552. int (*platform_execute_tuning)(struct sdhci_host *host, rt_uint32_t opcode);
  553. void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
  554. void (*hw_reset)(struct sdhci_host *host);
  555. void (*adma_workaround)(struct sdhci_host *host, rt_uint32_t intmask);
  556. void (*card_event)(struct sdhci_host *host);
  557. void (*voltage_switch)(struct sdhci_host *host);
  558. void (*adma_write_desc)(struct sdhci_host *host, void **desc,
  559. rt_uint64_t addr, int len, unsigned int cmd);
  560. void (*copy_to_bounce_buffer)(struct sdhci_host *host,
  561. struct rt_mmcsd_data *data,
  562. unsigned int length);
  563. void (*request_done)(struct sdhci_host *host,
  564. struct rt_mmcsd_req *mrq);
  565. void (*dump_vendor_regs)(struct sdhci_host *host);
  566. };
  567. static inline rt_uint8_t rt_uint8_t_read(const volatile void *addr)
  568. {
  569. return *(const volatile rt_uint8_t *)addr;
  570. }
  571. static inline rt_uint16_t rt_uint16_t_read(const volatile void *addr)
  572. {
  573. return *(const volatile rt_uint16_t *)addr;
  574. }
  575. static inline rt_uint32_t rt_uint32_t_read(const volatile void *addr)
  576. {
  577. return *(const volatile rt_uint32_t *)addr;
  578. }
  579. static inline void rt_uint8_t_write(rt_uint8_t value, volatile void *addr)
  580. {
  581. *(volatile rt_uint8_t *)addr = value;
  582. }
  583. static inline void rt_uint16_t_write(rt_uint16_t value, volatile void *addr)
  584. {
  585. *(volatile rt_uint16_t *)addr = value;
  586. }
  587. static inline void rt_uint32_t_write(rt_uint32_t value, volatile void *addr)
  588. {
  589. *(volatile rt_uint32_t *)addr = value;
  590. }
  591. #define readb(c) rt_uint8_t_read(c)
  592. #define readw(c) rt_uint16_t_read(c)
  593. #define readl(c) rt_uint32_t_read(c)
  594. #define readsb(p, d, l) ({ __raw_readsb(p,d,l); __iormb(); })
  595. #define readsw(p, d, l) ({ __raw_readsw(p,d,l); __iormb(); })
  596. #define readsl(p, d, l) ({ __raw_readsl(p,d,l); __iormb(); })
  597. #define writeb(v, c) rt_uint8_t_write(v, c)
  598. #define writew(v, c) rt_uint16_t_write(v, c)
  599. #define writel(v, c) rt_uint32_t_write(v, c)
  600. #define writesb(p, d, l) ({ __iowmb(); __raw_writesb(p,d,l); })
  601. #define writesw(p, d, l) ({ __iowmb(); __raw_writesw(p,d,l); })
  602. #define writesl(p, d, l) ({ __iowmb(); __raw_writesl(p,d,l); })
  603. static inline void sdhci_writel(struct sdhci_host *host, rt_uint32_t val, int reg)
  604. {
  605. if (host->ops->write_l)
  606. host->ops->write_l(host, val, reg);
  607. else
  608. writel(val, host->ioaddr + reg);
  609. }
  610. static inline void sdhci_writew(struct sdhci_host *host, rt_uint16_t val, int reg)
  611. {
  612. if (host->ops->write_w)
  613. host->ops->write_w(host, val, reg);
  614. else
  615. writew(val, host->ioaddr + reg);
  616. }
  617. static inline void sdhci_writeb(struct sdhci_host *host, rt_uint8_t val, int reg)
  618. {
  619. if (host->ops->write_b)
  620. host->ops->write_b(host, val, reg);
  621. else
  622. writeb(val, host->ioaddr + reg);
  623. }
  624. static inline rt_uint32_t sdhci_readl(struct sdhci_host *host, int reg)
  625. {
  626. if (host->ops->read_l)
  627. return host->ops->read_l(host, reg);
  628. else
  629. return readl(host->ioaddr + reg);
  630. }
  631. static inline rt_uint16_t sdhci_readw(struct sdhci_host *host, int reg)
  632. {
  633. if (host->ops->read_w)
  634. return host->ops->read_w(host, reg);
  635. else
  636. return readw(host->ioaddr + reg);
  637. }
  638. static inline rt_uint8_t sdhci_readb(struct sdhci_host *host, int reg)
  639. {
  640. if (host->ops->read_b)
  641. return host->ops->read_b(host, reg);
  642. else
  643. return readb(host->ioaddr + reg);
  644. }
  645. struct sdhci_host *sdhci_alloc_host(struct rt_device *dev, size_t priv_size);
  646. void sdhci_free_host(struct sdhci_host *host);
  647. static inline void *sdhci_priv(struct sdhci_host *host)
  648. {
  649. return host->private;
  650. }
  651. void __sdhci_read_caps(struct sdhci_host *host, const rt_uint16_t *ver,
  652. const rt_uint32_t *caps, const rt_uint32_t *caps1);
  653. int sdhci_setup_host(struct sdhci_host *host);
  654. void sdhci_cleanup_host(struct sdhci_host *host);
  655. int __sdhci_add_host(struct sdhci_host *host);
  656. int sdhci_add_host(struct sdhci_host *host);
  657. void sdhci_remove_host(struct sdhci_host *host, int dead);
  658. static inline void sdhci_read_caps(struct sdhci_host *host)
  659. {
  660. __sdhci_read_caps(host, NULL, NULL, NULL);
  661. }
  662. rt_uint16_t sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
  663. unsigned int *actual_clock);
  664. void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
  665. void sdhci_enable_clk(struct sdhci_host *host, rt_uint16_t clk);
  666. void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
  667. unsigned short vdd);
  668. void sdhci_set_power_and_bus_voltage(struct sdhci_host *host,
  669. unsigned char mode,
  670. unsigned short vdd);
  671. void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
  672. unsigned short vdd);
  673. int sdhci_get_cd_nogpio(struct mmc_host *mmc);
  674. void sdhci_request(struct mmc_host *mmc, struct rt_mmcsd_req *mrq);
  675. int sdhci_request_atomic(struct mmc_host *mmc, struct rt_mmcsd_req *mrq);
  676. void sdhci_set_bus_width(struct sdhci_host *host, int width);
  677. void sdhci_reset(struct sdhci_host *host, rt_uint8_t mask);
  678. void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing);
  679. int sdhci_execute_tuning(struct mmc_host *mmc, rt_uint32_t opcode);
  680. int __sdhci_execute_tuning(struct sdhci_host *host, rt_uint32_t opcode);
  681. void sdhci_set_ios(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
  682. int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
  683. struct rt_mmcsd_io_cfg *ios);
  684. void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
  685. void sdhci_adma_write_desc(struct sdhci_host *host, void **desc,
  686. rt_uint64_t addr, int len, unsigned int cmd);
  687. void sdhci_cqe_enable(struct mmc_host *mmc);
  688. void sdhci_cqe_disable(struct mmc_host *mmc, rt_bool_t recovery);
  689. rt_bool_t sdhci_cqe_irq(struct sdhci_host *host, rt_uint32_t intmask, int *cmd_error,
  690. int *data_error);
  691. void sdhci_dumpregs(struct sdhci_host *host);
  692. void sdhci_enable_v4_mode(struct sdhci_host *host);
  693. void sdhci_start_tuning(struct sdhci_host *host);
  694. void sdhci_end_tuning(struct sdhci_host *host);
  695. void sdhci_reset_tuning(struct sdhci_host *host);
  696. void sdhci_send_tuning(struct sdhci_host *host, rt_uint32_t opcode);
  697. void sdhci_abort_tuning(struct sdhci_host *host, rt_uint32_t opcode);
  698. void sdhci_switch_external_dma(struct sdhci_host *host, rt_bool_t en);
  699. void sdhci_set_data_timeout_irq(struct sdhci_host *host, rt_bool_t enable);
  700. void __sdhci_set_timeout(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd);
  701. #endif /* __SDHCI_HW_H */