sdhci_host.h 14 KB

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  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-16 zhujiale first version
  9. */
  10. #ifndef __SDHCI_MMC_H__
  11. #define __SDHCI_MMC_H__
  12. #include <rtthread.h>
  13. #include <drivers/mmcsd_cmd.h>
  14. #include <drivers/dev_mmcsd_core.h>
  15. #include <drivers/mmcsd_host.h>
  16. #include "sdhci_dma.h"
  17. #define mmc_dev(x) ((x)->parent)
  18. #define MMC_SEND_TUNING_BLOCK_HS200 SEND_TUNING_BLOCK_HS200
  19. #define MMC_SEND_TUNING_BLOCK SEND_TUNING_BLOCK
  20. #define MMC_STOP_TRANSMISSION STOP_TRANSMISSION
  21. #define MMC_BUS_TEST_R 14 /* adtc R1 */
  22. #define MMC_WRITE_MULTIPLE_BLOCK WRITE_MULTIPLE_BLOCK
  23. #define MMC_READ_MULTIPLE_BLOCK READ_MULTIPLE_BLOCK
  24. #define MMC_TIMING_UHS_DDR50 MMCSD_TIMING_UHS_DDR50
  25. #define MMC_TIMING_UHS_SDR50 MMCSD_TIMING_UHS_SDR50
  26. #define MMC_TIMING_MMC_HS200 MMCSD_TIMING_MMC_HS200
  27. #define MMC_TIMING_MMC_HS400 MMCSD_TIMING_MMC_HS400
  28. #define MMC_TIMING_UHS_SDR104 MMCSD_TIMING_UHS_SDR104
  29. #define MMC_TIMING_UHS_SDR25 MMCSD_TIMING_UHS_SDR25
  30. #define MMC_TIMING_MMC_DDR52 MMCSD_TIMING_MMC_DDR52
  31. #define MMC_TIMING_UHS_SDR12 MMCSD_TIMING_UHS_SDR12
  32. #define MMC_TIMING_SD_HS MMCSD_TIMING_SD_HS
  33. #define MMC_TIMING_MMC_HS MMCSD_TIMING_MMC_HS
  34. #define MMC_POWER_OFF MMCSD_POWER_OFF
  35. #define MMC_POWER_UP MMCSD_POWER_UP
  36. #define MMC_POWER_ON MMCSD_POWER_ON
  37. #define MMC_POWER_UNDEFINED 3
  38. #define MMC_SET_DRIVER_TYPE_B 0
  39. #define MMC_SET_DRIVER_TYPE_A 1
  40. #define MMC_SET_DRIVER_TYPE_C 2
  41. #define MMC_SET_DRIVER_TYPE_D 3
  42. #define MMC_SIGNAL_VOLTAGE_330 0
  43. #define MMC_SIGNAL_VOLTAGE_180 1
  44. #define MMC_SIGNAL_VOLTAGE_120 2
  45. #define MMC_RSP_PRESENT (1 << 16)
  46. #define MMC_RSP_136 (1 << 17) /* 136 bit response */
  47. #define MMC_RSP_CRC (1 << 18) /* expect valid crc */
  48. #define MMC_RSP_BUSY (1 << 19) /* card may send busy */
  49. #define MMC_RSP_OPCODE (1 << 20) /* response contains opcode */
  50. /*
  51. * These are the native response types, and correspond to valid bit
  52. * patterns of the above flags. One additional valid pattern
  53. * is all zeros, which means we don't expect a response.
  54. */
  55. #define MMC_RSP_NONE (0)
  56. #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
  57. #define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
  58. #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
  59. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  60. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  61. #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
  62. #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
  63. #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
  64. #define MMC_CMD_ADTC CMD_ADTC
  65. #define MMC_BUS_WIDTH_8 MMCSD_BUS_WIDTH_8
  66. #define MMC_BUS_WIDTH_4 MMCSD_BUS_WIDTH_4
  67. #define MMC_BUS_WIDTH_1 MMCSD_BUS_WIDTH_1
  68. #define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */
  69. #define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */
  70. enum mmc_blk_status
  71. {
  72. MMC_BLK_SUCCESS = 0,
  73. MMC_BLK_PARTIAL,
  74. MMC_BLK_CMD_ERR,
  75. MMC_BLK_RETRY,
  76. MMC_BLK_ABORT,
  77. MMC_BLK_DATA_ERR,
  78. MMC_BLK_ECC_ERR,
  79. MMC_BLK_NOMEDIUM,
  80. MMC_BLK_NEW_REQUEST,
  81. };
  82. /************************************************************************************************ */
  83. #define MMC_NUM_CLK_PHASES (MMC_TIMING_MMC_HS400 + 1)
  84. struct mmc_host;
  85. struct mmc_host_ops
  86. {
  87. /*
  88. * It is optional for the host to implement pre_req and post_req in
  89. * order to support double buffering of requests (prepare one
  90. * request while another request is active).
  91. * pre_req() must always be followed by a post_req().
  92. * To undo a call made to pre_req(), call post_req() with
  93. * a nonzero err condition.
  94. */
  95. void (*post_req)(struct mmc_host *host, struct rt_mmcsd_req *req,
  96. int err);
  97. void (*pre_req)(struct mmc_host *host, struct rt_mmcsd_req *req);
  98. void (*request)(struct mmc_host *host, struct rt_mmcsd_req *req);
  99. /*
  100. * Avoid calling the next three functions too often or in a "fast
  101. * path", since underlaying controller might implement them in an
  102. * expensive and/or slow way. Also note that these functions might
  103. * sleep, so don't call them in the atomic contexts!
  104. */
  105. /*
  106. * Notes to the set_ios callback:
  107. * ios->clock might be 0. For some controllers, setting 0Hz
  108. * as any other frequency works. However, some controllers
  109. * explicitly need to disable the clock. Otherwise e.g. voltage
  110. * switching might fail because the SDCLK is not really quiet.
  111. */
  112. void (*set_ios)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
  113. /*
  114. * Return values for the get_ro callback should be:
  115. * 0 for a read/write card
  116. * 1 for a read-only card
  117. * -ENOSYS when not supported (equal to NULL callback)
  118. * or a negative errno value when something bad happened
  119. */
  120. int (*get_ro)(struct mmc_host *host);
  121. /*
  122. * Return values for the get_cd callback should be:
  123. * 0 for a absent card
  124. * 1 for a present card
  125. * -ENOSYS when not supported (equal to NULL callback)
  126. * or a negative errno value when something bad happened
  127. */
  128. int (*get_cd)(struct mmc_host *host);
  129. void (*enable_sdio_irq)(struct mmc_host *host, int enable);
  130. /* Mandatory callback when using MMC_CAP2_SDIO_IRQ_NOTHREAD. */
  131. void (*ack_sdio_irq)(struct mmc_host *host);
  132. int (*start_signal_voltage_switch)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
  133. /* Check if the card is pulling dat[0:3] low */
  134. int (*card_busy)(struct mmc_host *host);
  135. /* The tuning command opcode value is different for SD and eMMC cards */
  136. int (*execute_tuning)(struct mmc_host *host, unsigned opcode);
  137. /* Prepare HS400 target operating frequency depending host driver */
  138. int (*prepare_hs400_tuning)(struct mmc_host *host, struct rt_mmcsd_io_cfg *ios);
  139. /* Prepare switch to DDR during the HS400 init sequence */
  140. int (*hs400_prepare_ddr)(struct mmc_host *host);
  141. /* Prepare for switching from HS400 to HS200 */
  142. void (*hs400_downgrade)(struct mmc_host *host);
  143. /* Complete selection of HS400 */
  144. void (*hs400_complete)(struct mmc_host *host);
  145. /* Prepare enhanced strobe depending host driver */
  146. void (*hs400_enhanced_strobe)(struct mmc_host *host,
  147. struct rt_mmcsd_io_cfg *ios);
  148. /* Reset the eMMC card via RST_n */
  149. void (*hw_reset)(struct mmc_host *host);
  150. void (*card_event)(struct mmc_host *host);
  151. };
  152. struct regulator;
  153. struct mmc_pwrseq;
  154. struct mmc_supply
  155. {
  156. struct regulator *vmmc; /* Card power supply */
  157. struct regulator *vqmmc; /* Optional Vccq supply */
  158. };
  159. struct mmc_ctx
  160. {
  161. struct task_struct *task;
  162. };
  163. /* VDD voltage 3.3 ~ 3.4 */
  164. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  165. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  166. #define MMC_CAP2_HS200_1_8V_SDR MMCSD_SUP_HS200_1V8
  167. #define MMC_CAP_4_BIT_DATA MMCSD_BUSWIDTH_4
  168. #define MMC_CAP_8_BIT_DATA MMCSD_BUSWIDTH_8
  169. #define MMC_CAP2_HS200 MMCSD_SUP_HS200
  170. #define MMC_CAP_MMC_HIGHSPEED MMCSD_SUP_HIGHSPEED
  171. #define MMC_CAP_SD_HIGHSPEED MMCSD_SUP_HIGHSPEED
  172. #define MMC_CAP_1_8V_DDR MMCSD_SUP_DDR_1V8
  173. #define MMC_CAP_3_3V_DDR MMCSD_SUP_DDR_3V3
  174. #define MMC_CAP_1_2V_DDR MMCSD_SUP_DDR_1V2
  175. #define MMC_CAP_NONREMOVABLE MMCSD_SUP_NONREMOVABLE
  176. #define MMC_CAP_UHS_DDR50 0
  177. #define MMC_CAP2_HS400 0
  178. #define MMC_CAP_UHS_SDR50 0
  179. #define MMC_CAP_UHS_SDR25 0
  180. #define MMC_CAP_UHS_SDR12 0
  181. #define MMC_CAP_UHS_SDR104 0
  182. #define MMC_CAP_UHS 0
  183. #define MMC_CAP2_HSX00_1_8V 0
  184. #define MMC_CAP2_HS400_ES 0
  185. #define MMC_CAP_NEEDS_POLL 0
  186. #define MMC_CAP2_HSX00_1_2V 0
  187. #define MMC_CAP2_HS400_1_8V 0
  188. #define MMC_CAP_DRIVER_TYPE_D 0
  189. #define MMC_CAP_DRIVER_TYPE_C 0
  190. #define MMC_SET_DRIVER_TYPE_B 0
  191. #define MMC_CAP_DRIVER_TYPE_A 0
  192. #define MMC_CAP2_SDIO_IRQ_NOTHREAD 0
  193. #define MMC_CAP_CMD23 0
  194. #define MMC_CAP_SDIO_IRQ 0
  195. #define MMC_CAP2_NO_SDIO (1 << 19)
  196. #define MMC_CAP2_NO_SD (1 << 21)
  197. #define MMC_CAP2_NO_MMC (1 << 22)
  198. #define MMC_CAP2_CQE (1 << 23)
  199. #define MMC_VDD_165_195 VDD_165_195
  200. #define MMC_VDD_20_21 VDD_20_21
  201. #define MMC_VDD_29_30 VDD_29_30
  202. #define MMC_VDD_30_31 VDD_30_31
  203. #define MMC_VDD_32_33 VDD_32_33
  204. #define MMC_VDD_33_34 VDD_33_34
  205. struct mmc_host
  206. {
  207. struct rt_mmcsd_host rthost;
  208. struct rt_device *parent;
  209. int index;
  210. const struct mmc_host_ops *ops;
  211. unsigned int f_min;
  212. unsigned int f_max;
  213. unsigned int f_init;
  214. rt_uint32_t ocr_avail;
  215. rt_uint32_t ocr_avail_sdio; /* SDIO-specific OCR */
  216. rt_uint32_t ocr_avail_sd; /* SD-specific OCR */
  217. rt_uint32_t ocr_avail_mmc; /* MMC-specific OCR */
  218. struct wakeup_source *ws; /* Enable consume of uevents */
  219. rt_uint32_t max_current_330;
  220. rt_uint32_t max_current_300;
  221. rt_uint32_t max_current_180;
  222. rt_uint32_t caps; /* Host capabilities */
  223. rt_uint32_t caps2; /* More host capabilities */
  224. /* host specific block data */
  225. unsigned int max_seg_size; /* see blk_queue_max_segment_size */
  226. unsigned short max_segs; /* see blk_queue_max_segments */
  227. unsigned short unused;
  228. unsigned int max_req_size; /* maximum number of bytes in one req */
  229. unsigned int max_blk_size; /* maximum size of one mmc block */
  230. unsigned int max_blk_count; /* maximum number of blocks in one req */
  231. unsigned int max_busy_timeout; /* max busy timeout in ms */
  232. struct rt_mmcsd_io_cfg ios; /* current io bus settings */
  233. unsigned int retune_period;
  234. /* group bitfields together to minimize padding */
  235. unsigned int use_spi_crc : 1;
  236. unsigned int claimed : 1; /* host exclusively claimed */
  237. unsigned int doing_init_tune : 1; /* initial tuning in progress */
  238. unsigned int can_retune : 1; /* re-tuning can be used */
  239. unsigned int doing_retune : 1; /* re-tuning in progress */
  240. unsigned int retune_now : 1; /* do re-tuning at next req */
  241. unsigned int retune_paused : 1; /* re-tuning is temporarily disabled */
  242. unsigned int retune_crc_disable : 1; /* don't trigger retune upon crc */
  243. unsigned int can_dma_map_merge : 1; /* merging can be used */
  244. unsigned int vqmmc_enabled : 1; /* vqmmc regulator is enabled */
  245. int need_retune; /* re-tuning is needed */
  246. int hold_retune; /* hold off re-tuning */
  247. rt_bool_t trigger_card_event; /* card_event necessary */
  248. unsigned int sdio_irqs;
  249. rt_bool_t sdio_irq_pending;
  250. struct led_trigger *led; /* activity led */
  251. struct mmc_supply supply;
  252. /* Ongoing data transfer that allows commands during transfer */
  253. struct rt_mmcsd_req *ongoing_mrq;
  254. unsigned int actual_clock; /* Actual HC clock rate */
  255. rt_uint32_t pm_caps;
  256. unsigned long private[];
  257. };
  258. static inline int mmc_card_is_removable(struct mmc_host *host)
  259. {
  260. return !(host->caps & MMC_CAP_NONREMOVABLE);
  261. }
  262. struct device_node;
  263. struct mmc_host *mmc_alloc_host(int extra, struct rt_device *);
  264. int mmc_add_host(struct mmc_host *);
  265. void mmc_remove_host(struct mmc_host *);
  266. void mmc_free_host(struct mmc_host *);
  267. int mmc_of_parse(struct mmc_host *host);
  268. int mmc_of_parse_voltage(struct mmc_host *host, rt_uint32_t *mask);
  269. static inline void *mmc_priv(struct mmc_host *host)
  270. {
  271. return (void *)host->private;
  272. }
  273. #define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
  274. #define mmc_dev(x) ((x)->parent)
  275. #define mmc_classdev(x) (&(x)->class_dev)
  276. #define mmc_hostname(x) (x->parent->parent.name)
  277. void mmc_detect_change(struct mmc_host *, unsigned long delay);
  278. void mmc_request_done(struct mmc_host *, struct rt_mmcsd_req *);
  279. void mmc_command_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
  280. void mmc_cqe_request_done(struct mmc_host *host, struct rt_mmcsd_req *mrq);
  281. /*
  282. * May be called from host driver's system/runtime suspend/resume callbacks,
  283. * to know if SDIO IRQs has been claimed.
  284. */
  285. static inline rt_bool_t sdio_irq_claimed(struct mmc_host *host)
  286. {
  287. return host->sdio_irqs > 0;
  288. }
  289. static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
  290. struct regulator *supply,
  291. unsigned short vdd_bit)
  292. {
  293. return 0;
  294. }
  295. int mmc_regulator_get_supply(struct mmc_host *mmc);
  296. int mmc_regulator_enable_vqmmc(struct mmc_host *mmc);
  297. void mmc_regulator_disable_vqmmc(struct mmc_host *mmc);
  298. void mmc_retune_timer_stop(struct mmc_host *host);
  299. static inline void mmc_retune_needed(struct mmc_host *host)
  300. {
  301. if (host->can_retune)
  302. host->need_retune = 1;
  303. }
  304. static inline rt_bool_t mmc_can_retune(struct mmc_host *host)
  305. {
  306. return host->can_retune == 1;
  307. }
  308. static inline rt_bool_t mmc_doing_retune(struct mmc_host *host)
  309. {
  310. return host->doing_retune == 1;
  311. }
  312. static inline rt_bool_t mmc_doing_tune(struct mmc_host *host)
  313. {
  314. return host->doing_retune == 1 || host->doing_init_tune == 1;
  315. }
  316. static inline int mmc_get_dma_dir(struct rt_mmcsd_data *data)
  317. {
  318. return data->flags & DATA_DIR_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  319. }
  320. static inline rt_bool_t mmc_op_multi(rt_uint32_t opcode)
  321. {
  322. return opcode == MMC_WRITE_MULTIPLE_BLOCK || opcode == MMC_READ_MULTIPLE_BLOCK;
  323. }
  324. static inline rt_bool_t mmc_op_tuning(rt_uint32_t opcode)
  325. {
  326. return opcode == MMC_SEND_TUNING_BLOCK || opcode == MMC_SEND_TUNING_BLOCK_HS200;
  327. }
  328. int mmc_gpio_get_cd(struct mmc_host *host);
  329. void mmc_detect_change(struct mmc_host *host, unsigned long delay);
  330. int mmc_regulator_set_vqmmc(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios);
  331. rt_bool_t mmc_can_gpio_ro(struct mmc_host *host);
  332. int mmc_gpio_get_ro(struct mmc_host *host);
  333. int mmc_send_tuning(struct mmc_host *host, rt_uint32_t opcode, int *cmd_error);
  334. int mmc_send_abort_tuning(struct mmc_host *host, rt_uint32_t opcode);
  335. int mmc_of_parse(struct mmc_host *host);
  336. #endif