sdhci.c 107 KB

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  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-16 zhujiale first version
  9. */
  10. #include <rtthread.h>
  11. #include "sdhci.h"
  12. #include <string.h>
  13. #define DBG_TAG "SDHCI"
  14. #ifdef DRV_DEBUG
  15. #define DBG_LVL DBG_LOG
  16. #else
  17. #define DBG_LVL DBG_INFO
  18. #endif /* DRV_DEBUG */
  19. #include <rtdbg.h>
  20. static unsigned int debug_quirks = 0;
  21. static unsigned int debug_quirks2;
  22. /********************************************************* */
  23. /* cmd */
  24. /********************************************************* */
  25. void read_reg(struct sdhci_host *host)
  26. {
  27. rt_kprintf("0x00 addddddddddddd = %x \n", sdhci_readl(host, 0x00));
  28. rt_kprintf("0x04 EMMC_BLOCKSIZE = %x \n", sdhci_readw(host, 0x04));
  29. rt_kprintf("0x06 EMMC_BLOCKCOUNT = %x \n", sdhci_readw(host, 0x06));
  30. rt_kprintf("0x08 SDHCI_ARGUMENT = %x \n", sdhci_readl(host, 0x08));
  31. rt_kprintf("0x0c EMMC_XFER_MODE = %x \n", sdhci_readw(host, 0x0c));
  32. rt_kprintf("0x0e SDHCI_COMMAND = %x \n", sdhci_readw(host, 0x0e));
  33. rt_kprintf("0x24 SDHCI_PRESENT_STATE = %x \n", sdhci_readl(host, 0x24));
  34. rt_kprintf("0x28 SDHCI_HOST_CONTROL = %x \n", sdhci_readb(host, 0x28));
  35. rt_kprintf("0x29 SDHCI_POWER_CONTROL = %x \n", sdhci_readb(host, 0x29));
  36. rt_kprintf("0x2a EMMC_BGAP_CTRL = %x \n", sdhci_readb(host, 0x2a));
  37. rt_kprintf("0x2c EMMC_CLK_CTRL = %x \n", sdhci_readw(host, 0x2c));
  38. rt_kprintf("0x2e EMMC_TOUT_CTRL = %x \n", sdhci_readb(host, 0x2e));
  39. rt_kprintf("0x2f EMMC_SW_RST = %x \n", sdhci_readb(host, 0x2f));
  40. rt_kprintf("0x30 SDHCI_INT_STATUS = %x \n", sdhci_readw(host, 0x30));
  41. rt_kprintf("0x32 SDHCI_ERR_INT_STATUS = %x \n", sdhci_readw(host, 0x32));
  42. rt_kprintf("0x34 SDHCI_INT_ENABLE = %x \n", sdhci_readw(host, 0x34));
  43. rt_kprintf("0x36 EMMC ERROR INT STATEN = %x \n", sdhci_readw(host, 0x36));
  44. rt_kprintf("0x38 EMMC NORMAL INT SIGNAL EN= %x \n", sdhci_readw(host, 0x38));
  45. rt_kprintf("0x3a EMMC ERROR INT SIGNAL EN = %x \n", sdhci_readw(host, 0x3a));
  46. rt_kprintf("0x3c EMMC_AUTO_CMD_STAT = %x \n", sdhci_readw(host, 0x3c));
  47. rt_kprintf("0x3e EMMC_HOST_CTRL2 = %x \n", sdhci_readw(host, 0x3e));
  48. rt_kprintf("0x40 EMMC_CAPABILITIES1 = %x \n", sdhci_readl(host, 0x40));
  49. rt_kprintf("0x44 EMMC_CAPABILITIES2 = %x \n", sdhci_readl(host, 0x44));
  50. rt_kprintf("0x52 EMMC_FORC_ERR_INT_STAT = %x \n", sdhci_readw(host, 0x52));
  51. rt_kprintf("0x54 EMMC_ADMA_ERR_STAT = %x \n", sdhci_readb(host, 0x54));
  52. rt_kprintf("0x58 EMMC_ADMA_SA = %x \n", sdhci_readl(host, 0x58));
  53. rt_kprintf("0x66 EMMC_PRESET_SDR12 = %x \n", sdhci_readw(host, 0x66));
  54. rt_kprintf("0x68 EMMC_PRESET_SDR25 = %x \n", sdhci_readw(host, 0x68));
  55. rt_kprintf("0x6a EMMC_PRESET_SDR50 = %x \n", sdhci_readw(host, 0x6a));
  56. rt_kprintf("0x6c EMMC_PRESET_SDR104 = %x \n", sdhci_readw(host, 0x6c));
  57. rt_kprintf("0x6e EMMC_PRESET_DDR50 = %x \n", sdhci_readw(host, 0x6e));
  58. rt_kprintf("0x78 EMMC_ADMA_ID = %x \n", sdhci_readl(host, 0x78));
  59. rt_kprintf("0xfe EMMC_HOST_CNTRL_VERS = %x \n", sdhci_readw(host, 0xfe));
  60. }
  61. static inline rt_bool_t sdhci_has_requests(struct sdhci_host *host)
  62. {
  63. return host->cmd || host->data_cmd;
  64. }
  65. static inline rt_bool_t sdhci_auto_cmd23(struct sdhci_host *host,
  66. struct rt_mmcsd_req *mrq)
  67. {
  68. return mrq->sbc && (host->flags & SDHCI_AUTO_CMD23);
  69. }
  70. static inline rt_bool_t sdhci_auto_cmd12(struct sdhci_host *host,
  71. struct rt_mmcsd_req *mrq)
  72. {
  73. return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) && !mrq->cap_cmd_during_tfr;
  74. }
  75. static inline rt_bool_t sdhci_manual_cmd23(struct sdhci_host *host,
  76. struct rt_mmcsd_req *mrq)
  77. {
  78. return mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23);
  79. }
  80. static inline rt_bool_t sdhci_data_line_cmd(struct rt_mmcsd_cmd *cmd)
  81. {
  82. return cmd->data || cmd->flags & MMC_RSP_BUSY;
  83. }
  84. void sdhci_set_data_timeout_irq(struct sdhci_host *host, rt_bool_t enable)
  85. {
  86. if (enable)
  87. host->ier |= SDHCI_INT_DATA_TIMEOUT;
  88. else
  89. host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
  90. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  91. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  92. }
  93. void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
  94. {
  95. rt_uint16_t ctrl_2;
  96. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  97. /* Select Bus Speed Mode for host */
  98. ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
  99. if ((timing == MMC_TIMING_MMC_HS200) || (timing == MMC_TIMING_UHS_SDR104))
  100. ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
  101. else if (timing == MMC_TIMING_UHS_SDR12)
  102. ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
  103. else if (timing == MMC_TIMING_UHS_SDR25)
  104. ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
  105. else if (timing == MMC_TIMING_UHS_SDR50)
  106. ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
  107. else if ((timing == MMC_TIMING_UHS_DDR50) || (timing == MMC_TIMING_MMC_DDR52))
  108. ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
  109. else if (timing == MMC_TIMING_MMC_HS400)
  110. ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
  111. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  112. }
  113. void sdhci_set_bus_width(struct sdhci_host *host, int width)
  114. {
  115. rt_uint8_t ctrl;
  116. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  117. if (width == MMC_BUS_WIDTH_8)
  118. {
  119. ctrl &= ~SDHCI_CTRL_4BITBUS;
  120. ctrl |= SDHCI_CTRL_8BITBUS;
  121. }
  122. else
  123. {
  124. if (host->mmc->caps & MMC_CAP_8_BIT_DATA)
  125. ctrl &= ~SDHCI_CTRL_8BITBUS;
  126. if (width == MMC_BUS_WIDTH_4)
  127. ctrl |= SDHCI_CTRL_4BITBUS;
  128. else
  129. ctrl &= ~SDHCI_CTRL_4BITBUS;
  130. }
  131. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  132. }
  133. static inline rt_bool_t sdhci_can_64bit_dma(struct sdhci_host *host)
  134. {
  135. /*
  136. * According to SD Host Controller spec v4.10, bit[27] added from
  137. * version 4.10 in Capabilities Register is used as 64-bit System
  138. * Address support for V4 mode.
  139. */
  140. if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
  141. return host->caps & SDHCI_CAN_64BIT_V4;
  142. return host->caps & SDHCI_CAN_64BIT;
  143. }
  144. static void sdhci_do_enable_v4_mode(struct sdhci_host *host)
  145. {
  146. rt_uint16_t ctrl2;
  147. ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  148. if (ctrl2 & SDHCI_CTRL_V4_MODE)
  149. return;
  150. ctrl2 |= SDHCI_CTRL_V4_MODE;
  151. sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
  152. }
  153. void sdhci_cleanup_host(struct sdhci_host *host)
  154. {
  155. struct mmc_host *mmc = host->mmc;
  156. if (host->sdhci_core_to_disable_vqmmc)
  157. regulator_disable(mmc->supply.vqmmc);
  158. if (host->align_buffer)
  159. dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, host->align_buffer,
  160. host->align_addr);
  161. host->adma_table = NULL;
  162. host->align_buffer = NULL;
  163. }
  164. static void sdhci_set_default_irqs(struct sdhci_host *host)
  165. {
  166. host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  167. if (host->tuning_mode == SDHCI_TUNING_MODE_2 || host->tuning_mode == SDHCI_TUNING_MODE_3)
  168. host->ier |= SDHCI_INT_RETUNE;
  169. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  170. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  171. }
  172. static inline void sdhci_auto_cmd_select(struct sdhci_host *host,
  173. struct rt_mmcsd_cmd *cmd,
  174. rt_uint16_t *mode)
  175. {
  176. rt_bool_t use_cmd12 = sdhci_auto_cmd12(host, cmd->mrq) && (cmd->cmd_code != SD_IO_RW_EXTENDED);
  177. rt_bool_t use_cmd23 = sdhci_auto_cmd23(host, cmd->mrq);
  178. rt_uint16_t ctrl2;
  179. /*
  180. * In case of Version 4.10 or later, use of 'Auto CMD Auto
  181. * Select' is recommended rather than use of 'Auto CMD12
  182. * Enable' or 'Auto CMD23 Enable'. We require Version 4 Mode
  183. * here because some controllers (e.g sdhci-of-dwmshc) expect it.
  184. */
  185. if (host->version >= SDHCI_SPEC_410 && host->v4_mode && (use_cmd12 || use_cmd23))
  186. {
  187. *mode |= SDHCI_TRNS_AUTO_SEL;
  188. ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  189. if (use_cmd23)
  190. ctrl2 |= SDHCI_CMD23_ENABLE;
  191. else
  192. ctrl2 &= ~SDHCI_CMD23_ENABLE;
  193. sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
  194. return;
  195. }
  196. /*
  197. * If we are sending CMD23, CMD12 never gets sent
  198. * on successful completion (so no Auto-CMD12).
  199. */
  200. if (use_cmd12)
  201. *mode |= SDHCI_TRNS_AUTO_CMD12;
  202. else if (use_cmd23)
  203. *mode |= SDHCI_TRNS_AUTO_CMD23;
  204. }
  205. static rt_bool_t sdhci_present_error(struct sdhci_host *host,
  206. struct rt_mmcsd_cmd *cmd, rt_bool_t present)
  207. {
  208. if (!present || host->flags & SDHCI_DEVICE_DEAD)
  209. {
  210. cmd->err = -ENOMEDIUM;
  211. return RT_TRUE;
  212. }
  213. return RT_FALSE;
  214. }
  215. static rt_uint16_t sdhci_get_preset_value(struct sdhci_host *host)
  216. {
  217. rt_uint16_t preset = 0;
  218. switch (host->timing)
  219. {
  220. case MMC_TIMING_MMC_HS:
  221. case MMC_TIMING_SD_HS:
  222. preset = sdhci_readw(host, SDHCI_PRESET_FOR_HIGH_SPEED);
  223. break;
  224. case MMC_TIMING_UHS_SDR12:
  225. preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
  226. break;
  227. case MMC_TIMING_UHS_SDR25:
  228. preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
  229. break;
  230. case MMC_TIMING_UHS_SDR50:
  231. preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
  232. break;
  233. case MMC_TIMING_UHS_SDR104:
  234. case MMC_TIMING_MMC_HS200:
  235. preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
  236. break;
  237. case MMC_TIMING_UHS_DDR50:
  238. case MMC_TIMING_MMC_DDR52:
  239. preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
  240. break;
  241. case MMC_TIMING_MMC_HS400:
  242. preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
  243. break;
  244. default:
  245. preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
  246. break;
  247. }
  248. return preset;
  249. }
  250. static void sdhci_set_card_detection(struct sdhci_host *host, rt_bool_t enable)
  251. {
  252. rt_uint32_t present;
  253. if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || !mmc_card_is_removable(host->mmc))
  254. return;
  255. if (enable)
  256. {
  257. present = sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT;
  258. host->ier |= present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
  259. }
  260. else
  261. {
  262. host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
  263. }
  264. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  265. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  266. }
  267. static void sdhci_enable_card_detection(struct sdhci_host *host)
  268. {
  269. sdhci_set_card_detection(host, RT_TRUE);
  270. }
  271. static inline int sdhci_external_dma_init(struct sdhci_host *host)
  272. {
  273. return -EOPNOTSUPP;
  274. }
  275. static inline void sdhci_external_dma_release(struct sdhci_host *host)
  276. {
  277. }
  278. static inline void sdhci_external_dma_prepare_data(struct sdhci_host *host,
  279. struct rt_mmcsd_cmd *cmd)
  280. {
  281. /* This should never happen */
  282. }
  283. static inline void sdhci_external_dma_pre_transfer(struct sdhci_host *host,
  284. struct rt_mmcsd_cmd *cmd)
  285. {
  286. }
  287. static inline struct dma_chan *sdhci_external_dma_channel(struct sdhci_host *host,
  288. struct rt_mmcsd_data *data)
  289. {
  290. return NULL;
  291. }
  292. /********************************************************* */
  293. /* reset */
  294. /********************************************************* */
  295. enum sdhci_reset_reason
  296. {
  297. SDHCI_RESET_FOR_INIT,
  298. SDHCI_RESET_FOR_REQUEST_ERROR,
  299. SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY,
  300. SDHCI_RESET_FOR_TUNING_ABORT,
  301. SDHCI_RESET_FOR_CARD_REMOVED,
  302. SDHCI_RESET_FOR_CQE_RECOVERY,
  303. };
  304. static rt_bool_t sdhci_needs_reset(struct sdhci_host *host, struct rt_mmcsd_req *mrq)
  305. {
  306. return (!(host->flags & SDHCI_DEVICE_DEAD) && ((mrq->cmd && mrq->cmd->err) || (mrq->sbc && mrq->sbc->err) || (mrq->data && mrq->data->stop && mrq->data->stop->err) || (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)));
  307. }
  308. static rt_bool_t sdhci_do_reset(struct sdhci_host *host, rt_uint8_t mask)
  309. {
  310. if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET)
  311. {
  312. struct mmc_host *mmc = host->mmc;
  313. if (!mmc->ops->get_cd(mmc))
  314. return RT_FALSE;
  315. }
  316. if (host->ops->reset)
  317. {
  318. host->ops->reset(host, mask);
  319. }
  320. return RT_TRUE;
  321. }
  322. static void sdhci_reset_for_reason(struct sdhci_host *host, enum sdhci_reset_reason reason)
  323. {
  324. if (host->quirks2 & SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER)
  325. {
  326. sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  327. return;
  328. }
  329. switch (reason)
  330. {
  331. case SDHCI_RESET_FOR_INIT:
  332. sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  333. break;
  334. case SDHCI_RESET_FOR_REQUEST_ERROR:
  335. case SDHCI_RESET_FOR_TUNING_ABORT:
  336. case SDHCI_RESET_FOR_CARD_REMOVED:
  337. case SDHCI_RESET_FOR_CQE_RECOVERY:
  338. sdhci_do_reset(host, SDHCI_RESET_CMD);
  339. sdhci_do_reset(host, SDHCI_RESET_DATA);
  340. break;
  341. case SDHCI_RESET_FOR_REQUEST_ERROR_DATA_ONLY:
  342. sdhci_do_reset(host, SDHCI_RESET_DATA);
  343. break;
  344. }
  345. }
  346. #define sdhci_reset_for(h, r) sdhci_reset_for_reason((h), SDHCI_RESET_FOR_##r)
  347. static void sdhci_reset_for_all(struct sdhci_host *host)
  348. {
  349. if (sdhci_do_reset(host, SDHCI_RESET_ALL))
  350. {
  351. if (host->flags & (SDHCI_USE_SDMA))
  352. {
  353. if (host->ops->enable_dma)
  354. host->ops->enable_dma(host);
  355. }
  356. /* Resetting the controller clears many */
  357. host->preset_enabled = RT_FALSE;
  358. }
  359. }
  360. static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  361. {
  362. if (host->bus_on)
  363. return;
  364. host->bus_on = RT_TRUE;
  365. }
  366. static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  367. {
  368. if (!host->bus_on)
  369. return;
  370. host->bus_on = RT_FALSE;
  371. }
  372. void sdhci_reset(struct sdhci_host *host, rt_uint8_t mask)
  373. {
  374. ssize_t timeout;
  375. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  376. if (mask & SDHCI_RESET_ALL)
  377. {
  378. host->clock = 0;
  379. /* Reset-all turns off SD Bus Power */
  380. if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
  381. sdhci_runtime_pm_bus_off(host);
  382. }
  383. timeout = rt_tick_from_millisecond(150);
  384. while (1)
  385. {
  386. timeout = timeout - rt_tick_get();
  387. if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
  388. break;
  389. if (timeout < 0)
  390. {
  391. rt_kprintf("%s: Reset 0x%x never completed.\n",
  392. mmc_hostname(host->mmc), (int)mask);
  393. sdhci_dumpregs(host);
  394. return;
  395. }
  396. rt_hw_us_delay(10);
  397. }
  398. }
  399. /********************************************************* */
  400. /* data */
  401. /********************************************************* */
  402. static void sdhci_initialize_data(struct sdhci_host *host,
  403. struct rt_mmcsd_data *data)
  404. {
  405. /* Sanity checks */
  406. LOG_D(data->blksize * data->blks > 524288);
  407. LOG_D(data->blksize > host->mmc->max_blk_size);
  408. LOG_D(data->blks > 65535);
  409. host->data = data;
  410. host->data_early = 0;
  411. host->data->bytes_xfered = 0;
  412. }
  413. static rt_ubase_t sdhci_sdma_address(struct sdhci_host *host)
  414. {
  415. return (rt_ubase_t)rt_kmem_v2p(host->data->buf);
  416. }
  417. static void sdhci_set_adma_addr(struct sdhci_host *host, rt_uint32_t addr)
  418. {
  419. sdhci_writel(host, lower_32_bits(addr), SDHCI_ADMA_ADDRESS);
  420. if (host->flags & SDHCI_USE_64_BIT_DMA)
  421. sdhci_writel(host, upper_32_bits(addr), SDHCI_ADMA_ADDRESS_HI);
  422. }
  423. static void sdhci_set_sdma_addr(struct sdhci_host *host, rt_uint32_t addr)
  424. {
  425. if (host->v4_mode)
  426. sdhci_set_adma_addr(host, addr);
  427. else
  428. sdhci_writel(host, addr, SDHCI_DMA_ADDRESS);
  429. }
  430. static void sdhci_config_dma(struct sdhci_host *host)
  431. {
  432. rt_uint8_t ctrl;
  433. rt_uint16_t ctrl2;
  434. if (host->version < SDHCI_SPEC_200)
  435. return;
  436. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  437. /*
  438. * Always adjust the DMA selection as some controllers
  439. * (e.g. JMicron) can't do PIO properly when the selection
  440. * is ADMA.
  441. */
  442. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  443. if (!(host->flags & SDHCI_REQ_USE_DMA))
  444. goto out;
  445. /* Note if DMA Select is zero then SDMA is selected */
  446. if (host->flags & SDHCI_USE_64_BIT_DMA)
  447. {
  448. /*
  449. * If v4 mode, all supported DMA can be 64-bit addressing if
  450. * controller supports 64-bit system address, otherwise only
  451. * ADMA can support 64-bit addressing.
  452. */
  453. if (host->v4_mode)
  454. {
  455. ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  456. ctrl2 |= SDHCI_CTRL_64BIT_ADDR;
  457. sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
  458. }
  459. }
  460. out:
  461. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  462. }
  463. static inline void sdhci_set_block_info(struct sdhci_host *host,
  464. struct rt_mmcsd_data *data)
  465. {
  466. /* Set the DMA boundary value and block size */
  467. sdhci_writew(host,
  468. SDHCI_MAKE_BLKSZ(7, data->blksize),
  469. SDHCI_BLOCK_SIZE);
  470. /*
  471. * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count
  472. * can be supported, in that case 16-bit block count register must be 0.
  473. */
  474. if (host->version >= SDHCI_SPEC_410 && host->v4_mode && (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT))
  475. {
  476. if (sdhci_readw(host, SDHCI_BLOCK_COUNT))
  477. sdhci_writew(host, 0, SDHCI_BLOCK_COUNT);
  478. sdhci_writew(host, data->blks, SDHCI_32BIT_BLK_CNT);
  479. }
  480. else
  481. {
  482. sdhci_writew(host, data->blks, SDHCI_BLOCK_COUNT);
  483. }
  484. }
  485. static void sdhci_set_transfer_irqs(struct sdhci_host *host)
  486. {
  487. rt_uint32_t pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
  488. rt_uint32_t dma_irqs = SDHCI_INT_DMA_END;
  489. if (host->flags & SDHCI_REQ_USE_DMA)
  490. host->ier = (host->ier & ~pio_irqs) | dma_irqs;
  491. else
  492. host->ier = (host->ier & ~dma_irqs) | pio_irqs;
  493. if (host->flags & (SDHCI_AUTO_CMD23 | SDHCI_AUTO_CMD12))
  494. host->ier |= SDHCI_INT_AUTO_CMD_ERR;
  495. else
  496. host->ier &= ~SDHCI_INT_AUTO_CMD_ERR;
  497. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  498. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  499. }
  500. static void sdhci_prepare_data(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd)
  501. {
  502. struct rt_mmcsd_data *data = cmd->data;
  503. sdhci_initialize_data(host, data);
  504. if (host->flags & SDHCI_USE_SDMA)
  505. {
  506. unsigned int length_mask, offset_mask;
  507. host->flags |= SDHCI_REQ_USE_DMA;
  508. /*
  509. * FIXME: This doesn't account for merging when mapping the
  510. * scatterlist.
  511. *
  512. * The assumption here being that alignment and lengths are
  513. * the same after DMA mapping to device address space.
  514. */
  515. length_mask = 0;
  516. offset_mask = 0;
  517. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
  518. length_mask = 3;
  519. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
  520. offset_mask = 3;
  521. if (length_mask | offset_mask)
  522. {
  523. host->flags &= ~SDHCI_REQ_USE_DMA;
  524. }
  525. }
  526. sdhci_config_dma(host);
  527. if (host->flags & SDHCI_REQ_USE_DMA)
  528. {
  529. if (mmc_get_dma_dir(data) == DMA_FROM_DEVICE)
  530. rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, data->buf, data->blks * data->blksize);
  531. else
  532. rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, data->buf, data->blks * data->blksize);
  533. sdhci_set_sdma_addr(host, sdhci_sdma_address(host));
  534. }
  535. if (!(host->flags & SDHCI_REQ_USE_DMA))
  536. {
  537. host->blocks = data->blks;
  538. }
  539. sdhci_set_transfer_irqs(host);
  540. sdhci_set_block_info(host, data);
  541. }
  542. static void sdhci_set_mrq_done(struct sdhci_host *host, struct rt_mmcsd_req *mrq)
  543. {
  544. int i;
  545. for (i = 0; i < SDHCI_MAX_MRQS; i++)
  546. {
  547. if (host->mrqs_done[i] == mrq)
  548. {
  549. LOG_D(1);
  550. return;
  551. }
  552. }
  553. for (i = 0; i < SDHCI_MAX_MRQS; i++)
  554. {
  555. if (!host->mrqs_done[i])
  556. {
  557. host->mrqs_done[i] = mrq;
  558. break;
  559. }
  560. }
  561. LOG_D(i >= SDHCI_MAX_MRQS);
  562. }
  563. static inline rt_bool_t sdhci_defer_done(struct sdhci_host *host,
  564. struct rt_mmcsd_req *mrq)
  565. {
  566. struct rt_mmcsd_data *data = mrq->data;
  567. return host->pending_reset || host->always_defer_done || ((host->flags & SDHCI_REQ_USE_DMA) && data && data->host_cookie == COOKIE_MAPPED);
  568. }
  569. /********************************************************* */
  570. /* pio */
  571. /********************************************************* */
  572. static void sdhci_read_block_pio(struct sdhci_host *host,void **buf)
  573. {
  574. rt_uint32_t scratch;
  575. size_t len;
  576. rt_uint32_t blksize = host->data->blksize;
  577. while (blksize)
  578. {
  579. len = min(4U, blksize);
  580. scratch = sdhci_readl(host, SDHCI_BUFFER);
  581. rt_memcpy(*buf, &scratch, len);
  582. *buf += len;
  583. blksize -= len;
  584. }
  585. }
  586. static void sdhci_write_block_pio(struct sdhci_host *host,void **buf)
  587. {
  588. size_t blksize, len;
  589. rt_uint32_t scratch;
  590. LOG_D("PIO writing\n");
  591. blksize = host->data->blksize;
  592. scratch = 0;
  593. while (blksize)
  594. {
  595. len = min(4U, blksize);
  596. rt_memcpy(&scratch, *buf, len);
  597. *buf += len;
  598. blksize -= len;
  599. sdhci_writel(host, scratch, SDHCI_BUFFER);
  600. }
  601. }
  602. static void sdhci_transfer_pio(struct sdhci_host *host)
  603. {
  604. rt_uint32_t mask;
  605. if (host->blocks == 0)
  606. return;
  607. if (host->data->flags & DATA_DIR_READ)
  608. mask = SDHCI_DATA_AVAILABLE;
  609. else
  610. mask = SDHCI_SPACE_AVAILABLE;
  611. /*
  612. * Some controllers (JMicron JMB38x) mess up the buffer bits
  613. * for transfers < 4 bytes. As long as it is just one block,
  614. * we can ignore the bits.
  615. */
  616. if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && (host->data->blks == 1))
  617. {
  618. mask = ~0;
  619. }
  620. void *buf = (void *)host->data->buf;
  621. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
  622. {
  623. if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
  624. rt_hw_us_delay(100);
  625. if (host->data->flags & DATA_DIR_READ)
  626. sdhci_read_block_pio(host,&buf);
  627. else
  628. sdhci_write_block_pio(host,&buf);
  629. host->data->blks--;
  630. if (host->data->blks == 0)
  631. break;
  632. /* host->data->buf += host->data->blksize;*/
  633. }
  634. }
  635. /********************************************************* */
  636. /* config */
  637. /********************************************************* */
  638. static rt_bool_t sdhci_timing_has_preset(unsigned char timing)
  639. {
  640. switch (timing)
  641. {
  642. case MMC_TIMING_UHS_SDR12:
  643. case MMC_TIMING_UHS_SDR25:
  644. case MMC_TIMING_UHS_SDR50:
  645. case MMC_TIMING_UHS_SDR104:
  646. case MMC_TIMING_UHS_DDR50:
  647. case MMC_TIMING_MMC_DDR52:
  648. return RT_TRUE;
  649. }
  650. return RT_FALSE;
  651. }
  652. static rt_bool_t sdhci_preset_needed(struct sdhci_host *host, unsigned char timing)
  653. {
  654. return !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && sdhci_timing_has_preset(timing);
  655. }
  656. static rt_bool_t sdhci_presetable_values_change(struct sdhci_host *host, struct rt_mmcsd_io_cfg *ios)
  657. {
  658. /*
  659. * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK
  660. * Frequency. Check if preset values need to be enabled, or the Driver
  661. * Strength needs updating. Note, clock changes are handled separately.
  662. */
  663. return !host->preset_enabled && (sdhci_preset_needed(host, ios->timing) || host->drv_type != ios->drv_type);
  664. }
  665. static void sdhci_enable_preset_value(struct sdhci_host *host, rt_bool_t enable)
  666. {
  667. /* Host Controller v3.00 defines preset value registers */
  668. if (host->version < SDHCI_SPEC_300)
  669. return;
  670. /*
  671. * We only enable or disable Preset Value if they are not already
  672. * enabled or disabled respectively. Otherwise, we bail out.
  673. */
  674. if (host->preset_enabled != enable)
  675. {
  676. rt_uint16_t ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  677. if (enable)
  678. ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
  679. else
  680. ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
  681. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  682. if (enable)
  683. host->flags |= SDHCI_PV_ENABLED;
  684. else
  685. host->flags &= ~SDHCI_PV_ENABLED;
  686. host->preset_enabled = enable;
  687. }
  688. }
  689. static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
  690. unsigned short vdd)
  691. {
  692. struct mmc_host *mmc = host->mmc;
  693. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
  694. if (mode != MMC_POWER_OFF)
  695. sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
  696. else
  697. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  698. }
  699. void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode,
  700. unsigned short vdd)
  701. {
  702. rt_uint8_t pwr = 0;
  703. if (mode != MMC_POWER_OFF)
  704. {
  705. switch (1 << vdd)
  706. {
  707. case MMC_VDD_165_195:
  708. /*
  709. * Without a regulator, SDHCI does not support 2.0v
  710. * so we only get here if the driver deliberately
  711. * added the 2.0v range to ocr_avail. Map it to 1.8v
  712. * for the purpose of turning on the power.
  713. */
  714. case MMC_VDD_20_21:
  715. pwr = SDHCI_POWER_180;
  716. break;
  717. case MMC_VDD_29_30:
  718. case MMC_VDD_30_31:
  719. pwr = SDHCI_POWER_300;
  720. break;
  721. case MMC_VDD_32_33:
  722. case MMC_VDD_33_34:
  723. /*
  724. * 3.4 ~ 3.6V are valid only for those platforms where it's
  725. * known that the voltage range is supported by hardware.
  726. */
  727. case MMC_VDD_34_35:
  728. case MMC_VDD_35_36:
  729. pwr = SDHCI_POWER_330;
  730. break;
  731. default:
  732. break;
  733. }
  734. }
  735. if (host->pwr == pwr)
  736. return;
  737. host->pwr = pwr;
  738. if (pwr == 0)
  739. {
  740. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  741. if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
  742. sdhci_runtime_pm_bus_off(host);
  743. }
  744. else
  745. {
  746. /*
  747. * Spec says that we should clear the power reg before setting
  748. * a new value. Some controllers don't seem to like this though.
  749. */
  750. if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
  751. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  752. /*
  753. * At least the Marvell CaFe chip gets confused if we set the
  754. * voltage and set turn on power at the same time, so set the
  755. * voltage first.
  756. */
  757. if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
  758. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  759. pwr |= SDHCI_POWER_ON;
  760. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  761. if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
  762. sdhci_runtime_pm_bus_on(host);
  763. /*
  764. * Some controllers need an extra 10ms delay of 10ms before
  765. * they can apply clock after applying power
  766. */
  767. if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
  768. rt_thread_mdelay(10);
  769. }
  770. }
  771. void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
  772. unsigned short vdd)
  773. {
  774. if (!host->mmc->supply.vmmc)
  775. sdhci_set_power_noreg(host, mode, vdd);
  776. else
  777. sdhci_set_power_reg(host, mode, vdd);
  778. }
  779. int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
  780. struct rt_mmcsd_io_cfg *ios)
  781. {
  782. struct sdhci_host *host = mmc_priv(mmc);
  783. rt_uint16_t ctrl;
  784. int ret;
  785. /*
  786. * Signal Voltage Switching is only applicable for Host Controllers
  787. * v3.00 and above.
  788. */
  789. if (host->version < SDHCI_SPEC_300)
  790. return 0;
  791. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  792. switch (ios->signal_voltage)
  793. {
  794. case MMC_SIGNAL_VOLTAGE_330:
  795. if (!(host->flags & SDHCI_SIGNALING_330))
  796. return -EINVAL;
  797. /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
  798. ctrl &= ~SDHCI_CTRL_VDD_180;
  799. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  800. if (!mmc->supply.vqmmc)
  801. {
  802. ret = mmc_regulator_set_vqmmc(mmc, ios);
  803. if (ret < 0)
  804. {
  805. return -EIO;
  806. }
  807. }
  808. /* Wait for 5ms */
  809. rt_thread_mdelay(5);
  810. /* 3.3V regulator output should be stable within 5 ms */
  811. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  812. if (!(ctrl & SDHCI_CTRL_VDD_180))
  813. return 0;
  814. return -EAGAIN;
  815. case MMC_SIGNAL_VOLTAGE_180:
  816. if (!(host->flags & SDHCI_SIGNALING_180))
  817. return -EINVAL;
  818. if (!mmc->supply.vqmmc)
  819. {
  820. ret = mmc_regulator_set_vqmmc(mmc, ios);
  821. if (ret < 0)
  822. {
  823. LOG_D("%s: Switching to 1.8V signalling voltage failed\n",
  824. mmc_hostname(mmc));
  825. return -EIO;
  826. }
  827. }
  828. /*
  829. * Enable 1.8V Signal Enable in the Host Control2
  830. * register
  831. */
  832. ctrl |= SDHCI_CTRL_VDD_180;
  833. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  834. /* Some controller need to do more when switching */
  835. if (host->ops->voltage_switch)
  836. host->ops->voltage_switch(host);
  837. /* 1.8V regulator output should be stable within 5 ms */
  838. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  839. if (ctrl & SDHCI_CTRL_VDD_180)
  840. return 0;
  841. LOG_D("%s: 1.8V regulator output did not become stable\n",
  842. mmc_hostname(mmc));
  843. return -EAGAIN;
  844. case MMC_SIGNAL_VOLTAGE_120:
  845. if (!(host->flags & SDHCI_SIGNALING_120))
  846. return -EINVAL;
  847. if (!mmc->supply.vqmmc)
  848. {
  849. ret = mmc_regulator_set_vqmmc(mmc, ios);
  850. if (ret < 0)
  851. {
  852. LOG_D("%s: Switching to 1.2V signalling voltage failed\n",
  853. mmc_hostname(mmc));
  854. return -EIO;
  855. }
  856. }
  857. return 0;
  858. default:
  859. /* No signal voltage switch required */
  860. return 0;
  861. }
  862. }
  863. static int sdhci_get_cd(struct mmc_host *mmc)
  864. {
  865. struct sdhci_host *host = mmc_priv(mmc);
  866. int gpio_cd = mmc_gpio_get_cd(mmc);
  867. if (host->flags & SDHCI_DEVICE_DEAD)
  868. return 0;
  869. /* If nonremovable, assume that the card is always present. */
  870. if (!mmc_card_is_removable(mmc))
  871. return 1;
  872. /*
  873. * Try slot gpio detect, if defined it take precedence
  874. * over build in controller functionality
  875. */
  876. if (gpio_cd >= 0)
  877. return !!gpio_cd;
  878. /* If polling, assume that the card is always present. */
  879. if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
  880. return 1;
  881. /* Host native card detect */
  882. return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
  883. }
  884. static int sdhci_check_ro(struct sdhci_host *host)
  885. {
  886. int is_readonly;
  887. rt_base_t flags;
  888. flags = rt_spin_lock_irqsave(&host->lock);
  889. if (host->flags & SDHCI_DEVICE_DEAD)
  890. is_readonly = 0;
  891. else if (host->ops->get_ro)
  892. is_readonly = host->ops->get_ro(host);
  893. else if (mmc_can_gpio_ro(host->mmc))
  894. is_readonly = mmc_gpio_get_ro(host->mmc);
  895. else
  896. is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
  897. & SDHCI_WRITE_PROTECT);
  898. rt_spin_unlock_irqrestore(&host->lock, flags);
  899. /* This quirk needs to be replaced by a callback-function later */
  900. return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? !is_readonly : is_readonly;
  901. }
  902. #define SAMPLE_COUNT 5
  903. static int sdhci_get_ro(struct mmc_host *mmc)
  904. {
  905. struct sdhci_host *host = mmc_priv(mmc);
  906. int i, ro_count;
  907. if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
  908. return sdhci_check_ro(host);
  909. ro_count = 0;
  910. for (i = 0; i < SAMPLE_COUNT; i++)
  911. {
  912. if (sdhci_check_ro(host))
  913. {
  914. if (++ro_count > SAMPLE_COUNT / 2)
  915. return 1;
  916. }
  917. rt_thread_mdelay(30);
  918. }
  919. return 0;
  920. }
  921. static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
  922. {
  923. if (!(host->flags & SDHCI_DEVICE_DEAD))
  924. {
  925. if (enable)
  926. host->ier |= SDHCI_INT_CARD_INT;
  927. else
  928. host->ier &= ~SDHCI_INT_CARD_INT;
  929. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  930. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  931. }
  932. }
  933. static void sdhci_ack_sdio_irq(struct mmc_host *mmc)
  934. {
  935. rt_base_t flags;
  936. struct sdhci_host *host = mmc_priv(mmc);
  937. flags = rt_spin_lock_irqsave(&host->lock);
  938. sdhci_enable_sdio_irq_nolock(host, RT_TRUE);
  939. rt_spin_unlock_irqrestore(&host->lock, flags);
  940. }
  941. static void sdhci_del_timer(struct sdhci_host *host, struct rt_mmcsd_req *mrq)
  942. {
  943. if (sdhci_data_line_cmd(mrq->cmd))
  944. rt_timer_stop(&host->data_timer);
  945. else
  946. rt_timer_stop(&host->timer);
  947. }
  948. static unsigned int sdhci_target_timeout(struct sdhci_host *host,
  949. struct rt_mmcsd_cmd *cmd,
  950. struct rt_mmcsd_data *data)
  951. {
  952. unsigned int target_timeout;
  953. /* timeout in us */
  954. if (!data)
  955. {
  956. target_timeout = cmd->busy_timeout * 1000;
  957. }
  958. else
  959. {
  960. target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
  961. if (host->clock && data->timeout_clks)
  962. {
  963. rt_uint32_t val;
  964. /*
  965. * data->timeout_clks is in units of clock cycles.
  966. * host->clock is in Hz. target_timeout is in us.
  967. * Hence, us = 1000000 * cycles / Hz. Round up.
  968. */
  969. val = 1000000ULL * data->timeout_clks;
  970. if (do_div(val, host->clock))
  971. target_timeout++;
  972. target_timeout += val;
  973. }
  974. }
  975. return target_timeout;
  976. }
  977. static rt_uint8_t sdhci_calc_timeout(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd,
  978. rt_bool_t *too_big)
  979. {
  980. rt_uint8_t count;
  981. struct rt_mmcsd_data *data;
  982. unsigned target_timeout, current_timeout;
  983. *too_big = RT_FALSE;
  984. /*
  985. * If the host controller provides us with an incorrect timeout
  986. * value, just skip the check and use the maximum. The hardware may take
  987. * longer to time out, but that's much better than having a too-short
  988. * timeout value.
  989. */
  990. if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
  991. return host->max_timeout_count;
  992. /* Unspecified command, assume max */
  993. if (cmd == NULL)
  994. return host->max_timeout_count;
  995. data = cmd->data;
  996. /* Unspecified timeout, assume max */
  997. if (!data && !cmd->busy_timeout)
  998. return host->max_timeout_count;
  999. /* timeout in us */
  1000. target_timeout = sdhci_target_timeout(host, cmd, data);
  1001. /*
  1002. * Figure out needed cycles.
  1003. * We do this in steps in order to fit inside a 32 bit int.
  1004. * The first step is the minimum timeout, which will have a
  1005. * minimum resolution of 6 bits:
  1006. * (1) 2^13*1000 > 2^22,
  1007. * (2) host->timeout_clk < 2^16
  1008. * =>
  1009. * (1) / (2) > 2^6
  1010. */
  1011. count = 0;
  1012. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  1013. while (current_timeout < target_timeout)
  1014. {
  1015. count++;
  1016. current_timeout <<= 1;
  1017. if (count > host->max_timeout_count)
  1018. {
  1019. if (!(host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT))
  1020. LOG_D("Too large timeout 0x%x requested for CMD%d!\n",
  1021. count, cmd->cmd_code);
  1022. count = host->max_timeout_count;
  1023. *too_big = RT_TRUE;
  1024. break;
  1025. }
  1026. }
  1027. return count;
  1028. }
  1029. static void sdhci_calc_sw_timeout(struct sdhci_host *host,
  1030. struct rt_mmcsd_cmd *cmd)
  1031. {
  1032. struct rt_mmcsd_data *data = cmd->data;
  1033. struct mmc_host *mmc = host->mmc;
  1034. struct rt_mmcsd_io_cfg *ios = &mmc->ios;
  1035. unsigned char bus_width = 1 << ios->bus_width;
  1036. unsigned int blksz;
  1037. unsigned int freq;
  1038. rt_uint64_t target_timeout;
  1039. rt_uint64_t transfer_time;
  1040. target_timeout = sdhci_target_timeout(host, cmd, data);
  1041. target_timeout *= 1000L;
  1042. if (data)
  1043. {
  1044. blksz = data->blksize;
  1045. freq = mmc->actual_clock ?: host->clock;
  1046. transfer_time = (rt_uint64_t)blksz * 1000000000L * (8 / bus_width);
  1047. do_div(transfer_time, freq);
  1048. /* multiply by '2' to account for any unknowns */
  1049. transfer_time = transfer_time * 2;
  1050. /* calculate timeout for the entire data */
  1051. host->data_timeout = data->blks * target_timeout + transfer_time;
  1052. }
  1053. else
  1054. {
  1055. host->data_timeout = target_timeout;
  1056. }
  1057. if (host->data_timeout)
  1058. host->data_timeout += MMC_CMD_TRANSFER_TIME;
  1059. }
  1060. void __sdhci_set_timeout(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd)
  1061. {
  1062. rt_bool_t too_big = RT_FALSE;
  1063. rt_uint8_t count = sdhci_calc_timeout(host, cmd, &too_big);
  1064. if (too_big && host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT)
  1065. {
  1066. sdhci_calc_sw_timeout(host, cmd);
  1067. sdhci_set_data_timeout_irq(host, RT_FALSE);
  1068. }
  1069. else if (!(host->ier & SDHCI_INT_DATA_TIMEOUT))
  1070. {
  1071. sdhci_set_data_timeout_irq(host, RT_FALSE);
  1072. }
  1073. sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
  1074. }
  1075. static void sdhci_set_timeout(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd)
  1076. {
  1077. if (host->ops->set_timeout)
  1078. host->ops->set_timeout(host, cmd);
  1079. else
  1080. __sdhci_set_timeout(host, cmd);
  1081. }
  1082. static void sdhci_mod_timer(struct sdhci_host *host, struct rt_mmcsd_req *mrq,
  1083. unsigned long timeout)
  1084. {
  1085. if (sdhci_data_line_cmd(mrq->cmd))
  1086. {
  1087. rt_tick_t tick = rt_tick_get();
  1088. if (timeout < tick)
  1089. {
  1090. timeout = tick;
  1091. }
  1092. tick = timeout - tick;
  1093. rt_timer_stop(&host->data_timer);
  1094. rt_timer_control(&host->data_timer, RT_TIMER_CTRL_SET_TIME, &tick);
  1095. rt_timer_start(&host->data_timer);
  1096. }
  1097. else
  1098. {
  1099. rt_tick_t tick = rt_tick_get();
  1100. if (timeout < tick)
  1101. {
  1102. timeout = tick;
  1103. }
  1104. tick = timeout - tick;
  1105. rt_timer_stop(&host->timer);
  1106. rt_timer_control(&host->timer, RT_TIMER_CTRL_SET_TIME, &tick);
  1107. rt_timer_start(&host->timer);
  1108. }
  1109. }
  1110. static void __sdhci_finish_mrq(struct sdhci_host *host, struct rt_mmcsd_req *mrq)
  1111. {
  1112. if (host->cmd && host->cmd->mrq == mrq)
  1113. host->cmd = NULL;
  1114. if (host->data_cmd && host->data_cmd->mrq == mrq)
  1115. host->data_cmd = NULL;
  1116. if (host->deferred_cmd && host->deferred_cmd->mrq == mrq)
  1117. host->deferred_cmd = NULL;
  1118. if (host->data && host->data->mrq == mrq)
  1119. host->data = NULL;
  1120. if (sdhci_needs_reset(host, mrq))
  1121. host->pending_reset = RT_TRUE;
  1122. sdhci_set_mrq_done(host, mrq);
  1123. sdhci_del_timer(host, mrq);
  1124. }
  1125. static void sdhci_finish_mrq(struct sdhci_host *host, struct rt_mmcsd_req *mrq)
  1126. {
  1127. __sdhci_finish_mrq(host, mrq);
  1128. rt_workqueue_submit_work(host->complete_wq, &host->complete_work, 0);
  1129. }
  1130. static void sdhci_error_out_mrqs(struct sdhci_host *host, int err)
  1131. {
  1132. if (host->data_cmd)
  1133. {
  1134. host->data_cmd->err = err;
  1135. sdhci_finish_mrq(host, host->data_cmd->mrq);
  1136. }
  1137. if (host->cmd)
  1138. {
  1139. host->cmd->err = err;
  1140. sdhci_finish_mrq(host, host->cmd->mrq);
  1141. }
  1142. }
  1143. static void sdhci_card_event(struct mmc_host *mmc)
  1144. {
  1145. struct sdhci_host *host = mmc_priv(mmc);
  1146. rt_uint32_t flags;
  1147. int present;
  1148. /* First check if client has provided their own card event */
  1149. if (host->ops->card_event)
  1150. host->ops->card_event(host);
  1151. present = mmc->ops->get_cd(mmc);
  1152. flags = rt_spin_lock_irqsave(&host->lock);
  1153. /* Check sdhci_has_requests() first in case we are runtime suspended */
  1154. if (sdhci_has_requests(host) && !present)
  1155. {
  1156. rt_kprintf("%s: Card removed during transfer!\n",
  1157. mmc_hostname(mmc));
  1158. rt_kprintf("%s: Resetting controller.\n",
  1159. mmc_hostname(mmc));
  1160. sdhci_do_reset(host, SDHCI_RESET_CMD);
  1161. sdhci_do_reset(host, SDHCI_RESET_DATA);
  1162. sdhci_error_out_mrqs(host, -ENOMEDIUM);
  1163. }
  1164. rt_spin_unlock_irqrestore(&host->lock, flags);
  1165. }
  1166. static int sdhci_card_busy(struct mmc_host *mmc)
  1167. {
  1168. struct sdhci_host *host = mmc_priv(mmc);
  1169. rt_uint32_t present_state;
  1170. /* Check whether DAT[0] is 0 */
  1171. present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
  1172. return !(present_state & SDHCI_DATA_0_LVL_MASK);
  1173. }
  1174. static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios)
  1175. {
  1176. struct sdhci_host *host = mmc_priv(mmc);
  1177. rt_uint32_t flags;
  1178. flags = rt_spin_lock_irqsave(&host->lock);
  1179. host->flags |= SDHCI_HS400_TUNING;
  1180. rt_spin_unlock_irqrestore(&host->lock, flags);
  1181. return 0;
  1182. }
  1183. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  1184. struct rt_mmcsd_cmd *cmd)
  1185. {
  1186. rt_uint16_t mode = 0;
  1187. struct rt_mmcsd_data *data = cmd->data;
  1188. if (data == NULL)
  1189. {
  1190. if (host->quirks2 & SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD)
  1191. {
  1192. /* must not clear SDHCI_TRANSFER_MODE when tuning */
  1193. if (!mmc_op_tuning(cmd->cmd_code))
  1194. sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
  1195. }
  1196. else
  1197. {
  1198. /* clear Auto CMD settings for no data CMDs */
  1199. mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
  1200. sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
  1201. }
  1202. return;
  1203. }
  1204. if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
  1205. mode = SDHCI_TRNS_BLK_CNT_EN;
  1206. if (mmc_op_multi(cmd->cmd_code) || data->blks > 1)
  1207. {
  1208. mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
  1209. sdhci_auto_cmd_select(host, cmd, &mode);
  1210. if (sdhci_auto_cmd23(host, cmd->mrq))
  1211. sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2);
  1212. }
  1213. if (data->flags & DATA_DIR_READ)
  1214. mode |= SDHCI_TRNS_READ;
  1215. if (host->flags & SDHCI_REQ_USE_DMA)
  1216. mode |= SDHCI_TRNS_DMA;
  1217. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  1218. }
  1219. static rt_bool_t sdhci_send_command(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd)
  1220. {
  1221. int flags;
  1222. rt_uint32_t mask;
  1223. unsigned long timeout;
  1224. /* Initially, a command has no error */
  1225. cmd->err = 0;
  1226. if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && cmd->cmd_code == MMC_STOP_TRANSMISSION)
  1227. cmd->flags |= MMC_RSP_BUSY;
  1228. mask = SDHCI_CMD_INHIBIT;
  1229. if (sdhci_data_line_cmd(cmd))
  1230. mask |= SDHCI_DATA_INHIBIT;
  1231. /* We shouldn't wait for data inihibit for stop commands, even
  1232. though they might use busy signaling */
  1233. if (cmd->mrq->data && (cmd == cmd->mrq->data->stop))
  1234. mask &= ~SDHCI_DATA_INHIBIT;
  1235. if (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)
  1236. return RT_FALSE;
  1237. host->cmd = cmd;
  1238. host->data_timeout = 0;
  1239. if (sdhci_data_line_cmd(cmd))
  1240. {
  1241. host->data_cmd = cmd;
  1242. sdhci_set_timeout(host, cmd);
  1243. }
  1244. if (cmd->data)
  1245. {
  1246. if (host->use_external_dma)
  1247. sdhci_external_dma_prepare_data(host, cmd);
  1248. else
  1249. sdhci_prepare_data(host, cmd);
  1250. }
  1251. sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
  1252. sdhci_set_transfer_mode(host, cmd);
  1253. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY))
  1254. {
  1255. /*
  1256. * This does not happen in practice because 136-bit response
  1257. * commands never have busy waiting, so rather than complicate
  1258. * the error path, just remove busy waiting and continue.
  1259. */
  1260. cmd->flags &= ~MMC_RSP_BUSY;
  1261. }
  1262. if (!(cmd->flags & MMC_RSP_PRESENT))
  1263. flags = SDHCI_CMD_RESP_NONE;
  1264. else if (cmd->flags & MMC_RSP_136)
  1265. flags = SDHCI_CMD_RESP_LONG;
  1266. else if (cmd->flags & MMC_RSP_BUSY)
  1267. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  1268. else
  1269. flags = SDHCI_CMD_RESP_SHORT;
  1270. if (cmd->flags & MMC_RSP_CRC)
  1271. flags |= SDHCI_CMD_CRC;
  1272. if (cmd->flags & MMC_RSP_OPCODE)
  1273. flags |= SDHCI_CMD_INDEX;
  1274. /* CMD19 is special in that the Data Present Select should be set */
  1275. if (cmd->data || mmc_op_tuning(cmd->cmd_code))
  1276. flags |= SDHCI_CMD_DATA;
  1277. timeout = rt_tick_get();
  1278. if (host->data_timeout)
  1279. timeout += rt_tick_from_millisecond(host->data_timeout * 1000);
  1280. else if (!cmd->data && cmd->busy_timeout > 9000)
  1281. timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * RT_TICK_PER_SECOND + RT_TICK_PER_SECOND;
  1282. else
  1283. timeout += 10 * RT_TICK_PER_SECOND;
  1284. sdhci_mod_timer(host, cmd->mrq, timeout);
  1285. if (host->use_external_dma)
  1286. sdhci_external_dma_pre_transfer(host, cmd);
  1287. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmd_code, flags), SDHCI_COMMAND);
  1288. return RT_TRUE;
  1289. }
  1290. /********************************************************* */
  1291. /* dma */
  1292. /********************************************************* */
  1293. static void __sdhci_finish_data(struct sdhci_host *host, rt_bool_t sw_data_timeout)
  1294. {
  1295. struct rt_mmcsd_cmd *data_cmd = host->data_cmd;
  1296. struct rt_mmcsd_data *data = host->data;
  1297. host->data = NULL;
  1298. host->data_cmd = NULL;
  1299. /*
  1300. * The controller needs a reset of internal state machines upon error
  1301. * conditions.
  1302. */
  1303. if (data->err)
  1304. {
  1305. if (!host->cmd || host->cmd == data_cmd)
  1306. sdhci_reset_for(host, REQUEST_ERROR);
  1307. else
  1308. sdhci_reset_for(host, REQUEST_ERROR_DATA_ONLY);
  1309. }
  1310. /*
  1311. * The specification states that the block count register must
  1312. * be updated, but it does not specify at what point in the
  1313. * data flow. That makes the register entirely useless to read
  1314. * back so we have to assume that nothing made it to the card
  1315. * in the event of an error.
  1316. */
  1317. if (data->err)
  1318. {
  1319. data->bytes_xfered = 0;
  1320. }
  1321. else
  1322. {
  1323. data->bytes_xfered = data->blksize * data->blks;
  1324. }
  1325. /*
  1326. * Need to send CMD12 if -
  1327. * a) open-ended multiblock transfer not using auto CMD12 (no CMD23)
  1328. * b) error in multiblock transfer
  1329. */
  1330. if (data->stop && ((!data->mrq->sbc && !sdhci_auto_cmd12(host, data->mrq)) || data->err))
  1331. {
  1332. /*
  1333. * 'cap_cmd_during_tfr' request must not use the command line
  1334. * after mmc_command_done() has been called. It is upper layer's
  1335. * responsibility to send the stop command if required.
  1336. */
  1337. if (data->mrq->cap_cmd_during_tfr)
  1338. {
  1339. __sdhci_finish_mrq(host, data->mrq);
  1340. }
  1341. else
  1342. {
  1343. /* Avoid triggering warning in sdhci_send_command() */
  1344. host->cmd = NULL;
  1345. if (!sdhci_send_command(host, data->stop))
  1346. {
  1347. if (sw_data_timeout)
  1348. {
  1349. /*
  1350. * This is anyway a sw data timeout, so
  1351. * give up now.
  1352. */
  1353. data->stop->err = -EIO;
  1354. __sdhci_finish_mrq(host, data->mrq);
  1355. }
  1356. else
  1357. {
  1358. host->deferred_cmd = data->stop;
  1359. }
  1360. }
  1361. }
  1362. }
  1363. else
  1364. {
  1365. __sdhci_finish_mrq(host, data->mrq);
  1366. }
  1367. }
  1368. static void sdhci_finish_data(struct sdhci_host *host)
  1369. {
  1370. __sdhci_finish_data(host, RT_FALSE);
  1371. }
  1372. /********************************************************* */
  1373. /* irq */
  1374. /********************************************************* */
  1375. static void sdhci_data_irq(struct sdhci_host *host, rt_uint32_t intmask)
  1376. {
  1377. rt_uint32_t command;
  1378. /*
  1379. * CMD19 generates _only_ Buffer Read Ready interrupt if
  1380. * use sdhci_send_tuning.
  1381. * Need to exclude this case: PIO mode and use mmc_send_tuning,
  1382. * If not, sdhci_transfer_pio will never be called, make the
  1383. * SDHCI_INT_DATA_AVAIL always there, stuck in irq storm.
  1384. */
  1385. if (intmask & SDHCI_INT_DATA_AVAIL && !host->data)
  1386. {
  1387. command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
  1388. if (command == MMC_SEND_TUNING_BLOCK || command == MMC_SEND_TUNING_BLOCK_HS200)
  1389. {
  1390. host->tuning_done = 1;
  1391. rt_wqueue_wakeup(&host->buf_ready_int, 0);
  1392. return;
  1393. }
  1394. }
  1395. if (!host->data)
  1396. {
  1397. struct rt_mmcsd_cmd *data_cmd = host->data_cmd;
  1398. /*
  1399. * The "data complete" interrupt is also used to
  1400. * indicate that a busy state has ended. See comment
  1401. * above in sdhci_cmd_irq().
  1402. */
  1403. if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY))
  1404. {
  1405. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  1406. {
  1407. host->data_cmd = NULL;
  1408. data_cmd->err = -ETIMEDOUT;
  1409. __sdhci_finish_mrq(host, data_cmd->mrq);
  1410. return;
  1411. }
  1412. if (intmask & SDHCI_INT_DATA_END)
  1413. {
  1414. host->data_cmd = NULL;
  1415. /*
  1416. * Some cards handle busy-end interrupt
  1417. * before the command completed, so make
  1418. * sure we do things in the proper order.
  1419. */
  1420. if (host->cmd == data_cmd)
  1421. return;
  1422. __sdhci_finish_mrq(host, data_cmd->mrq);
  1423. return;
  1424. }
  1425. }
  1426. /*
  1427. * SDHCI recovers from errors by resetting the cmd and data
  1428. * circuits. Until that is done, there very well might be more
  1429. * interrupts, so ignore them in that case.
  1430. */
  1431. if (host->pending_reset)
  1432. return;
  1433. rt_kprintf("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
  1434. mmc_hostname(host->mmc), (unsigned)intmask);
  1435. sdhci_dumpregs(host);
  1436. return;
  1437. }
  1438. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  1439. host->data->err = -ETIMEDOUT;
  1440. else if (intmask & SDHCI_INT_DATA_END_BIT)
  1441. host->data->err = -EILSEQ;
  1442. else if ((intmask & SDHCI_INT_DATA_CRC) && SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) != MMC_BUS_TEST_R)
  1443. {
  1444. host->data->err = -EILSEQ;
  1445. }
  1446. if (host->data->err)
  1447. {
  1448. sdhci_finish_data(host);
  1449. }
  1450. else
  1451. {
  1452. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  1453. sdhci_transfer_pio(host);
  1454. /*
  1455. * We currently don't do anything fancy with DMA
  1456. * boundaries, but as we can't disable the feature
  1457. * we need to at least restart the transfer.
  1458. *
  1459. * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
  1460. * should return a valid address to continue from, but as
  1461. * some controllers are faulty, don't trust them.
  1462. */
  1463. if (intmask & SDHCI_INT_DMA_END)
  1464. {
  1465. rt_uint32_t dmastart, dmanow;
  1466. dmastart = sdhci_sdma_address(host);
  1467. dmanow = dmastart + host->data->bytes_xfered;
  1468. /*
  1469. * Force update to the next DMA block boundary.
  1470. */
  1471. dmanow = (dmanow & ~((rt_uint32_t)SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + SDHCI_DEFAULT_BOUNDARY_SIZE;
  1472. host->data->bytes_xfered = dmanow - dmastart;
  1473. LOG_D("DMA base %pad, transferred 0x%06x bytes, next %pad\n",
  1474. &dmastart, host->data->bytes_xfered, &dmanow);
  1475. sdhci_set_sdma_addr(host, dmanow);
  1476. }
  1477. if (intmask & SDHCI_INT_DATA_END)
  1478. {
  1479. if (host->cmd == host->data_cmd)
  1480. {
  1481. /*
  1482. * Data managed to finish before the
  1483. * command completed. Make sure we do
  1484. * things in the proper order.
  1485. */
  1486. host->data_early = 1;
  1487. }
  1488. else
  1489. {
  1490. sdhci_finish_data(host);
  1491. }
  1492. }
  1493. }
  1494. }
  1495. static void sdhci_read_rsp_136(struct sdhci_host *host, struct rt_mmcsd_cmd *cmd)
  1496. {
  1497. int i, reg;
  1498. for (i = 0; i < 4; i++)
  1499. {
  1500. reg = SDHCI_RESPONSE + (3 - i) * 4;
  1501. cmd->resp[i] = sdhci_readl(host, reg);
  1502. }
  1503. if (host->quirks2 & SDHCI_QUIRK2_RSP_136_HAS_CRC)
  1504. return;
  1505. /* CRC is stripped so we need to do some shifting */
  1506. for (i = 0; i < 4; i++)
  1507. {
  1508. cmd->resp[i] <<= 8;
  1509. if (i != 3)
  1510. cmd->resp[i] |= cmd->resp[i + 1] >> 24;
  1511. }
  1512. }
  1513. static void sdhci_finish_command(struct sdhci_host *host)
  1514. {
  1515. struct rt_mmcsd_cmd *cmd = host->cmd;
  1516. host->cmd = NULL;
  1517. if (cmd->flags & MMC_RSP_PRESENT)
  1518. {
  1519. if (cmd->flags & MMC_RSP_136)
  1520. {
  1521. sdhci_read_rsp_136(host, cmd);
  1522. }
  1523. else
  1524. {
  1525. cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
  1526. }
  1527. }
  1528. /*
  1529. * The host can send and interrupt when the busy state has
  1530. * ended, allowing us to wait without wasting CPU cycles.
  1531. * The busy signal uses DAT0 so this is similar to waiting
  1532. * for data to complete.
  1533. *
  1534. * Note: The 1.0 specification is a bit ambiguous about this
  1535. * feature so there might be some problems with older
  1536. * controllers.
  1537. */
  1538. if (cmd->flags & MMC_RSP_BUSY)
  1539. {
  1540. if (cmd->data)
  1541. {
  1542. LOG_D("Cannot wait for busy signal when also doing a data transfer");
  1543. }
  1544. else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && cmd == host->data_cmd)
  1545. {
  1546. /* Command complete before busy is ended */
  1547. return;
  1548. }
  1549. }
  1550. /* Finished CMD23, now send actual command. */
  1551. if (cmd == cmd->mrq->sbc)
  1552. {
  1553. if (!sdhci_send_command(host, cmd->mrq->cmd))
  1554. {
  1555. host->deferred_cmd = cmd->mrq->cmd;
  1556. }
  1557. }
  1558. else
  1559. {
  1560. /* Processed actual command. */
  1561. if (host->data && host->data_early)
  1562. sdhci_finish_data(host);
  1563. if (!cmd->data)
  1564. __sdhci_finish_mrq(host, cmd->mrq);
  1565. }
  1566. }
  1567. static void sdhci_cmd_irq(struct sdhci_host *host, rt_uint32_t intmask, rt_uint32_t *intmask_p)
  1568. {
  1569. /* Handle auto-CMD12 error */
  1570. if (intmask & SDHCI_INT_AUTO_CMD_ERR && host->data_cmd)
  1571. {
  1572. struct rt_mmcsd_req *mrq = host->data_cmd->mrq;
  1573. rt_uint16_t auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
  1574. int data_err_bit = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? SDHCI_INT_DATA_TIMEOUT : SDHCI_INT_DATA_CRC;
  1575. /* Treat auto-CMD12 error the same as data error */
  1576. if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
  1577. {
  1578. *intmask_p |= data_err_bit;
  1579. return;
  1580. }
  1581. }
  1582. if (!host->cmd)
  1583. {
  1584. /*
  1585. * SDHCI recovers from errors by resetting the cmd and data
  1586. * circuits. Until that is done, there very well might be more
  1587. * interrupts, so ignore them in that case.
  1588. */
  1589. if (host->pending_reset)
  1590. return;
  1591. rt_kprintf("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
  1592. mmc_hostname(host->mmc), (unsigned)intmask);
  1593. sdhci_dumpregs(host);
  1594. return;
  1595. }
  1596. if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  1597. {
  1598. if (intmask & SDHCI_INT_TIMEOUT)
  1599. host->cmd->err = -ETIMEDOUT;
  1600. else
  1601. host->cmd->err = -EILSEQ;
  1602. /* Treat data command CRC error the same as data CRC error */
  1603. if (host->cmd->data && (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == SDHCI_INT_CRC)
  1604. {
  1605. host->cmd = NULL;
  1606. *intmask_p |= SDHCI_INT_DATA_CRC;
  1607. return;
  1608. }
  1609. __sdhci_finish_mrq(host, host->cmd->mrq);
  1610. return;
  1611. }
  1612. /* Handle auto-CMD23 error */
  1613. if (intmask & SDHCI_INT_AUTO_CMD_ERR)
  1614. {
  1615. struct rt_mmcsd_req *mrq = host->cmd->mrq;
  1616. rt_uint16_t auto_cmd_status = sdhci_readw(host, SDHCI_AUTO_CMD_STATUS);
  1617. int err = (auto_cmd_status & SDHCI_AUTO_CMD_TIMEOUT) ? -ETIMEDOUT : -EILSEQ;
  1618. if (mrq->sbc && (host->flags & SDHCI_AUTO_CMD23))
  1619. {
  1620. mrq->sbc->err = err;
  1621. __sdhci_finish_mrq(host, mrq);
  1622. return;
  1623. }
  1624. }
  1625. if (intmask & SDHCI_INT_RESPONSE)
  1626. sdhci_finish_command(host);
  1627. }
  1628. static void sdhci_irq(int irq, void *dev_id)
  1629. {
  1630. struct rt_mmcsd_req *mrqs_done[SDHCI_MAX_MRQS] = {0};
  1631. struct sdhci_host *host = dev_id;
  1632. rt_uint32_t intmask, mask, unexpected = 0;
  1633. int max_loops = 16;
  1634. int i, result;
  1635. rt_spin_lock(&host->lock);
  1636. if (host->runtime_suspended)
  1637. {
  1638. rt_spin_unlock(&host->lock);
  1639. }
  1640. intmask = sdhci_readl(host, SDHCI_INT_STATUS);
  1641. if (!intmask || intmask == 0xffffffff)
  1642. {
  1643. result = 0;
  1644. goto out;
  1645. }
  1646. do {
  1647. LOG_D("IRQ status 0x%08x\n", intmask);
  1648. if (host->ops->irq)
  1649. {
  1650. intmask = host->ops->irq(host, intmask);
  1651. if (!intmask)
  1652. goto cont;
  1653. }
  1654. /* Clear selected interrupts. */
  1655. mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | SDHCI_INT_BUS_POWER);
  1656. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  1657. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  1658. {
  1659. rt_uint32_t present = sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT;
  1660. /*
  1661. * There is a observation on i.mx esdhc. INSERT
  1662. * bit will be immediately set again when it gets
  1663. * cleared, if a card is inserted. We have to mask
  1664. * the irq to prevent interrupt storm which will
  1665. * freeze the system. And the REMOVE gets the
  1666. * same situation.
  1667. *
  1668. * More testing are needed here to ensure it works
  1669. * for other platforms though.
  1670. */
  1671. host->ier &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  1672. host->ier |= present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
  1673. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  1674. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  1675. sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
  1676. host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  1677. result = RT_EOK;
  1678. }
  1679. if (intmask & SDHCI_INT_CMD_MASK)
  1680. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, &intmask);
  1681. if (intmask & SDHCI_INT_DATA_MASK)
  1682. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  1683. if (intmask & SDHCI_INT_BUS_POWER)
  1684. rt_kprintf("%s: Card is consuming too much power!\n",
  1685. mmc_hostname(host->mmc));
  1686. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | SDHCI_INT_RETUNE | SDHCI_INT_CARD_INT);
  1687. if (intmask)
  1688. {
  1689. unexpected |= intmask;
  1690. sdhci_writel(host, intmask, SDHCI_INT_STATUS);
  1691. }
  1692. cont:
  1693. intmask = sdhci_readl(host, SDHCI_INT_STATUS);
  1694. } while (intmask && --max_loops);
  1695. /* Determine if mrqs can be completed immediately */
  1696. for (i = 0; i < SDHCI_MAX_MRQS; i++)
  1697. {
  1698. struct rt_mmcsd_req *mrq = host->mrqs_done[i];
  1699. if (!mrq)
  1700. continue;
  1701. if (sdhci_defer_done(host, mrq))
  1702. {
  1703. result = RT_EOK;
  1704. }
  1705. else
  1706. {
  1707. mrqs_done[i] = mrq;
  1708. host->mrqs_done[i] = NULL;
  1709. }
  1710. }
  1711. out:
  1712. if (host->deferred_cmd)
  1713. result = RT_EOK;
  1714. rt_spin_unlock(&host->lock);
  1715. /* Process mrqs ready for immediate completion */
  1716. for (i = 0; i < SDHCI_MAX_MRQS; i++)
  1717. {
  1718. if (!mrqs_done[i])
  1719. continue;
  1720. if (host->ops->request_done)
  1721. host->ops->request_done(host, mrqs_done[i]);
  1722. else
  1723. mmc_request_done(host->mmc, mrqs_done[i]);
  1724. }
  1725. if (unexpected)
  1726. {
  1727. sdhci_dumpregs(host);
  1728. }
  1729. if (result == RT_EOK)
  1730. {
  1731. rt_workqueue_submit_work(host->irq_wq, &host->irq_work, 0);
  1732. }
  1733. }
  1734. static rt_bool_t sdhci_send_command_retry(struct sdhci_host *host,
  1735. struct rt_mmcsd_cmd *cmd,
  1736. unsigned long flags)
  1737. {
  1738. struct rt_mmcsd_cmd *deferred_cmd = host->deferred_cmd;
  1739. int timeout = 10; /* Approx. 10 ms */
  1740. rt_bool_t present;
  1741. while (!sdhci_send_command(host, cmd))
  1742. {
  1743. if (!timeout--)
  1744. {
  1745. rt_kprintf("%s: Controller never released inhibit bit(s).\n",
  1746. mmc_hostname(host->mmc));
  1747. sdhci_dumpregs(host);
  1748. cmd->err = -EIO;
  1749. return RT_FALSE;
  1750. }
  1751. rt_spin_unlock_irqrestore(&host->lock, flags);
  1752. rt_thread_mdelay(1);
  1753. present = host->mmc->ops->get_cd(host->mmc);
  1754. flags = rt_spin_lock_irqsave(&host->lock);
  1755. /* A deferred command might disappear, handle that */
  1756. if (cmd == deferred_cmd && cmd != host->deferred_cmd)
  1757. return RT_TRUE;
  1758. if (sdhci_present_error(host, cmd, present))
  1759. return RT_FALSE;
  1760. }
  1761. if (cmd == host->deferred_cmd)
  1762. host->deferred_cmd = NULL;
  1763. return RT_TRUE;
  1764. }
  1765. static rt_bool_t sdhci_request_done(struct sdhci_host *host)
  1766. {
  1767. rt_base_t flags;
  1768. struct rt_mmcsd_req *mrq;
  1769. int i;
  1770. flags = rt_spin_lock_irqsave(&host->lock);
  1771. for (i = 0; i < SDHCI_MAX_MRQS; i++)
  1772. {
  1773. mrq = host->mrqs_done[i];
  1774. if (mrq)
  1775. break;
  1776. }
  1777. if (!mrq)
  1778. {
  1779. rt_spin_unlock_irqrestore(&host->lock, flags);
  1780. return RT_TRUE;
  1781. }
  1782. /*
  1783. * The controller needs a reset of internal state machines
  1784. * upon error conditions.
  1785. */
  1786. if (sdhci_needs_reset(host, mrq))
  1787. {
  1788. /*
  1789. * Do not finish until command and data lines are available for
  1790. * reset. Note there can only be one other mrq, so it cannot
  1791. * also be in mrqs_done, otherwise host->cmd and host->data_cmd
  1792. * would both be null.
  1793. */
  1794. if (host->cmd || host->data_cmd)
  1795. {
  1796. rt_spin_unlock_irqrestore(&host->lock, flags);
  1797. return RT_TRUE;
  1798. }
  1799. /* Some controllers need this kick or reset won't work here */
  1800. if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
  1801. /* This is to force an update */
  1802. host->ops->set_clock(host, host->clock);
  1803. sdhci_do_reset(host, SDHCI_RESET_CMD);
  1804. sdhci_do_reset(host, SDHCI_RESET_DATA);
  1805. host->pending_reset = RT_FALSE;
  1806. }
  1807. /*
  1808. * Always unmap the data buffers if they were mapped by
  1809. * sdhci_prepare_data() whenever we finish with a request.
  1810. * This avoids leaking DMA mappings on error.
  1811. */
  1812. if (host->flags & SDHCI_REQ_USE_DMA)
  1813. {
  1814. struct rt_mmcsd_data *data = mrq->data;
  1815. if (host->use_external_dma && data && (mrq->cmd->err || data->err))
  1816. {
  1817. host->mrqs_done[i] = NULL;
  1818. sdhci_set_mrq_done(host, mrq);
  1819. }
  1820. }
  1821. host->mrqs_done[i] = NULL;
  1822. rt_spin_unlock_irqrestore(&host->lock, flags);
  1823. if (host->ops->request_done)
  1824. host->ops->request_done(host, mrq);
  1825. else
  1826. mmc_request_done(host->mmc, mrq);
  1827. return RT_FALSE;
  1828. }
  1829. static void sdhci_thread_irq(struct rt_work *work, void *work_data)
  1830. {
  1831. struct sdhci_host *host = work_data;
  1832. struct rt_mmcsd_cmd *cmd;
  1833. rt_base_t flags;
  1834. rt_uint32_t isr;
  1835. while (!sdhci_request_done(host));
  1836. flags = rt_spin_lock_irqsave(&host->lock);
  1837. isr = host->thread_isr;
  1838. host->thread_isr = 0;
  1839. cmd = host->deferred_cmd;
  1840. if (cmd && !sdhci_send_command_retry(host, cmd, flags))
  1841. sdhci_finish_mrq(host, cmd->mrq);
  1842. rt_spin_unlock_irqrestore(&host->lock, flags);
  1843. if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE))
  1844. {
  1845. struct mmc_host *mmc = host->mmc;
  1846. mmc->ops->card_event(mmc);
  1847. }
  1848. }
  1849. void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
  1850. {
  1851. struct sdhci_host *host = mmc_priv(mmc);
  1852. rt_uint32_t flags;
  1853. flags = rt_spin_lock_irqsave(&host->lock);
  1854. sdhci_enable_sdio_irq_nolock(host, enable);
  1855. rt_spin_unlock_irqrestore(&host->lock, flags);
  1856. }
  1857. /********************************************************* */
  1858. /* request */
  1859. /********************************************************* */
  1860. void sdhci_request(struct mmc_host *mmc, struct rt_mmcsd_req *mrq)
  1861. {
  1862. struct sdhci_host *host = mmc_priv(mmc);
  1863. struct rt_mmcsd_cmd *cmd;
  1864. rt_base_t flags;
  1865. rt_bool_t present;
  1866. /* Firstly check card presence */
  1867. present = mmc->ops->get_cd(mmc);
  1868. flags = rt_spin_lock_irqsave(&host->lock);
  1869. if (sdhci_present_error(host, mrq->cmd, present))
  1870. goto out_finish;
  1871. cmd = sdhci_manual_cmd23(host, mrq) ? mrq->sbc : mrq->cmd;
  1872. if (!sdhci_send_command_retry(host, cmd, flags))
  1873. goto out_finish;
  1874. rt_spin_unlock_irqrestore(&host->lock, flags);
  1875. return;
  1876. out_finish:
  1877. sdhci_finish_mrq(host, mrq);
  1878. rt_spin_unlock_irqrestore(&host->lock, flags);
  1879. }
  1880. static void sdhci_complete_work(struct rt_work *work, void *work_data)
  1881. {
  1882. struct sdhci_host *host = work_data;
  1883. while (!sdhci_request_done(host));
  1884. }
  1885. /********************************************************* */
  1886. /* timer */
  1887. /********************************************************* */
  1888. static void sdhci_timeout_timer(void *parameter)
  1889. {
  1890. struct sdhci_host *host = parameter;
  1891. rt_base_t flags;
  1892. flags = rt_spin_lock_irqsave(&host->lock);
  1893. if (host->cmd && !sdhci_data_line_cmd(host->cmd))
  1894. {
  1895. rt_kprintf("%s: Timeout waiting for hardware cmd interrupt.\n",
  1896. mmc_hostname(host->mmc));
  1897. sdhci_dumpregs(host);
  1898. host->cmd->err = -ETIMEDOUT;
  1899. sdhci_finish_mrq(host, host->cmd->mrq);
  1900. }
  1901. rt_spin_unlock_irqrestore(&host->lock, flags);
  1902. }
  1903. static void sdhci_timeout_data_timer(void *parameter)
  1904. {
  1905. struct sdhci_host *host = parameter;
  1906. rt_base_t flags;
  1907. flags = rt_spin_lock_irqsave(&host->lock);
  1908. if (host->data || host->data_cmd || (host->cmd && sdhci_data_line_cmd(host->cmd)))
  1909. {
  1910. rt_kprintf("%s: Timeout waiting for hardware interrupt.\n",
  1911. mmc_hostname(host->mmc));
  1912. sdhci_dumpregs(host);
  1913. if (host->data)
  1914. {
  1915. host->data->err = -ETIMEDOUT;
  1916. __sdhci_finish_data(host, RT_TRUE);
  1917. rt_workqueue_submit_work(host->complete_wq, &host->complete_work, 0);
  1918. }
  1919. else if (host->data_cmd)
  1920. {
  1921. host->data_cmd->err = -ETIMEDOUT;
  1922. sdhci_finish_mrq(host, host->data_cmd->mrq);
  1923. }
  1924. else
  1925. {
  1926. host->cmd->err = -ETIMEDOUT;
  1927. sdhci_finish_mrq(host, host->cmd->mrq);
  1928. }
  1929. }
  1930. rt_spin_unlock_irqrestore(&host->lock, flags);
  1931. }
  1932. /********************************************************* */
  1933. /* tuning */
  1934. /********************************************************* */
  1935. int sdhci_execute_tuning(struct mmc_host *mmc, rt_uint32_t opcode)
  1936. {
  1937. struct sdhci_host *host = mmc_priv(mmc);
  1938. int err = 0;
  1939. unsigned int tuning_count = 0;
  1940. rt_bool_t hs400_tuning;
  1941. hs400_tuning = host->flags & SDHCI_HS400_TUNING;
  1942. if (host->tuning_mode == SDHCI_TUNING_MODE_1)
  1943. tuning_count = host->tuning_count;
  1944. /*
  1945. * The Host Controller needs tuning in case of SDR104 and DDR50
  1946. * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
  1947. * the Capabilities register.
  1948. * If the Host Controller supports the HS200 mode then the
  1949. * tuning function has to be executed.
  1950. */
  1951. switch (host->timing)
  1952. {
  1953. /* HS400 tuning is done in HS200 mode */
  1954. case MMC_TIMING_MMC_HS400:
  1955. err = -EINVAL;
  1956. goto out;
  1957. case MMC_TIMING_MMC_HS200:
  1958. /*
  1959. * Periodic re-tuning for HS400 is not expected to be needed, so
  1960. * disable it here.
  1961. */
  1962. if (hs400_tuning)
  1963. tuning_count = 0;
  1964. break;
  1965. case MMC_TIMING_UHS_SDR104:
  1966. case MMC_TIMING_UHS_DDR50:
  1967. break;
  1968. case MMC_TIMING_UHS_SDR50:
  1969. if (host->flags & SDHCI_SDR50_NEEDS_TUNING)
  1970. break;
  1971. fallthrough;
  1972. default:
  1973. goto out;
  1974. }
  1975. if (host->ops->platform_execute_tuning)
  1976. {
  1977. err = host->ops->platform_execute_tuning(host, opcode);
  1978. goto out;
  1979. }
  1980. mmc->retune_period = tuning_count;
  1981. if (host->tuning_delay < 0)
  1982. host->tuning_delay = opcode == MMC_SEND_TUNING_BLOCK;
  1983. sdhci_start_tuning(host);
  1984. host->tuning_err = __sdhci_execute_tuning(host, opcode);
  1985. sdhci_end_tuning(host);
  1986. out:
  1987. host->flags &= ~SDHCI_HS400_TUNING;
  1988. return err;
  1989. }
  1990. int __sdhci_execute_tuning(struct sdhci_host *host, rt_uint32_t opcode)
  1991. {
  1992. int i;
  1993. /*
  1994. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  1995. * of loops reaches tuning loop count.
  1996. */
  1997. for (i = 0; i < host->tuning_loop_count; i++)
  1998. {
  1999. rt_uint16_t ctrl;
  2000. sdhci_send_tuning(host, opcode);
  2001. if (!host->tuning_done)
  2002. {
  2003. sdhci_abort_tuning(host, opcode);
  2004. return -ETIMEDOUT;
  2005. }
  2006. /* Spec does not require a delay between tuning cycles */
  2007. if (host->tuning_delay > 0)
  2008. rt_thread_mdelay(host->tuning_delay);
  2009. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  2010. if (!(ctrl & SDHCI_CTRL_EXEC_TUNING))
  2011. {
  2012. if (ctrl & SDHCI_CTRL_TUNED_CLK)
  2013. return 0; /* Success! */
  2014. break;
  2015. }
  2016. }
  2017. LOG_D("%s: Tuning failed, falling back to fixed sampling clock\n",
  2018. mmc_hostname(host->mmc));
  2019. sdhci_reset_tuning(host);
  2020. return -EAGAIN;
  2021. }
  2022. void sdhci_start_tuning(struct sdhci_host *host)
  2023. {
  2024. rt_uint16_t ctrl;
  2025. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  2026. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  2027. if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
  2028. ctrl |= SDHCI_CTRL_TUNED_CLK;
  2029. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  2030. /*
  2031. * As per the Host Controller spec v3.00, tuning command
  2032. * generates Buffer Read Ready interrupt, so enable that.
  2033. *
  2034. * Note: The spec clearly says that when tuning sequence
  2035. * is being performed, the controller does not generate
  2036. * interrupts other than Buffer Read Ready interrupt. But
  2037. * to make sure we don't hit a controller bug, we _only_
  2038. * enable Buffer Read Ready interrupt here.
  2039. */
  2040. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  2041. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  2042. }
  2043. void sdhci_end_tuning(struct sdhci_host *host)
  2044. {
  2045. sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
  2046. sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
  2047. }
  2048. void sdhci_abort_tuning(struct sdhci_host *host, rt_uint32_t opcode)
  2049. {
  2050. sdhci_reset_tuning(host);
  2051. sdhci_reset_for(host, TUNING_ABORT);
  2052. sdhci_end_tuning(host);
  2053. }
  2054. void sdhci_send_tuning(struct sdhci_host *host, rt_uint32_t opcode)
  2055. {
  2056. struct mmc_host *mmc = host->mmc;
  2057. struct rt_mmcsd_cmd cmd = {};
  2058. struct rt_mmcsd_req mrq = {};
  2059. unsigned long flags;
  2060. rt_uint32_t b = host->sdma_boundary;
  2061. flags = rt_spin_lock_irqsave(&host->lock);
  2062. cmd.cmd_code = opcode;
  2063. cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
  2064. cmd.mrq = &mrq;
  2065. mrq.cmd = &cmd;
  2066. /*
  2067. * In response to CMD19, the card sends 64 bytes of tuning
  2068. * block to the Host Controller. So we set the block size
  2069. * to 64 here.
  2070. */
  2071. if (cmd.cmd_code == MMC_SEND_TUNING_BLOCK_HS200 && mmc->ios.bus_width == MMC_BUS_WIDTH_8)
  2072. sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 128), SDHCI_BLOCK_SIZE);
  2073. else
  2074. sdhci_writew(host, SDHCI_MAKE_BLKSZ(b, 64), SDHCI_BLOCK_SIZE);
  2075. /*
  2076. * The tuning block is sent by the card to the host controller.
  2077. * So we set the TRNS_READ bit in the Transfer Mode register.
  2078. * This also takes care of setting DMA Enable and Multi Block
  2079. * Select in the same register to 0.
  2080. */
  2081. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  2082. if (!sdhci_send_command_retry(host, &cmd, flags))
  2083. {
  2084. rt_spin_unlock_irqrestore(&host->lock, flags);
  2085. host->tuning_done = 0;
  2086. return;
  2087. }
  2088. host->cmd = NULL;
  2089. sdhci_del_timer(host, &mrq);
  2090. host->tuning_done = 0;
  2091. rt_spin_unlock_irqrestore(&host->lock, flags);
  2092. }
  2093. void sdhci_reset_tuning(struct sdhci_host *host)
  2094. {
  2095. rt_uint16_t ctrl;
  2096. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  2097. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  2098. ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
  2099. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  2100. }
  2101. /********************************************************* */
  2102. /* error */
  2103. /********************************************************* */
  2104. void sdhci_dumpregs(struct sdhci_host *host)
  2105. {
  2106. #define SDHCI_DUMP rt_kprintf
  2107. SDHCI_DUMP("============ SDHCI REGISTER DUMP ===========\n");
  2108. SDHCI_DUMP("Sys addr: 0x%08x | Version: 0x%08x\n",
  2109. sdhci_readl(host, SDHCI_DMA_ADDRESS),
  2110. sdhci_readw(host, SDHCI_HOST_VERSION));
  2111. SDHCI_DUMP("Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  2112. sdhci_readw(host, SDHCI_BLOCK_SIZE),
  2113. sdhci_readw(host, SDHCI_BLOCK_COUNT));
  2114. SDHCI_DUMP("Argument: 0x%08x | Trn mode: 0x%08x\n",
  2115. sdhci_readl(host, SDHCI_ARGUMENT),
  2116. sdhci_readw(host, SDHCI_TRANSFER_MODE));
  2117. SDHCI_DUMP("Present: 0x%08x | Host ctl: 0x%08x\n",
  2118. sdhci_readl(host, SDHCI_PRESENT_STATE),
  2119. sdhci_readb(host, SDHCI_HOST_CONTROL));
  2120. SDHCI_DUMP("Power: 0x%08x | Blk gap: 0x%08x\n",
  2121. sdhci_readb(host, SDHCI_POWER_CONTROL),
  2122. sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  2123. SDHCI_DUMP("Wake-up: 0x%08x | Clock: 0x%08x\n",
  2124. sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  2125. sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  2126. SDHCI_DUMP("Timeout: 0x%08x | Int stat: 0x%08x\n",
  2127. sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  2128. sdhci_readl(host, SDHCI_INT_STATUS));
  2129. SDHCI_DUMP("Int enab: 0x%08x | Sig enab: 0x%08x\n",
  2130. sdhci_readl(host, SDHCI_INT_ENABLE),
  2131. sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  2132. SDHCI_DUMP("ACmd stat: 0x%08x | Slot int: 0x%08x\n",
  2133. sdhci_readw(host, SDHCI_AUTO_CMD_STATUS),
  2134. sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  2135. SDHCI_DUMP("Caps: 0x%08x | Caps_1: 0x%08x\n",
  2136. sdhci_readl(host, SDHCI_CAPABILITIES),
  2137. sdhci_readl(host, SDHCI_CAPABILITIES_1));
  2138. SDHCI_DUMP("Cmd: 0x%08x | Max curr: 0x%08x\n",
  2139. sdhci_readw(host, SDHCI_COMMAND),
  2140. sdhci_readl(host, SDHCI_MAX_CURRENT));
  2141. SDHCI_DUMP("Resp[0]: 0x%08x | Resp[1]: 0x%08x\n",
  2142. sdhci_readl(host, SDHCI_RESPONSE),
  2143. sdhci_readl(host, SDHCI_RESPONSE + 4));
  2144. SDHCI_DUMP("Resp[2]: 0x%08x | Resp[3]: 0x%08x\n",
  2145. sdhci_readl(host, SDHCI_RESPONSE + 8),
  2146. sdhci_readl(host, SDHCI_RESPONSE + 12));
  2147. SDHCI_DUMP("Host ctl2: 0x%08x\n",
  2148. sdhci_readw(host, SDHCI_HOST_CONTROL2));
  2149. if (host->ops->dump_vendor_regs)
  2150. host->ops->dump_vendor_regs(host);
  2151. SDHCI_DUMP("============================================\n");
  2152. }
  2153. static const struct mmc_host_ops sdhci_ops = {
  2154. .request = sdhci_request,
  2155. .set_ios = sdhci_set_ios,
  2156. .get_cd = sdhci_get_cd,
  2157. .get_ro = sdhci_get_ro,
  2158. .enable_sdio_irq = sdhci_enable_sdio_irq,
  2159. .ack_sdio_irq = sdhci_ack_sdio_irq,
  2160. .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
  2161. .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
  2162. .execute_tuning = sdhci_execute_tuning,
  2163. .card_event = sdhci_card_event,
  2164. .card_busy = sdhci_card_busy,
  2165. };
  2166. void sdhci_remove_host(struct sdhci_host *host, int dead)
  2167. {
  2168. struct mmc_host *mmc = host->mmc;
  2169. unsigned long flags;
  2170. if (dead)
  2171. {
  2172. flags = rt_spin_lock_irqsave(&host->lock);
  2173. host->flags |= SDHCI_DEVICE_DEAD;
  2174. if (sdhci_has_requests(host))
  2175. {
  2176. rt_kprintf("%s: Controller removed during "
  2177. " transfer!\n",
  2178. mmc_hostname(mmc));
  2179. sdhci_error_out_mrqs(host, -ENOMEDIUM);
  2180. }
  2181. rt_spin_unlock_irqrestore(&host->lock, flags);
  2182. }
  2183. sdhci_set_card_detection(host, RT_FALSE);
  2184. mmc_remove_host(mmc);
  2185. if (!dead)
  2186. sdhci_reset_for_all(host);
  2187. sdhci_writel(host, 0, SDHCI_INT_ENABLE);
  2188. sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
  2189. rt_timer_delete(&host->timer);
  2190. rt_timer_delete(&host->data_timer);
  2191. rt_workqueue_destroy(host->complete_wq);
  2192. if (host->use_external_dma)
  2193. sdhci_external_dma_release(host);
  2194. host->align_buffer = NULL;
  2195. }
  2196. rt_uint16_t sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
  2197. unsigned int *actual_clock)
  2198. {
  2199. int div = 0; /* Initialized for compiler warning */
  2200. int real_div = div, clk_mul = 1;
  2201. rt_uint16_t clk = 0;
  2202. rt_bool_t switch_base_clk = RT_FALSE;
  2203. if (host->version >= SDHCI_SPEC_300)
  2204. {
  2205. if (host->preset_enabled)
  2206. {
  2207. rt_uint16_t pre_val;
  2208. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  2209. pre_val = sdhci_get_preset_value(host);
  2210. div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
  2211. if (host->clk_mul && (pre_val & SDHCI_PRESET_CLKGEN_SEL))
  2212. {
  2213. clk = SDHCI_PROG_CLOCK_MODE;
  2214. real_div = div + 1;
  2215. clk_mul = host->clk_mul;
  2216. }
  2217. else
  2218. {
  2219. real_div = max_t(int, 1, div << 1);
  2220. }
  2221. goto clock_set;
  2222. }
  2223. /*
  2224. * Check if the Host Controller supports Programmable Clock
  2225. * Mode.
  2226. */
  2227. if (host->clk_mul)
  2228. {
  2229. for (div = 1; div <= 1024; div++)
  2230. {
  2231. if ((host->max_clk * host->clk_mul / div)
  2232. <= clock)
  2233. break;
  2234. }
  2235. if ((host->max_clk * host->clk_mul / div) <= clock)
  2236. {
  2237. /*
  2238. * Set Programmable Clock Mode in the Clock
  2239. * Control register.
  2240. */
  2241. clk = SDHCI_PROG_CLOCK_MODE;
  2242. real_div = div;
  2243. clk_mul = host->clk_mul;
  2244. div--;
  2245. }
  2246. else
  2247. {
  2248. /*
  2249. * Divisor can be too small to reach clock
  2250. * speed requirement. Then use the base clock.
  2251. */
  2252. switch_base_clk = RT_TRUE;
  2253. }
  2254. }
  2255. if (!host->clk_mul || switch_base_clk)
  2256. {
  2257. /* Version 3.00 divisors must be a multiple of 2. */
  2258. if (host->max_clk <= clock)
  2259. div = 1;
  2260. else
  2261. {
  2262. for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
  2263. div += 2)
  2264. {
  2265. if ((host->max_clk / div) <= clock)
  2266. break;
  2267. }
  2268. }
  2269. real_div = div;
  2270. div >>= 1;
  2271. if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
  2272. && !div && host->max_clk <= 25000000)
  2273. div = 1;
  2274. }
  2275. }
  2276. else
  2277. {
  2278. /* Version 2.00 divisors must be a power of 2. */
  2279. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2)
  2280. {
  2281. if ((host->max_clk / div) <= clock)
  2282. break;
  2283. }
  2284. real_div = div;
  2285. div >>= 1;
  2286. }
  2287. clock_set:
  2288. if (real_div)
  2289. *actual_clock = (host->max_clk * clk_mul) / real_div;
  2290. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  2291. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  2292. << SDHCI_DIVIDER_HI_SHIFT;
  2293. return clk;
  2294. }
  2295. void sdhci_enable_clk(struct sdhci_host *host, rt_uint16_t clk)
  2296. {
  2297. long timeout;
  2298. clk |= SDHCI_CLOCK_INT_EN;
  2299. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  2300. /* Wait max 150 ms */
  2301. timeout = rt_tick_from_millisecond(150);
  2302. while (1)
  2303. {
  2304. timeout = timeout - rt_tick_get();
  2305. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  2306. if (clk & SDHCI_CLOCK_INT_STABLE)
  2307. break;
  2308. if (timeout < 0)
  2309. {
  2310. rt_kprintf("%s: Internal clock never stabilised.\n",
  2311. mmc_hostname(host->mmc));
  2312. sdhci_dumpregs(host);
  2313. return;
  2314. }
  2315. rt_hw_us_delay(10);
  2316. }
  2317. if (host->version >= SDHCI_SPEC_410 && host->v4_mode)
  2318. {
  2319. clk |= SDHCI_CLOCK_PLL_EN;
  2320. clk &= ~SDHCI_CLOCK_INT_STABLE;
  2321. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  2322. /* Wait max 150 ms */
  2323. timeout = rt_tick_from_millisecond(150);
  2324. while (1)
  2325. {
  2326. timeout = timeout - rt_tick_get();
  2327. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  2328. if (clk & SDHCI_CLOCK_INT_STABLE)
  2329. break;
  2330. if (timeout < 0)
  2331. {
  2332. rt_kprintf("%s: PLL clock never stabilised.\n",
  2333. mmc_hostname(host->mmc));
  2334. sdhci_dumpregs(host);
  2335. return;
  2336. }
  2337. rt_hw_us_delay(10);
  2338. }
  2339. }
  2340. clk |= SDHCI_CLOCK_CARD_EN;
  2341. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  2342. }
  2343. void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  2344. {
  2345. rt_uint16_t clk;
  2346. host->mmc->actual_clock = 0;
  2347. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  2348. if (clock == 0)
  2349. return;
  2350. clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
  2351. sdhci_enable_clk(host, clk);
  2352. }
  2353. void __sdhci_read_caps(struct sdhci_host *host, const rt_uint16_t *ver,
  2354. const rt_uint32_t *caps, const rt_uint32_t *caps1)
  2355. {
  2356. rt_uint16_t v;
  2357. rt_uint64_t dt_caps_mask = 0;
  2358. rt_uint64_t dt_caps = 0;
  2359. if (host->read_caps)
  2360. return;
  2361. host->read_caps = RT_TRUE;
  2362. if (debug_quirks)
  2363. host->quirks = debug_quirks;
  2364. if (debug_quirks2)
  2365. host->quirks2 = debug_quirks2;
  2366. sdhci_reset_for_all(host);
  2367. if (host->v4_mode)
  2368. sdhci_do_enable_v4_mode(host);
  2369. #ifdef RT_USING_OFW
  2370. rt_ofw_prop_read_u64(mmc_dev(host->mmc)->ofw_node,
  2371. "sdhci-caps-mask", &dt_caps_mask);
  2372. rt_ofw_prop_read_u64(mmc_dev(host->mmc)->ofw_node,
  2373. "sdhci-caps", &dt_caps);
  2374. #endif
  2375. v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
  2376. host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  2377. if (caps)
  2378. {
  2379. host->caps = *caps;
  2380. }
  2381. else
  2382. {
  2383. host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  2384. host->caps &= ~lower_32_bits(dt_caps_mask);
  2385. host->caps |= lower_32_bits(dt_caps);
  2386. }
  2387. if (host->version < SDHCI_SPEC_300)
  2388. return;
  2389. if (caps1)
  2390. {
  2391. host->caps1 = *caps1;
  2392. }
  2393. else
  2394. {
  2395. host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  2396. host->caps1 &= ~upper_32_bits(dt_caps_mask);
  2397. host->caps1 |= upper_32_bits(dt_caps);
  2398. }
  2399. }
  2400. struct sdhci_host *sdhci_alloc_host(struct rt_device *dev,
  2401. size_t priv_size)
  2402. {
  2403. struct mmc_host *mmc;
  2404. struct sdhci_host *host;
  2405. mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
  2406. if (!mmc)
  2407. return NULL;
  2408. host = mmc_priv(mmc);
  2409. host->mmc = mmc;
  2410. host->mmc_host_ops = sdhci_ops;
  2411. mmc->ops = &host->mmc_host_ops;
  2412. host->flags = SDHCI_SIGNALING_330;
  2413. host->cqe_ier = SDHCI_CQE_INT_MASK;
  2414. host->cqe_err_ier = SDHCI_CQE_INT_ERR_MASK;
  2415. host->tuning_delay = -1;
  2416. host->tuning_loop_count = MAX_TUNING_LOOP;
  2417. host->sdma_boundary = SDHCI_DEFAULT_BOUNDARY_ARG;
  2418. /*
  2419. * The DMA table descriptor count is calculated as the maximum
  2420. * number of segments times 2, to allow for an alignment
  2421. * descriptor for each segment, plus 1 for a nop end descriptor.
  2422. */
  2423. host->max_timeout_count = 0xE;
  2424. return host;
  2425. }
  2426. int sdhci_setup_host(struct sdhci_host *host)
  2427. {
  2428. struct mmc_host *mmc;
  2429. size_t max_current_caps;
  2430. unsigned int ocr_avail;
  2431. unsigned int override_timeout_clk;
  2432. size_t max_clk;
  2433. int ret = 0;
  2434. bool enable_vqmmc = RT_FALSE;
  2435. RT_ASSERT(host != NULL);
  2436. mmc = host->mmc;
  2437. /*
  2438. * If there are external regulators, get them. Note this must be done
  2439. * early before resetting the host and reading the capabilities so that
  2440. * the host can take the appropriate action if regulators are not
  2441. * available.
  2442. */
  2443. if (!mmc->supply.vqmmc)
  2444. {
  2445. if (ret)
  2446. return ret;
  2447. enable_vqmmc = RT_TRUE;
  2448. }
  2449. LOG_D("Version: 0x%08x | Present: 0x%08x\n",
  2450. sdhci_readw(host, SDHCI_HOST_VERSION),
  2451. sdhci_readl(host, SDHCI_PRESENT_STATE));
  2452. LOG_D("Caps: 0x%08x | Caps_1: 0x%08x\n",
  2453. sdhci_readl(host, SDHCI_CAPABILITIES),
  2454. sdhci_readl(host, SDHCI_CAPABILITIES_1));
  2455. sdhci_read_caps(host);
  2456. override_timeout_clk = host->timeout_clk;
  2457. if (host->version > SDHCI_SPEC_420)
  2458. {
  2459. rt_kprintf("%s: Unknown controller version (%d). You may experience problems.\n",
  2460. mmc_hostname(mmc), host->version);
  2461. }
  2462. if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
  2463. host->flags |= SDHCI_USE_SDMA;
  2464. else if (!(host->caps & SDHCI_CAN_DO_SDMA))
  2465. LOG_D("Controller doesn't have SDMA capability\n");
  2466. else
  2467. host->flags |= SDHCI_USE_SDMA;
  2468. if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && (host->flags & SDHCI_USE_SDMA))
  2469. {
  2470. LOG_D("Disabling DMA as it is marked broken\n");
  2471. host->flags &= ~SDHCI_USE_SDMA;
  2472. }
  2473. if (sdhci_can_64bit_dma(host))
  2474. host->flags |= SDHCI_USE_64_BIT_DMA;
  2475. if (host->flags & SDHCI_USE_SDMA)
  2476. {
  2477. if (host->ops->set_dma_mask)
  2478. ret = host->ops->set_dma_mask(host);
  2479. if (!ret && host->ops->enable_dma)
  2480. ret = host->ops->enable_dma(host);
  2481. if (ret)
  2482. {
  2483. rt_kprintf("%s: No suitable DMA available - falling back to PIO\n",
  2484. mmc_hostname(mmc));
  2485. host->flags &= ~SDHCI_USE_SDMA;
  2486. ret = 0;
  2487. }
  2488. }
  2489. /* SDMA does not support 64-bit DMA if v4 mode not set */
  2490. if ((host->flags & SDHCI_USE_64_BIT_DMA) && !host->v4_mode)
  2491. host->flags &= ~SDHCI_USE_SDMA;
  2492. /*
  2493. * If we use DMA, then it's up to the caller to set the DMA
  2494. * mask, but PIO does not need the hw shim so we set a new
  2495. * mask here in that case.
  2496. */
  2497. if (!(host->flags & SDHCI_USE_SDMA))
  2498. {
  2499. host->dma_mask = DMA_BIT_MASK(64);
  2500. }
  2501. if (host->version >= SDHCI_SPEC_300)
  2502. host->max_clk = FIELD_GET(SDHCI_CLOCK_V3_BASE_MASK, host->caps);
  2503. else
  2504. host->max_clk = FIELD_GET(SDHCI_CLOCK_BASE_MASK, host->caps);
  2505. host->max_clk *= 1000000;
  2506. if (host->max_clk == 0 || host->quirks & SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN)
  2507. {
  2508. if (!host->ops->get_max_clock)
  2509. {
  2510. rt_kprintf("%s: Hardware doesn't specify base clock frequency. %p \n",
  2511. mmc_hostname(mmc), host->ops->get_max_clock);
  2512. ret = -ENODEV;
  2513. goto undma;
  2514. }
  2515. host->max_clk = host->ops->get_max_clock(host);
  2516. }
  2517. /*
  2518. * In case of Host Controller v3.00, find out whether clock
  2519. * multiplier is supported.
  2520. */
  2521. host->clk_mul = FIELD_GET(SDHCI_CLOCK_MUL_MASK, host->caps1);
  2522. /*
  2523. * In case the value in Clock Multiplier is 0, then programmable
  2524. * clock mode is not supported, otherwise the actual clock
  2525. * multiplier is one more than the value of Clock Multiplier
  2526. * in the Capabilities Register.
  2527. */
  2528. if (host->clk_mul)
  2529. host->clk_mul += 1;
  2530. /*
  2531. * Set host parameters.
  2532. */
  2533. max_clk = host->max_clk;
  2534. if (host->ops->get_min_clock)
  2535. mmc->f_min = host->ops->get_min_clock(host);
  2536. else if (host->version >= SDHCI_SPEC_300)
  2537. {
  2538. if (host->clk_mul)
  2539. max_clk = host->max_clk * host->clk_mul;
  2540. /*
  2541. * Divided Clock Mode minimum clock rate is always less than
  2542. * Programmable Clock Mode minimum clock rate.
  2543. */
  2544. mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
  2545. }
  2546. else
  2547. mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
  2548. if (!mmc->f_max || mmc->f_max > max_clk)
  2549. mmc->f_max = max_clk;
  2550. if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK))
  2551. {
  2552. host->timeout_clk = FIELD_GET(SDHCI_TIMEOUT_CLK_MASK, host->caps);
  2553. if (host->caps & SDHCI_TIMEOUT_CLK_UNIT)
  2554. host->timeout_clk *= 1000;
  2555. if (host->timeout_clk == 0)
  2556. {
  2557. if (!host->ops->get_timeout_clock)
  2558. {
  2559. rt_kprintf("%s: Hardware doesn't specify timeout clock frequency.\n",
  2560. mmc_hostname(mmc));
  2561. ret = -ENODEV;
  2562. goto undma;
  2563. }
  2564. host->timeout_clk =
  2565. DIV_ROUND_UP(host->ops->get_timeout_clock(host),
  2566. 1000);
  2567. }
  2568. if (override_timeout_clk)
  2569. host->timeout_clk = override_timeout_clk;
  2570. mmc->max_busy_timeout = host->ops->get_max_timeout_count ? host->ops->get_max_timeout_count(host) : 1 << 27;
  2571. mmc->max_busy_timeout /= host->timeout_clk;
  2572. }
  2573. if (host->quirks2 & SDHCI_QUIRK2_DISABLE_HW_TIMEOUT && !host->ops->get_max_timeout_count)
  2574. mmc->max_busy_timeout = 0;
  2575. mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_CMD23;
  2576. mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
  2577. if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
  2578. host->flags |= SDHCI_AUTO_CMD12;
  2579. /*
  2580. * For v3 mode, Auto-CMD23 stuff only works in ADMA or PIO.
  2581. * For v4 mode, SDMA may use Auto-CMD23 as well.
  2582. */
  2583. if ((host->version >= SDHCI_SPEC_300) && (!(host->flags & SDHCI_USE_SDMA) || host->v4_mode) && !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN))
  2584. {
  2585. host->flags |= SDHCI_AUTO_CMD23;
  2586. LOG_D("Auto-CMD23 available\n");
  2587. }
  2588. else
  2589. {
  2590. LOG_D("Auto-CMD23 unavailable\n");
  2591. }
  2592. /*
  2593. * A controller may support 8-bit width, but the board itself
  2594. * might not have the pins brought out. Boards that support
  2595. * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
  2596. * their platform code before calling sdhci_add_host(), and we
  2597. * won't assume 8-bit width for hosts without that CAP.
  2598. */
  2599. if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
  2600. mmc->caps |= MMC_CAP_4_BIT_DATA;
  2601. if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
  2602. mmc->caps &= ~MMC_CAP_CMD23;
  2603. if (host->caps & SDHCI_CAN_DO_HISPD)
  2604. mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
  2605. if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && mmc_card_is_removable(mmc) && mmc_gpio_get_cd(mmc) < 0)
  2606. mmc->caps |= MMC_CAP_NEEDS_POLL;
  2607. if (mmc->supply.vqmmc)
  2608. {
  2609. if (enable_vqmmc)
  2610. {
  2611. host->sdhci_core_to_disable_vqmmc = !ret;
  2612. }
  2613. /* If vqmmc provides no 1.8V signalling, then there's no UHS */
  2614. if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
  2615. 1950000))
  2616. host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
  2617. /* In eMMC case vqmmc might be a fixed 1.8V regulator */
  2618. if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000,
  2619. 3600000))
  2620. host->flags &= ~SDHCI_SIGNALING_330;
  2621. if (ret)
  2622. {
  2623. rt_kprintf("%s: Failed to enable vqmmc regulator: %d\n",
  2624. mmc_hostname(mmc), ret);
  2625. mmc->supply.vqmmc = (void *)-EINVAL;
  2626. }
  2627. }
  2628. if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
  2629. {
  2630. host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
  2631. /*
  2632. * The SDHCI controller in a SoC might support HS200/HS400
  2633. * (indicated using mmc-hs200-1_8v/mmc-hs400-1_8v dt property),
  2634. * but if the board is modeled such that the IO lines are not
  2635. * connected to 1.8v then HS200/HS400 cannot be supported.
  2636. * Disable HS200/HS400 if the board does not have 1.8v connected
  2637. * to the IO lines. (Applicable for other modes in 1.8v)
  2638. */
  2639. mmc->caps2 &= ~(MMC_CAP2_HSX00_1_8V | MMC_CAP2_HS400_ES);
  2640. mmc->caps &= ~(MMC_CAP_1_8V_DDR | MMC_CAP_UHS);
  2641. }
  2642. /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
  2643. if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50))
  2644. mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
  2645. /* SDR104 supports also implies SDR50 support */
  2646. if (host->caps1 & SDHCI_SUPPORT_SDR104)
  2647. {
  2648. mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
  2649. /* SD3.0: SDR104 is supported so (for eMMC) the caps2
  2650. * field can be promoted to support HS200.
  2651. */
  2652. if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
  2653. mmc->caps2 |= MMC_CAP2_HS200;
  2654. }
  2655. else if (host->caps1 & SDHCI_SUPPORT_SDR50)
  2656. {
  2657. mmc->caps |= MMC_CAP_UHS_SDR50;
  2658. }
  2659. if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && (host->caps1 & SDHCI_SUPPORT_HS400))
  2660. mmc->caps2 |= MMC_CAP2_HS400;
  2661. if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && (!mmc->supply.vqmmc || !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, 1300000)))
  2662. mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
  2663. if ((host->caps1 & SDHCI_SUPPORT_DDR50) && !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
  2664. mmc->caps |= MMC_CAP_UHS_DDR50;
  2665. /* Does the host need tuning for SDR50? */
  2666. if (host->caps1 & SDHCI_USE_SDR50_TUNING)
  2667. host->flags |= SDHCI_SDR50_NEEDS_TUNING;
  2668. /* Driver Type(s) (A, C, D) supported by the host */
  2669. if (host->caps1 & SDHCI_DRIVER_TYPE_A)
  2670. mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
  2671. if (host->caps1 & SDHCI_DRIVER_TYPE_C)
  2672. mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
  2673. if (host->caps1 & SDHCI_DRIVER_TYPE_D)
  2674. mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
  2675. /* Initial value for re-tuning timer count */
  2676. host->tuning_count = FIELD_GET(SDHCI_RETUNING_TIMER_COUNT_MASK,
  2677. host->caps1);
  2678. /*
  2679. * In case Re-tuning Timer is not disabled, the actual value of
  2680. * re-tuning timer will be 2 ^ (n - 1).
  2681. */
  2682. if (host->tuning_count)
  2683. host->tuning_count = 1 << (host->tuning_count - 1);
  2684. /* Re-tuning mode supported by the Host Controller */
  2685. host->tuning_mode = FIELD_GET(SDHCI_RETUNING_MODE_MASK, host->caps1);
  2686. ocr_avail = 0;
  2687. /*
  2688. * According to SD Host Controller spec v3.00, if the Host System
  2689. * can afford more than 150mA, Host Driver should set XPC to 1. Also
  2690. * the value is meaningful only if Voltage Support in the Capabilities
  2691. * register is set. The actual current value is 4 times the register
  2692. * value.
  2693. */
  2694. max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
  2695. if (!max_current_caps && mmc->supply.vmmc)
  2696. {
  2697. int curr = regulator_get_current_limit(mmc->supply.vmmc);
  2698. if (curr > 0)
  2699. {
  2700. /* convert to SDHCI_MAX_CURRENT format */
  2701. curr = curr / 1000; /* convert to mA */
  2702. curr = curr / SDHCI_MAX_CURRENT_MULTIPLIER;
  2703. curr = min_t(rt_uint32_t, curr, SDHCI_MAX_CURRENT_LIMIT);
  2704. max_current_caps =
  2705. FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, curr) | FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, curr) | FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, curr);
  2706. }
  2707. }
  2708. if (host->caps & SDHCI_CAN_VDD_330)
  2709. {
  2710. ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
  2711. mmc->max_current_330 = FIELD_GET(SDHCI_MAX_CURRENT_330_MASK,
  2712. max_current_caps)
  2713. * SDHCI_MAX_CURRENT_MULTIPLIER;
  2714. }
  2715. if (host->caps & SDHCI_CAN_VDD_300)
  2716. {
  2717. ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
  2718. mmc->max_current_300 = FIELD_GET(SDHCI_MAX_CURRENT_300_MASK,
  2719. max_current_caps)
  2720. * SDHCI_MAX_CURRENT_MULTIPLIER;
  2721. }
  2722. if (host->caps & SDHCI_CAN_VDD_180)
  2723. {
  2724. ocr_avail |= MMC_VDD_165_195;
  2725. mmc->max_current_180 = FIELD_GET(SDHCI_MAX_CURRENT_180_MASK,
  2726. max_current_caps)
  2727. * SDHCI_MAX_CURRENT_MULTIPLIER;
  2728. }
  2729. /* If OCR set by host, use it instead. */
  2730. if (host->ocr_mask)
  2731. ocr_avail = host->ocr_mask;
  2732. /* If OCR set by external regulators, give it highest prio. */
  2733. if (mmc->ocr_avail)
  2734. ocr_avail = mmc->ocr_avail;
  2735. mmc->ocr_avail = ocr_avail;
  2736. mmc->ocr_avail_sdio = ocr_avail;
  2737. if (host->ocr_avail_sdio)
  2738. mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
  2739. mmc->ocr_avail_sd = ocr_avail;
  2740. if (host->ocr_avail_sd)
  2741. mmc->ocr_avail_sd &= host->ocr_avail_sd;
  2742. else /* normal SD controllers don't support 1.8V */
  2743. mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
  2744. mmc->ocr_avail_mmc = ocr_avail;
  2745. if (host->ocr_avail_mmc)
  2746. mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
  2747. if (mmc->ocr_avail == 0)
  2748. {
  2749. rt_kprintf("%s: Hardware doesn't report any support voltages.\n",
  2750. mmc_hostname(mmc));
  2751. ret = -ENODEV;
  2752. goto unreg;
  2753. }
  2754. if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V)))
  2755. host->flags |= SDHCI_SIGNALING_180;
  2756. if (mmc->caps2 & MMC_CAP2_HSX00_1_2V)
  2757. host->flags |= SDHCI_SIGNALING_120;
  2758. rt_spin_lock_init(&host->lock);
  2759. /*
  2760. * Maximum number of sectors in one transfer. Limited by SDMA boundary
  2761. * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
  2762. * is less anyway.
  2763. */
  2764. mmc->max_req_size = 524288;
  2765. /*
  2766. * Maximum number of segments. Depends on if the hardware
  2767. * can do scatter/gather or not.
  2768. */
  2769. if (host->flags & SDHCI_USE_SDMA)
  2770. {
  2771. mmc->max_segs = 1;
  2772. }
  2773. else
  2774. { /* PIO */
  2775. mmc->max_segs = SDHCI_MAX_SEGS;
  2776. }
  2777. /*
  2778. * Maximum segment size. Could be one segment with the maximum number
  2779. * of bytes. When doing hardware scatter/gather, each entry cannot
  2780. * be larger than 64 KiB though.
  2781. */
  2782. mmc->max_seg_size = mmc->max_req_size;
  2783. /*
  2784. * Maximum block size. This varies from controller to controller and
  2785. * is specified in the capabilities register.
  2786. */
  2787. if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048)
  2788. {
  2789. mmc->max_blk_size = 2;
  2790. }
  2791. else
  2792. {
  2793. mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  2794. if (mmc->max_blk_size >= 3)
  2795. {
  2796. rt_kprintf("%s: Invalid maximum block size, assuming 512 bytes\n",
  2797. mmc_hostname(mmc));
  2798. mmc->max_blk_size = 0;
  2799. }
  2800. }
  2801. mmc->max_blk_size = 512 << mmc->max_blk_size;
  2802. /*
  2803. * Maximum block count.
  2804. */
  2805. mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
  2806. return 0;
  2807. unreg:
  2808. undma:
  2809. return ret;
  2810. }
  2811. static void sdhci_init(struct sdhci_host *host, int soft)
  2812. {
  2813. struct mmc_host *mmc = host->mmc;
  2814. rt_base_t flags;
  2815. if (soft)
  2816. {
  2817. sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
  2818. }
  2819. else
  2820. {
  2821. sdhci_do_reset(host, SDHCI_RESET_ALL);
  2822. }
  2823. if (host->v4_mode)
  2824. {
  2825. sdhci_do_enable_v4_mode(host);
  2826. }
  2827. flags = rt_spin_lock_irqsave(&host->lock);
  2828. sdhci_set_default_irqs(host);
  2829. rt_spin_unlock_irqrestore(&host->lock, flags);
  2830. host->cqe_on = RT_FALSE;
  2831. if (soft)
  2832. {
  2833. /* force clock reconfiguration */
  2834. host->clock = 0;
  2835. host->reinit_uhs = RT_TRUE;
  2836. mmc->ops->set_ios(mmc, &mmc->ios);
  2837. }
  2838. }
  2839. static void sdhci_reinit(struct sdhci_host *host)
  2840. {
  2841. rt_uint32_t cd = host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
  2842. sdhci_init(host, 0);
  2843. sdhci_enable_card_detection(host);
  2844. /*
  2845. * A change to the card detect bits indicates a change in present state,
  2846. * refer sdhci_set_card_detection(). A card detect interrupt might have
  2847. * been missed while the host controller was being reset, so trigger a
  2848. * rescan to check.
  2849. */
  2850. if (cd != (host->ier & (SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT)))
  2851. mmc_detect_change(host->mmc, rt_tick_from_millisecond(200));
  2852. }
  2853. int __sdhci_add_host(struct sdhci_host *host)
  2854. {
  2855. struct mmc_host *mmc = host->mmc;
  2856. int ret;
  2857. if ((mmc->caps2 & MMC_CAP2_CQE) && (host->quirks & SDHCI_QUIRK_BROKEN_CQE))
  2858. {
  2859. mmc->caps2 &= ~MMC_CAP2_CQE;
  2860. }
  2861. host->complete_wq = rt_workqueue_create("sdhci", 4096, 20);
  2862. if (!host->complete_wq)
  2863. return -ENOMEM;
  2864. rt_work_init(&host->complete_work, sdhci_complete_work, host);
  2865. rt_timer_init(&host->timer, "sdhci_timer", sdhci_timeout_timer, host, 0, RT_TIMER_FLAG_SOFT_TIMER);
  2866. rt_timer_init(&host->data_timer, "sdhci_data_timer", sdhci_timeout_data_timer, host, 0, RT_TIMER_FLAG_SOFT_TIMER);
  2867. rt_wqueue_init(&host->buf_ready_int);
  2868. sdhci_init(host, 0);
  2869. host->irq_wq = rt_workqueue_create("sdhci_irq", 8192, 1);
  2870. rt_work_init(&host->irq_work, sdhci_thread_irq, host);
  2871. rt_hw_interrupt_install(host->irq, sdhci_irq, host, mmc_hostname(mmc));
  2872. rt_pic_irq_unmask(host->irq);
  2873. ret = mmc_add_host(mmc);
  2874. if (ret)
  2875. goto unirq;
  2876. rt_kprintf("%s: SDHCI controller on %s [%s] using %s\n",
  2877. mmc_hostname(mmc), host->hw_name, mmc_dev(mmc)->parent.name,
  2878. (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
  2879. sdhci_enable_card_detection(host);
  2880. return 0;
  2881. unirq:
  2882. sdhci_reset_for_all(host);
  2883. sdhci_writel(host, 0, SDHCI_INT_ENABLE);
  2884. sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
  2885. return ret;
  2886. }
  2887. int sdhci_add_host(struct sdhci_host *host)
  2888. {
  2889. int ret;
  2890. ret = sdhci_setup_host(host);
  2891. if (ret)
  2892. return ret;
  2893. ret = __sdhci_add_host(host);
  2894. if (ret)
  2895. goto cleanup;
  2896. return 0;
  2897. cleanup:
  2898. sdhci_cleanup_host(host);
  2899. return ret;
  2900. }
  2901. void sdhci_set_ios(struct mmc_host *mmc, struct rt_mmcsd_io_cfg *ios)
  2902. {
  2903. struct sdhci_host *host = mmc_priv(mmc);
  2904. rt_bool_t reinit_uhs = host->reinit_uhs;
  2905. rt_bool_t turning_on_clk = RT_FALSE;
  2906. rt_uint8_t ctrl;
  2907. host->reinit_uhs = RT_FALSE;
  2908. if (ios->power_mode == MMC_POWER_UNDEFINED)
  2909. return;
  2910. if (host->flags & SDHCI_DEVICE_DEAD)
  2911. {
  2912. if (mmc->supply.vmmc && ios->power_mode == MMC_POWER_OFF)
  2913. mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
  2914. return;
  2915. }
  2916. /*
  2917. * Reset the chip on each power off.
  2918. * Should clear out any weird states.
  2919. */
  2920. if (ios->power_mode == MMC_POWER_OFF)
  2921. {
  2922. sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
  2923. sdhci_reinit(host);
  2924. }
  2925. if (host->version >= SDHCI_SPEC_300 && (ios->power_mode == MMC_POWER_UP) && !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
  2926. sdhci_enable_preset_value(host, RT_FALSE);
  2927. if (!ios->clock || ios->clock != host->clock)
  2928. {
  2929. turning_on_clk = ios->clock && !host->clock;
  2930. host->ops->set_clock(host, ios->clock);
  2931. host->clock = ios->clock;
  2932. if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && host->clock)
  2933. {
  2934. host->timeout_clk = mmc->actual_clock ? mmc->actual_clock / 1000 : host->clock / 1000;
  2935. mmc->max_busy_timeout =
  2936. host->ops->get_max_timeout_count ? host->ops->get_max_timeout_count(host) : 1 << 27;
  2937. mmc->max_busy_timeout /= host->timeout_clk;
  2938. }
  2939. }
  2940. if (host->ops->set_power)
  2941. host->ops->set_power(host, ios->power_mode, ios->vdd);
  2942. else
  2943. sdhci_set_power(host, ios->power_mode, ios->vdd);
  2944. if (host->ops->platform_send_init_74_clocks)
  2945. host->ops->platform_send_init_74_clocks(host, ios->power_mode);
  2946. host->ops->set_bus_width(host, ios->bus_width);
  2947. /*
  2948. * Special case to avoid multiple clock changes during voltage
  2949. * switching.
  2950. */
  2951. if (!reinit_uhs && turning_on_clk && host->timing == ios->timing && host->version >= SDHCI_SPEC_300 && !sdhci_presetable_values_change(host, ios))
  2952. return;
  2953. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  2954. if (!(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
  2955. {
  2956. if (ios->timing == MMC_TIMING_SD_HS || ios->timing == MMC_TIMING_MMC_HS || ios->timing == MMC_TIMING_MMC_HS400 || ios->timing == MMC_TIMING_MMC_HS200 || ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_SDR50 || ios->timing == MMC_TIMING_UHS_SDR104 || ios->timing == MMC_TIMING_UHS_DDR50 || ios->timing == MMC_TIMING_UHS_SDR25)
  2957. ctrl |= SDHCI_CTRL_HISPD;
  2958. else
  2959. ctrl &= ~SDHCI_CTRL_HISPD;
  2960. }
  2961. if (host->version >= SDHCI_SPEC_300)
  2962. {
  2963. rt_uint16_t clk, ctrl_2;
  2964. /*
  2965. * According to SDHCI Spec v3.00, if the Preset Value
  2966. * Enable in the Host Control 2 register is set, we
  2967. * need to reset SD Clock Enable before changing High
  2968. * Speed Enable to avoid generating clock glitches.
  2969. */
  2970. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  2971. if (clk & SDHCI_CLOCK_CARD_EN)
  2972. {
  2973. clk &= ~SDHCI_CLOCK_CARD_EN;
  2974. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  2975. }
  2976. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  2977. if (!host->preset_enabled)
  2978. {
  2979. /*
  2980. * We only need to set Driver Strength if the
  2981. * preset value enable is not set.
  2982. */
  2983. ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  2984. ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
  2985. if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
  2986. ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
  2987. else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
  2988. ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
  2989. else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
  2990. ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
  2991. else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
  2992. ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
  2993. else
  2994. {
  2995. LOG_D("%s: invalid driver type, default to driver type B\n",
  2996. mmc_hostname(mmc));
  2997. ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
  2998. }
  2999. sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
  3000. host->drv_type = ios->drv_type;
  3001. }
  3002. host->ops->set_uhs_signaling(host, ios->timing);
  3003. host->timing = ios->timing;
  3004. if (sdhci_preset_needed(host, ios->timing))
  3005. {
  3006. rt_uint16_t preset;
  3007. sdhci_enable_preset_value(host, RT_TRUE);
  3008. preset = sdhci_get_preset_value(host);
  3009. ios->drv_type = FIELD_GET(SDHCI_PRESET_DRV_MASK,
  3010. preset);
  3011. host->drv_type = ios->drv_type;
  3012. }
  3013. /* Re-enable SD Clock */
  3014. host->ops->set_clock(host, host->clock);
  3015. }
  3016. else
  3017. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  3018. }
  3019. void sdhci_free_host(struct sdhci_host *host)
  3020. {
  3021. sdhci_cleanup_host(host);
  3022. rt_free(host);
  3023. }