pic-gicv2.c 15 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2013-07-20 Bernard first version
  9. * 2014-04-03 Grissiom many enhancements
  10. * 2018-11-22 Jesven add rt_hw_ipi_send()
  11. * add rt_hw_ipi_handler_install()
  12. * 2022-08-24 GuEe-GUI add pic support
  13. * 2022-11-07 GuEe-GUI add v2m support
  14. */
  15. #include <rthw.h>
  16. #include <rtthread.h>
  17. #include <rtdevice.h>
  18. #define DBG_TAG "pic.gicv2"
  19. #define DBG_LVL DBG_INFO
  20. #include <rtdbg.h>
  21. #include <cpuport.h>
  22. #include <ioremap.h>
  23. #include "pic-gicv2.h"
  24. #include "pic-gic-common.h"
  25. #define GIC_CPU_IMAX 8
  26. #define raw_to_gicv2(raw) rt_container_of(raw, struct gicv2, parent)
  27. static rt_bool_t needs_rmw_access = RT_FALSE;
  28. static int _gicv2_nr = 0, _init_cpu_id = 0;
  29. static struct gicv2 _gicv2_list[RT_PIC_ARM_GIC_MAX_NR] = {};
  30. static rt_bool_t _gicv2_eoi_mode_ns = RT_FALSE;
  31. static rt_uint8_t _gicv2_cpumask_map[GIC_CPU_IMAX] =
  32. {
  33. [0 ... GIC_CPU_IMAX - 1] = 0xff,
  34. };
  35. static rt_uint8_t gicv2_cpumask_map(struct gicv2 *gic)
  36. {
  37. rt_uint32_t mask, i;
  38. for (i = mask = 0; i < 32; i += 4)
  39. {
  40. mask = HWREG32(gic->dist_base + GIC_DIST_TARGET + i);
  41. mask |= mask >> 16;
  42. mask |= mask >> 8;
  43. if (mask)
  44. {
  45. break;
  46. }
  47. }
  48. return mask;
  49. }
  50. static void gicv2_dist_init(struct gicv2 *gic)
  51. {
  52. void *base = gic->dist_base;
  53. rt_uint32_t i;
  54. rt_uint32_t cpumask = gicv2_cpumask_map(gic);
  55. _init_cpu_id = rt_hw_cpu_id();
  56. gic->max_irq = HWREG32(base + GIC_DIST_TYPE) & 0x1f;
  57. gic->max_irq = (gic->max_irq + 1) * 32;
  58. /*
  59. * The GIC only supports up to 1020 interrupt sources.
  60. * Limit this to either the architected maximum, or the
  61. * platform maximum.
  62. */
  63. if (gic->max_irq > 1020)
  64. {
  65. gic->max_irq = 1020;
  66. }
  67. LOG_D("Max irq = %d", gic->max_irq);
  68. if (gic->skip_init)
  69. {
  70. return;
  71. }
  72. HWREG32(base + GIC_DIST_CTRL) = GICD_DISABLE;
  73. /* Set all global (unused) interrupts to this CPU only. */
  74. cpumask |= cpumask << 8;
  75. cpumask |= cpumask << 16;
  76. for (i = 32; i < gic->max_irq; i += 4)
  77. {
  78. HWREG32(base + GIC_DIST_TARGET + i * 4 / 4) = cpumask;
  79. }
  80. gic_common_dist_config(base, gic->max_irq, RT_NULL, RT_NULL);
  81. HWREG32(base + GIC_DIST_CTRL) = GICD_ENABLE;
  82. }
  83. static void gicv2_cpu_init(struct gicv2 *gic)
  84. {
  85. rt_uint32_t cpumask;
  86. void *base = gic->cpu_base;
  87. rt_uint32_t config = GICC_ENABLE;
  88. int cpu_id = rt_hw_cpu_id();
  89. cpumask = gicv2_cpumask_map(gic);
  90. _gicv2_cpumask_map[cpu_id] = cpumask;
  91. /*
  92. * Clear our mask from the other map entries in case they're
  93. * still undefined.
  94. */
  95. for (int i = 0; i < RT_ARRAY_SIZE(_gicv2_cpumask_map); ++i)
  96. {
  97. if (i != cpu_id)
  98. {
  99. _gicv2_cpumask_map[i] &= ~cpumask;
  100. }
  101. }
  102. gic_common_cpu_config(gic->dist_base, 32, RT_NULL, RT_NULL);
  103. HWREG32(base + GIC_CPU_PRIMASK) = GICC_INT_PRI_THRESHOLD;
  104. HWREG32(base + GIC_CPU_BINPOINT) = 0x7;
  105. #ifdef ARCH_SUPPORT_HYP
  106. _gicv2_eoi_mode_ns = RT_TRUE;
  107. #else
  108. _gicv2_eoi_mode_ns = !!rt_ofw_bootargs_select("pic.gicv2_eoimode", 0);
  109. #endif
  110. if (_gicv2_eoi_mode_ns)
  111. {
  112. config |= GIC_CPU_CTRL_EOI_MODE_NS;
  113. }
  114. HWREG32(base + GIC_CPU_CTRL) = config;
  115. }
  116. static rt_err_t gicv2_irq_init(struct rt_pic *pic)
  117. {
  118. gicv2_cpu_init(rt_container_of(pic, struct gicv2, parent));
  119. return RT_EOK;
  120. }
  121. static void gicv2_irq_ack(struct rt_pic_irq *pirq)
  122. {
  123. int hwirq = pirq->hwirq;
  124. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  125. if (!_gicv2_eoi_mode_ns)
  126. {
  127. HWREG32(gic->dist_base + GIC_DIST_PENDING_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
  128. }
  129. HWREG32(gic->cpu_base + GIC_CPU_EOI) = hwirq;
  130. }
  131. static void gicv2_irq_mask(struct rt_pic_irq *pirq)
  132. {
  133. int hwirq = pirq->hwirq;
  134. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  135. HWREG32(gic->dist_base + GIC_DIST_ENABLE_CLEAR + hwirq / 32 * 4) = 1U << (hwirq % 32);
  136. }
  137. static void gicv2_irq_unmask(struct rt_pic_irq *pirq)
  138. {
  139. int hwirq = pirq->hwirq;
  140. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  141. HWREG32(gic->dist_base + GIC_DIST_ENABLE_SET + hwirq / 32 * 4) = 1U << (hwirq % 32);
  142. }
  143. static void gicv2_irq_eoi(struct rt_pic_irq *pirq)
  144. {
  145. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  146. if (_gicv2_eoi_mode_ns)
  147. {
  148. HWREG32(gic->cpu_base + GIC_CPU_DIR) = pirq->hwirq;
  149. }
  150. }
  151. static rt_err_t gicv2_irq_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
  152. {
  153. rt_uint32_t mask;
  154. int hwirq = pirq->hwirq;
  155. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  156. mask = HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4);
  157. mask &= ~(0xffU << ((hwirq % 4) * 8));
  158. mask |= ((priority & 0xffU) << ((hwirq % 4) * 8));
  159. HWREG32(gic->dist_base + GIC_DIST_PRI + hwirq / 4 * 4) = mask;
  160. return RT_EOK;
  161. }
  162. static rt_err_t gicv2_irq_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
  163. {
  164. int hwirq = pirq->hwirq;
  165. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  166. rt_uint32_t target_list = ((rt_uint8_t *)affinity)[gic - &_gicv2_list[0]];
  167. rt_uint8_t valb = _gicv2_cpumask_map[__rt_ffs(target_list) - 1];
  168. void *io_addr = gic->dist_base + GIC_DIST_TARGET + hwirq;
  169. if (valb == 0xfe)
  170. {
  171. return -RT_EIO;
  172. }
  173. if (needs_rmw_access)
  174. {
  175. /* RMW write byte */
  176. rt_uint32_t val;
  177. rt_ubase_t level;
  178. rt_ubase_t offset = (rt_ubase_t)io_addr & 3UL, shift = offset * 8;
  179. static RT_DEFINE_SPINLOCK(rmw_lock);
  180. level = rt_spin_lock_irqsave(&rmw_lock);
  181. io_addr -= offset;
  182. val = HWREG32(io_addr);
  183. val &= ~RT_GENMASK(shift + 7, shift);
  184. val |= valb << shift;
  185. HWREG32(io_addr) = val;
  186. rt_spin_unlock_irqrestore(&rmw_lock, level);
  187. }
  188. else
  189. {
  190. HWREG8(io_addr) = valb;
  191. }
  192. return RT_EOK;
  193. }
  194. static rt_err_t gicv2_irq_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
  195. {
  196. rt_err_t err = RT_EOK;
  197. int hwirq = pirq->hwirq;
  198. struct gicv2 *gic = raw_to_gicv2(pirq->pic);
  199. if (hwirq >= GIC_SGI_NR)
  200. {
  201. err = gic_common_configure_irq(gic->dist_base + GIC_DIST_CONFIG, pirq->hwirq, mode, RT_NULL, RT_NULL);
  202. }
  203. else
  204. {
  205. err = -RT_ENOSYS;
  206. }
  207. return err;
  208. }
  209. static void gicv2_irq_send_ipi(struct rt_pic_irq *pirq, rt_bitmap_t *cpumask)
  210. {
  211. struct gicv2 *gic;
  212. int sgi = pirq->hwirq;
  213. rt_uint8_t *target_list = (rt_uint8_t *)cpumask;
  214. for (int i = 0; i < _gicv2_nr; ++i)
  215. {
  216. if (*target_list)
  217. {
  218. gic = &_gicv2_list[i];
  219. HWREG32(gic->dist_base + GIC_DIST_SOFTINT) = ((*target_list & 0xffU) << 16) | (sgi & 0xf);
  220. rt_hw_dsb();
  221. }
  222. ++target_list;
  223. }
  224. }
  225. static rt_err_t gicv2_irq_set_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
  226. {
  227. rt_err_t err = RT_EOK;
  228. rt_uint32_t offset = 0;
  229. struct gicv2 *gic = raw_to_gicv2(pic);
  230. switch (type)
  231. {
  232. case RT_IRQ_STATE_PENDING:
  233. offset = state ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
  234. break;
  235. case RT_IRQ_STATE_ACTIVE:
  236. offset = state ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
  237. break;
  238. case RT_IRQ_STATE_MASKED:
  239. offset = state ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
  240. break;
  241. default:
  242. err = -RT_EINVAL;
  243. break;
  244. }
  245. if (!err)
  246. {
  247. rt_uint32_t mask = 1 << (hwirq % 32);
  248. HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) = mask;
  249. }
  250. return err;
  251. }
  252. static rt_err_t gicv2_irq_get_state(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
  253. {
  254. rt_err_t err = RT_EOK;
  255. rt_uint32_t offset = 0;
  256. struct gicv2 *gic = raw_to_gicv2(pic);
  257. switch (type)
  258. {
  259. case RT_IRQ_STATE_PENDING:
  260. offset = GIC_DIST_PENDING_SET;
  261. break;
  262. case RT_IRQ_STATE_ACTIVE:
  263. offset = GIC_DIST_ACTIVE_SET;
  264. break;
  265. case RT_IRQ_STATE_MASKED:
  266. offset = GIC_DIST_ENABLE_SET;
  267. break;
  268. default:
  269. err = -RT_EINVAL;
  270. break;
  271. }
  272. if (!err)
  273. {
  274. rt_uint32_t mask = 1 << (hwirq % 32);
  275. *out_state = !!(HWREG32(gic->dist_base + offset + (hwirq / 32) * 4) & mask);
  276. }
  277. return err;
  278. }
  279. static int gicv2_irq_map(struct rt_pic *pic, int hwirq, rt_uint32_t mode)
  280. {
  281. int irq, irq_index = hwirq - GIC_SGI_NR;
  282. struct rt_pic_irq *pirq = rt_pic_find_irq(pic, irq_index);
  283. if (pirq && hwirq >= GIC_SGI_NR)
  284. {
  285. pirq->mode = mode;
  286. pirq->priority = GICD_INT_DEF_PRI;
  287. if (hwirq < 32)
  288. {
  289. gic_fill_ppi_affinity(pirq->affinity);
  290. }
  291. else
  292. {
  293. RT_IRQ_AFFINITY_SET(pirq->affinity, _init_cpu_id);
  294. }
  295. irq = rt_pic_config_irq(pic, irq_index, hwirq);
  296. if (irq >= 0 && mode != RT_IRQ_MODE_LEVEL_HIGH)
  297. {
  298. gicv2_irq_set_triger_mode(pirq, mode);
  299. }
  300. }
  301. else
  302. {
  303. irq = -1;
  304. }
  305. return irq;
  306. }
  307. static rt_err_t gicv2_irq_parse(struct rt_pic *pic, struct rt_ofw_cell_args *args, struct rt_pic_irq *out_pirq)
  308. {
  309. rt_err_t err = RT_EOK;
  310. if (args->args_count == 3)
  311. {
  312. out_pirq->mode = args->args[2] & RT_IRQ_MODE_MASK;
  313. switch (args->args[0])
  314. {
  315. case 0:
  316. /* SPI */
  317. out_pirq->hwirq = args->args[1] + 32;
  318. break;
  319. case 1:
  320. /* PPI */
  321. out_pirq->hwirq = args->args[1] + 16;
  322. break;
  323. default:
  324. err = -RT_ENOSYS;
  325. break;
  326. }
  327. }
  328. else
  329. {
  330. err = -RT_EINVAL;
  331. }
  332. return err;
  333. }
  334. const static struct rt_pic_ops gicv2_ops =
  335. {
  336. .name = "GICv2",
  337. .irq_init = gicv2_irq_init,
  338. .irq_ack = gicv2_irq_ack,
  339. .irq_mask = gicv2_irq_mask,
  340. .irq_unmask = gicv2_irq_unmask,
  341. .irq_eoi = gicv2_irq_eoi,
  342. .irq_set_priority = gicv2_irq_set_priority,
  343. .irq_set_affinity = gicv2_irq_set_affinity,
  344. .irq_set_triger_mode = gicv2_irq_set_triger_mode,
  345. .irq_send_ipi = gicv2_irq_send_ipi,
  346. .irq_set_state = gicv2_irq_set_state,
  347. .irq_get_state = gicv2_irq_get_state,
  348. .irq_map = gicv2_irq_map,
  349. .irq_parse = gicv2_irq_parse,
  350. };
  351. static rt_bool_t gicv2_handler(void *data)
  352. {
  353. rt_bool_t res = RT_FALSE;
  354. int hwirq;
  355. struct gicv2 *gic = data;
  356. hwirq = HWREG32(gic->cpu_base + GIC_CPU_INTACK) & 0x3ffUL;
  357. if (!(hwirq >= 1020 && hwirq <= 1023))
  358. {
  359. struct rt_pic_irq *pirq;
  360. if (hwirq < GIC_SGI_NR)
  361. {
  362. rt_hw_rmb();
  363. pirq = rt_pic_find_ipi(&gic->parent, hwirq);
  364. }
  365. else
  366. {
  367. pirq = rt_pic_find_irq(&gic->parent, hwirq - GIC_SGI_NR);
  368. }
  369. gicv2_irq_ack(pirq);
  370. rt_pic_handle_isr(pirq);
  371. gicv2_irq_eoi(pirq);
  372. res = RT_TRUE;
  373. }
  374. return res;
  375. }
  376. static rt_err_t gicv2_enable_rmw_access(void *data)
  377. {
  378. if (rt_ofw_machine_is_compatible("renesas,emev2"))
  379. {
  380. needs_rmw_access = RT_TRUE;
  381. return RT_EOK;
  382. }
  383. return -RT_EINVAL;
  384. }
  385. static const struct gic_quirk _gicv2_quirks[] =
  386. {
  387. {
  388. .desc = "GICv2: Broken byte access",
  389. .compatible = "arm,pl390",
  390. .init = gicv2_enable_rmw_access,
  391. },
  392. { /* sentinel */ }
  393. };
  394. static rt_err_t gicv2_iomap_init(struct gicv2 *gic, rt_uint64_t *regs)
  395. {
  396. rt_err_t err = RT_EOK;
  397. int idx;
  398. const char *name[] =
  399. {
  400. "Distributor",
  401. "CPU interfaces",
  402. "Virtual interface control",
  403. "Virtual CPU interface",
  404. };
  405. do {
  406. /* GICD->GICC->GICH->GICV */
  407. gic->dist_size = regs[1];
  408. gic->dist_base = rt_ioremap((void *)regs[0], gic->dist_size);
  409. if (!gic->dist_base)
  410. {
  411. idx = 0;
  412. err = -RT_ERROR;
  413. break;
  414. }
  415. gic->cpu_size = regs[3];
  416. gic->cpu_base = rt_ioremap((void *)regs[2], gic->cpu_size);
  417. if (!gic->cpu_base)
  418. {
  419. idx = 1;
  420. err = -RT_ERROR;
  421. break;
  422. }
  423. /* ArchRev[4:7] */
  424. gic->version = HWREG32(gic->dist_base + GIC_DIST_ICPIDR2) >> 4;
  425. #ifdef ARCH_SUPPORT_HYP
  426. if (gic->version == 1)
  427. {
  428. break;
  429. }
  430. gic->hyp_size = regs[5];
  431. gic->hyp_base = rt_ioremap((void *)regs[4], gic->hyp_size);
  432. if (!gic->hyp_base)
  433. {
  434. idx = 2;
  435. err = -RT_ERROR;
  436. break;
  437. }
  438. gic->vcpu_size = regs[7];
  439. gic->vcpu_base = rt_ioremap((void *)regs[6], gic->vcpu_size);
  440. if (!gic->vcpu_base)
  441. {
  442. idx = 3;
  443. err = -RT_ERROR;
  444. break;
  445. }
  446. #endif /* ARCH_SUPPORT_HYP */
  447. } while (0);
  448. if (err)
  449. {
  450. RT_UNUSED(idx);
  451. RT_UNUSED(name);
  452. LOG_E("gic[%d] %s IO[%p, %p] map fail", _gicv2_nr, name[idx], regs[idx * 2], regs[idx * 2 + 1]);
  453. }
  454. return err;
  455. }
  456. static void gicv2_init(struct gicv2 *gic)
  457. {
  458. gicv2_dist_init(gic);
  459. gic->parent.priv_data = gic;
  460. gic->parent.ops = &gicv2_ops;
  461. rt_pic_linear_irq(&gic->parent, gic->max_irq + 1 - GIC_SGI_NR);
  462. gic_common_sgi_config(gic->dist_base, &gic->parent, _gicv2_nr * GIC_SGI_NR);
  463. rt_pic_add_traps(gicv2_handler, gic);
  464. rt_pic_user_extends(&gic->parent);
  465. }
  466. static void gicv2_init_fail(struct gicv2 *gic)
  467. {
  468. if (gic->dist_base)
  469. {
  470. rt_iounmap(gic->dist_base);
  471. }
  472. if (gic->cpu_base)
  473. {
  474. rt_iounmap(gic->cpu_base);
  475. }
  476. if (gic->hyp_base)
  477. {
  478. rt_iounmap(gic->hyp_base);
  479. }
  480. if (gic->vcpu_base)
  481. {
  482. rt_iounmap(gic->vcpu_base);
  483. }
  484. rt_memset(gic, 0, sizeof(*gic));
  485. }
  486. static rt_err_t gicv2_ofw_init(struct rt_ofw_node *np, const struct rt_ofw_node_id *id)
  487. {
  488. rt_err_t err = RT_EOK;
  489. struct gicv2 *gic = RT_NULL;
  490. do {
  491. rt_uint64_t regs[8];
  492. if (_gicv2_nr >= RT_PIC_ARM_GIC_MAX_NR)
  493. {
  494. LOG_W("GICv2/v1 table is full");
  495. err = -RT_EFULL;
  496. break;
  497. }
  498. gic = &_gicv2_list[_gicv2_nr];
  499. rt_ofw_get_address_array(np, RT_ARRAY_SIZE(regs), regs);
  500. if ((err = gicv2_iomap_init(gic, regs)))
  501. {
  502. break;
  503. }
  504. if (gic->version != 1 && gic->version != 2)
  505. {
  506. LOG_E("Version = %d is not support", gic->version);
  507. err = -RT_EINVAL;
  508. break;
  509. }
  510. gic->skip_init = rt_ofw_prop_read_bool(np, "skip-init");
  511. gic_common_init_quirk_ofw(np, _gicv2_quirks, gic);
  512. gicv2_init(gic);
  513. rt_ofw_data(np) = &gic->parent;
  514. if (gic->version == 2)
  515. {
  516. #ifdef RT_PIC_ARM_GIC_V2M
  517. gicv2m_ofw_probe(np, id);
  518. #endif
  519. }
  520. ++_gicv2_nr;
  521. } while (0);
  522. if (err && gic)
  523. {
  524. gicv2_init_fail(gic);
  525. }
  526. return err;
  527. }
  528. static const struct rt_ofw_node_id gicv2_ofw_ids[] =
  529. {
  530. { .compatible = "arm,gic-400" },
  531. { .compatible = "arm,arm11mp-gic" },
  532. { .compatible = "arm,arm1176jzf-devchip-gic" },
  533. { .compatible = "arm,cortex-a15-gic" },
  534. { .compatible = "arm,cortex-a9-gic" },
  535. { .compatible = "arm,cortex-a7-gic" },
  536. { .compatible = "qcom,msm-8660-qgic" },
  537. { .compatible = "qcom,msm-qgic2" },
  538. { .compatible = "arm,pl390" },
  539. { /* sentinel */ }
  540. };
  541. RT_PIC_OFW_DECLARE(gicv2, gicv2_ofw_ids, gicv2_ofw_init);