board.h 1.2 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-12-05 supperthomas first version
  9. */
  10. #ifndef __BOARD_H__
  11. #define __BOARD_H__
  12. #include <rtthread.h>
  13. #include <stm32l4xx.h>
  14. #include "drv_common.h"
  15. #ifdef __cplusplus
  16. extern "C" {
  17. #endif
  18. #ifdef BSP_USING_GPIO
  19. #include "drv_gpio.h"
  20. /* Board Pin definitions */
  21. #endif /* BSP_USING_GPIO */
  22. /* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/
  23. #define STM32_SRAM_SIZE 64
  24. #define STM32_SRAM_END (0x20000000 + STM32_SRAM_SIZE * 1024)
  25. #define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
  26. #define STM32_FLASH_SIZE (256 * 1024)
  27. #define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
  28. #if defined(__CC_ARM) || defined(__CLANG_ARM)
  29. extern int Image$$RW_IRAM1$$ZI$$Limit;
  30. #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
  31. #elif __ICCARM__
  32. #pragma section="CSTACK"
  33. #define HEAP_BEGIN (__segment_end("CSTACK"))
  34. #else
  35. extern int __bss_end;
  36. #define HEAP_BEGIN ((void *)&__bss_end)
  37. #endif
  38. #define HEAP_END STM32_SRAM_END
  39. void SystemClock_Config(void);
  40. #ifdef __cplusplus
  41. }
  42. #endif
  43. #endif