pic.c 28 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-08-24 GuEe-GUI first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #define DBG_TAG "rtdm.pic"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. #include <drivers/pic.h>
  16. #include <ktime.h>
  17. struct irq_traps
  18. {
  19. rt_list_t list;
  20. void *data;
  21. rt_bool_t (*handler)(void *);
  22. };
  23. static int _ipi_hash[] =
  24. {
  25. #ifdef RT_USING_SMP
  26. [RT_SCHEDULE_IPI] = RT_SCHEDULE_IPI,
  27. [RT_STOP_IPI] = RT_STOP_IPI,
  28. #endif
  29. };
  30. /* reserved ipi */
  31. static int _pirq_hash_idx = RT_ARRAY_SIZE(_ipi_hash);
  32. static struct rt_pic_irq _pirq_hash[MAX_HANDLERS] =
  33. {
  34. [0 ... MAX_HANDLERS - 1] =
  35. {
  36. .irq = -1,
  37. .hwirq = -1,
  38. .mode = RT_IRQ_MODE_NONE,
  39. .priority = RT_UINT32_MAX,
  40. .rw_lock = { },
  41. }
  42. };
  43. static struct rt_spinlock _pic_lock = { };
  44. static rt_size_t _pic_name_max = sizeof("PIC");
  45. static rt_list_t _pic_nodes = RT_LIST_OBJECT_INIT(_pic_nodes);
  46. static rt_list_t _traps_nodes = RT_LIST_OBJECT_INIT(_traps_nodes);
  47. static struct rt_pic_irq *irq2pirq(int irq)
  48. {
  49. struct rt_pic_irq *pirq = RT_NULL;
  50. if ((irq >= 0) && (irq < MAX_HANDLERS))
  51. {
  52. pirq = &_pirq_hash[irq];
  53. if (pirq->irq < 0)
  54. {
  55. pirq = RT_NULL;
  56. }
  57. }
  58. if (!pirq)
  59. {
  60. LOG_E("irq = %d is invalid", irq);
  61. }
  62. return pirq;
  63. }
  64. static void append_pic(struct rt_pic *pic)
  65. {
  66. int pic_name_len = rt_strlen(pic->ops->name);
  67. rt_list_insert_before(&_pic_nodes, &pic->list);
  68. if (pic_name_len > _pic_name_max)
  69. {
  70. _pic_name_max = pic_name_len;
  71. }
  72. }
  73. void rt_pic_default_name(struct rt_pic *pic)
  74. {
  75. if (pic)
  76. {
  77. #if RT_NAME_MAX > 0
  78. rt_strncpy(pic->parent.name, "PIC", RT_NAME_MAX - 1);
  79. pic->parent.name[RT_NAME_MAX - 1] = '\0';
  80. #else
  81. pic->parent.name = "PIC";
  82. #endif
  83. }
  84. }
  85. struct rt_pic *rt_pic_dynamic_cast(void *ptr)
  86. {
  87. struct rt_pic *pic = RT_NULL, *tmp = RT_NULL;
  88. if (ptr)
  89. {
  90. struct rt_object *obj = ptr;
  91. if (obj->type == RT_Object_Class_Unknown)
  92. {
  93. tmp = (void *)obj;
  94. }
  95. else if (obj->type == RT_Object_Class_Device)
  96. {
  97. tmp = (void *)obj + sizeof(struct rt_device);
  98. }
  99. else
  100. {
  101. tmp = (void *)obj + sizeof(struct rt_object);
  102. }
  103. if (tmp && !rt_strcmp(tmp->parent.name, "PIC"))
  104. {
  105. pic = tmp;
  106. }
  107. }
  108. return pic;
  109. }
  110. rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr)
  111. {
  112. rt_err_t err = RT_EOK;
  113. if (pic && pic->ops && pic->ops->name)
  114. {
  115. rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock);
  116. if (_pirq_hash_idx + irq_nr <= RT_ARRAY_SIZE(_pirq_hash))
  117. {
  118. rt_list_init(&pic->list);
  119. rt_pic_default_name(pic);
  120. pic->parent.type = RT_Object_Class_Unknown;
  121. pic->irq_start = _pirq_hash_idx;
  122. pic->irq_nr = irq_nr;
  123. pic->pirqs = &_pirq_hash[_pirq_hash_idx];
  124. _pirq_hash_idx += irq_nr;
  125. append_pic(pic);
  126. LOG_D("%s alloc irqs ranges [%d, %d]", pic->ops->name,
  127. pic->irq_start, pic->irq_start + pic->irq_nr);
  128. }
  129. else
  130. {
  131. LOG_E("%s alloc %d irqs is overflow", pic->ops->name, irq_nr);
  132. err = -RT_EEMPTY;
  133. }
  134. rt_spin_unlock_irqrestore(&_pic_lock, level);
  135. }
  136. else
  137. {
  138. err = -RT_EINVAL;
  139. }
  140. return err;
  141. }
  142. static void config_pirq(struct rt_pic *pic, struct rt_pic_irq *pirq, int irq, int hwirq)
  143. {
  144. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  145. if (pirq->irq < 0)
  146. {
  147. rt_list_init(&pirq->list);
  148. rt_list_init(&pirq->children_nodes);
  149. rt_list_init(&pirq->isr.list);
  150. }
  151. else if (pirq->pic != pic)
  152. {
  153. RT_ASSERT(rt_list_isempty(&pirq->list) == RT_TRUE);
  154. RT_ASSERT(rt_list_isempty(&pirq->children_nodes) == RT_TRUE);
  155. RT_ASSERT(rt_list_isempty(&pirq->isr.list) == RT_TRUE);
  156. }
  157. pirq->irq = irq;
  158. pirq->hwirq = hwirq;
  159. pirq->pic = pic;
  160. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  161. }
  162. int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq)
  163. {
  164. int ipi = ipi_index;
  165. struct rt_pic_irq *pirq;
  166. if (pic && ipi < RT_ARRAY_SIZE(_ipi_hash) && hwirq >= 0 && pic->ops->irq_send_ipi)
  167. {
  168. pirq = &_pirq_hash[ipi];
  169. config_pirq(pic, pirq, ipi, hwirq);
  170. for (int cpuid = 0; cpuid < RT_CPUS_NR; ++cpuid)
  171. {
  172. RT_IRQ_AFFINITY_SET(pirq->affinity, cpuid);
  173. }
  174. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "ipi", ipi, hwirq);
  175. }
  176. else
  177. {
  178. ipi = -RT_EINVAL;
  179. }
  180. return ipi;
  181. }
  182. int rt_pic_config_irq(struct rt_pic *pic, int irq_index, int hwirq)
  183. {
  184. int irq;
  185. if (pic && hwirq >= 0)
  186. {
  187. irq = pic->irq_start + irq_index;
  188. if (irq >= 0 && irq < MAX_HANDLERS)
  189. {
  190. config_pirq(pic, &_pirq_hash[irq], irq, hwirq);
  191. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "irq", irq, hwirq);
  192. }
  193. else
  194. {
  195. irq = -RT_ERROR;
  196. }
  197. }
  198. else
  199. {
  200. irq = -RT_EINVAL;
  201. }
  202. return irq;
  203. }
  204. struct rt_pic_irq *rt_pic_find_ipi(struct rt_pic *pic, int ipi_index)
  205. {
  206. struct rt_pic_irq *pirq = &_pirq_hash[ipi_index];
  207. RT_ASSERT(ipi_index < RT_ARRAY_SIZE(_ipi_hash));
  208. RT_ASSERT(pirq->pic == pic);
  209. return pirq;
  210. }
  211. struct rt_pic_irq *rt_pic_find_pirq(struct rt_pic *pic, int irq)
  212. {
  213. if (pic && irq >= pic->irq_start && irq <= pic->irq_start + pic->irq_nr)
  214. {
  215. return &pic->pirqs[irq - pic->irq_start];
  216. }
  217. return RT_NULL;
  218. }
  219. rt_err_t rt_pic_cascade(struct rt_pic_irq *pirq, int parent_irq)
  220. {
  221. rt_err_t err = RT_EOK;
  222. if (pirq && !pirq->parent && parent_irq >= 0)
  223. {
  224. struct rt_pic_irq *parent;
  225. rt_spin_lock(&pirq->rw_lock);
  226. parent = irq2pirq(parent_irq);
  227. if (parent)
  228. {
  229. pirq->parent = parent;
  230. pirq->priority = parent->priority;
  231. rt_memcpy(&pirq->affinity, &parent->affinity, sizeof(pirq->affinity));
  232. }
  233. rt_spin_unlock(&pirq->rw_lock);
  234. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  235. {
  236. rt_spin_lock(&parent->rw_lock);
  237. rt_list_insert_before(&parent->children_nodes, &pirq->list);
  238. rt_spin_unlock(&parent->rw_lock);
  239. }
  240. }
  241. else
  242. {
  243. err = -RT_EINVAL;
  244. }
  245. return err;
  246. }
  247. rt_err_t rt_pic_uncascade(struct rt_pic_irq *pirq)
  248. {
  249. rt_err_t err = RT_EOK;
  250. if (pirq && pirq->parent)
  251. {
  252. struct rt_pic_irq *parent;
  253. rt_spin_lock(&pirq->rw_lock);
  254. parent = pirq->parent;
  255. pirq->parent = RT_NULL;
  256. rt_spin_unlock(&pirq->rw_lock);
  257. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  258. {
  259. rt_spin_lock(&parent->rw_lock);
  260. rt_list_remove(&pirq->list);
  261. rt_spin_unlock(&parent->rw_lock);
  262. }
  263. }
  264. else
  265. {
  266. err = -RT_EINVAL;
  267. }
  268. return err;
  269. }
  270. rt_err_t rt_pic_attach_irq(int irq, rt_isr_handler_t handler, void *uid, const char *name, int flags)
  271. {
  272. rt_err_t err = -RT_EINVAL;
  273. struct rt_pic_irq *pirq;
  274. if (handler && name && (pirq = irq2pirq(irq)))
  275. {
  276. struct rt_pic_isr *isr = RT_NULL;
  277. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  278. err = RT_EOK;
  279. if (!pirq->isr.action.handler)
  280. {
  281. /* first attach */
  282. isr = &pirq->isr;
  283. rt_list_init(&isr->list);
  284. }
  285. else
  286. {
  287. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  288. if ((isr = rt_malloc(sizeof(*isr))))
  289. {
  290. rt_list_init(&isr->list);
  291. level = rt_spin_lock_irqsave(&pirq->rw_lock);
  292. rt_list_insert_after(&pirq->isr.list, &isr->list);
  293. }
  294. else
  295. {
  296. LOG_E("No memory to save '%s' isr", name);
  297. err = -RT_ERROR;
  298. }
  299. }
  300. if (!err)
  301. {
  302. isr->flags = flags;
  303. isr->action.handler = handler;
  304. isr->action.param = uid;
  305. #ifdef RT_USING_INTERRUPT_INFO
  306. isr->action.counter = 0;
  307. rt_strncpy(isr->action.name, name, RT_NAME_MAX - 1);
  308. isr->action.name[RT_NAME_MAX - 1] = '\0';
  309. #ifdef RT_USING_SMP
  310. rt_memset(isr->action.cpu_counter, 0, sizeof(isr->action.cpu_counter));
  311. #endif
  312. #endif
  313. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  314. }
  315. }
  316. return err;
  317. }
  318. rt_err_t rt_pic_detach_irq(int irq, void *uid)
  319. {
  320. rt_err_t err = -RT_EINVAL;
  321. struct rt_pic_irq *pirq = irq2pirq(irq);
  322. if (pirq)
  323. {
  324. rt_bool_t will_free = RT_FALSE;
  325. struct rt_pic_isr *isr = RT_NULL;
  326. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  327. isr = &pirq->isr;
  328. if (isr->action.param == uid)
  329. {
  330. if (rt_list_isempty(&isr->list))
  331. {
  332. isr->action.handler = RT_NULL;
  333. isr->action.param = RT_NULL;
  334. }
  335. else
  336. {
  337. struct rt_pic_isr *next_isr = rt_list_first_entry(&isr->list, struct rt_pic_isr, list);
  338. rt_list_remove(&next_isr->list);
  339. isr->action.handler = next_isr->action.handler;
  340. isr->action.param = next_isr->action.param;
  341. #ifdef RT_USING_INTERRUPT_INFO
  342. isr->action.counter = next_isr->action.counter;
  343. rt_strncpy(isr->action.name, next_isr->action.name, RT_NAME_MAX);
  344. #ifdef RT_USING_SMP
  345. rt_memcpy(isr->action.cpu_counter, next_isr->action.cpu_counter, sizeof(next_isr->action.cpu_counter));
  346. #endif
  347. #endif
  348. isr = next_isr;
  349. will_free = RT_TRUE;
  350. }
  351. err = RT_EOK;
  352. }
  353. else
  354. {
  355. rt_list_for_each_entry(isr, &pirq->isr.list, list)
  356. {
  357. if (isr->action.param == uid)
  358. {
  359. err = RT_EOK;
  360. will_free = RT_TRUE;
  361. rt_list_remove(&isr->list);
  362. break;
  363. }
  364. }
  365. }
  366. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  367. if (will_free)
  368. {
  369. rt_free(isr);
  370. }
  371. }
  372. return err;
  373. }
  374. rt_err_t rt_pic_add_traps(rt_bool_t (*handler)(void *), void *data)
  375. {
  376. rt_err_t err = -RT_EINVAL;
  377. if (handler)
  378. {
  379. struct irq_traps *traps = rt_malloc(sizeof(*traps));
  380. if (traps)
  381. {
  382. rt_ubase_t level = rt_hw_interrupt_disable();
  383. rt_list_init(&traps->list);
  384. traps->data = data;
  385. traps->handler = handler;
  386. rt_list_insert_before(&_traps_nodes, &traps->list);
  387. err = RT_EOK;
  388. rt_hw_interrupt_enable(level);
  389. }
  390. else
  391. {
  392. LOG_E("No memory to save '%p' handler", handler);
  393. err = -RT_ENOMEM;
  394. }
  395. }
  396. return err;
  397. }
  398. rt_err_t rt_pic_do_traps(void)
  399. {
  400. rt_err_t err = -RT_ERROR;
  401. struct irq_traps *traps;
  402. rt_interrupt_enter();
  403. rt_list_for_each_entry(traps, &_traps_nodes, list)
  404. {
  405. if (traps->handler(traps->data))
  406. {
  407. err = RT_EOK;
  408. break;
  409. }
  410. }
  411. rt_interrupt_leave();
  412. return err;
  413. }
  414. rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq)
  415. {
  416. rt_err_t err = -RT_EEMPTY;
  417. rt_list_t *handler_nodes;
  418. struct rt_irq_desc *action;
  419. #ifdef RT_USING_PIC_STATISTICS
  420. struct timespec ts;
  421. rt_ubase_t irq_time_ns;
  422. rt_ubase_t current_irq_begin;
  423. #endif
  424. RT_ASSERT(pirq != RT_NULL);
  425. RT_ASSERT(pirq->pic != RT_NULL);
  426. #ifdef RT_USING_PIC_STATISTICS
  427. rt_ktime_boottime_get_ns(&ts);
  428. current_irq_begin = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec;
  429. #endif
  430. handler_nodes = &pirq->isr.list;
  431. action = &pirq->isr.action;
  432. if (!rt_list_isempty(&pirq->children_nodes))
  433. {
  434. struct rt_pic_irq *child;
  435. rt_list_for_each_entry(child, &pirq->children_nodes, list)
  436. {
  437. rt_pic_irq_ack(child->irq);
  438. err = rt_pic_handle_isr(child);
  439. rt_pic_irq_eoi(child->irq);
  440. }
  441. }
  442. if (action->handler)
  443. {
  444. action->handler(pirq->irq, action->param);
  445. #ifdef RT_USING_INTERRUPT_INFO
  446. action->counter++;
  447. #ifdef RT_USING_SMP
  448. action->cpu_counter[rt_hw_cpu_id()]++;
  449. #endif
  450. #endif
  451. if (!rt_list_isempty(handler_nodes))
  452. {
  453. struct rt_pic_isr *isr;
  454. rt_list_for_each_entry(isr, handler_nodes, list)
  455. {
  456. action = &isr->action;
  457. RT_ASSERT(action->handler != RT_NULL);
  458. action->handler(pirq->irq, action->param);
  459. #ifdef RT_USING_INTERRUPT_INFO
  460. action->counter++;
  461. #ifdef RT_USING_SMP
  462. action->cpu_counter[rt_hw_cpu_id()]++;
  463. #endif
  464. #endif
  465. }
  466. }
  467. err = RT_EOK;
  468. }
  469. #ifdef RT_USING_PIC_STATISTICS
  470. rt_ktime_boottime_get_ns(&ts);
  471. irq_time_ns = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec - current_irq_begin;
  472. pirq->stat.sum_irq_time_ns += irq_time_ns;
  473. if (irq_time_ns < pirq->stat.min_irq_time_ns || pirq->stat.min_irq_time_ns == 0)
  474. {
  475. pirq->stat.min_irq_time_ns = irq_time_ns;
  476. }
  477. if (irq_time_ns > pirq->stat.max_irq_time_ns)
  478. {
  479. pirq->stat.max_irq_time_ns = irq_time_ns;
  480. }
  481. #endif
  482. return err;
  483. }
  484. rt_weak rt_err_t rt_pic_user_extends(struct rt_pic *pic)
  485. {
  486. return -RT_ENOSYS;
  487. }
  488. rt_err_t rt_pic_irq_init(void)
  489. {
  490. rt_err_t err = RT_EOK;
  491. struct rt_pic *pic;
  492. rt_list_for_each_entry(pic, &_pic_nodes, list)
  493. {
  494. if (pic->ops->irq_init)
  495. {
  496. err = pic->ops->irq_init(pic);
  497. if (err)
  498. {
  499. LOG_E("PIC = %s init fail", pic->ops->name);
  500. break;
  501. }
  502. }
  503. }
  504. return err;
  505. }
  506. rt_err_t rt_pic_irq_finit(void)
  507. {
  508. rt_err_t err = RT_EOK;
  509. struct rt_pic *pic;
  510. rt_list_for_each_entry(pic, &_pic_nodes, list)
  511. {
  512. if (pic->ops->irq_finit)
  513. {
  514. err = pic->ops->irq_finit(pic);
  515. if (err)
  516. {
  517. LOG_E("PIC = %s finit fail", pic->ops->name);
  518. break;
  519. }
  520. }
  521. }
  522. return err;
  523. }
  524. void rt_pic_irq_enable(int irq)
  525. {
  526. struct rt_pic_irq *pirq = irq2pirq(irq);
  527. RT_ASSERT(pirq != RT_NULL);
  528. rt_hw_spin_lock(&pirq->rw_lock.lock);
  529. if (pirq->pic->ops->irq_enable)
  530. {
  531. pirq->pic->ops->irq_enable(pirq);
  532. }
  533. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  534. }
  535. void rt_pic_irq_disable(int irq)
  536. {
  537. struct rt_pic_irq *pirq = irq2pirq(irq);
  538. RT_ASSERT(pirq != RT_NULL);
  539. rt_hw_spin_lock(&pirq->rw_lock.lock);
  540. if (pirq->pic->ops->irq_disable)
  541. {
  542. pirq->pic->ops->irq_disable(pirq);
  543. }
  544. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  545. }
  546. void rt_pic_irq_ack(int irq)
  547. {
  548. struct rt_pic_irq *pirq = irq2pirq(irq);
  549. RT_ASSERT(pirq != RT_NULL);
  550. rt_hw_spin_lock(&pirq->rw_lock.lock);
  551. if (pirq->pic->ops->irq_ack)
  552. {
  553. pirq->pic->ops->irq_ack(pirq);
  554. }
  555. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  556. }
  557. void rt_pic_irq_mask(int irq)
  558. {
  559. struct rt_pic_irq *pirq = irq2pirq(irq);
  560. RT_ASSERT(pirq != RT_NULL);
  561. rt_hw_spin_lock(&pirq->rw_lock.lock);
  562. if (pirq->pic->ops->irq_mask)
  563. {
  564. pirq->pic->ops->irq_mask(pirq);
  565. }
  566. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  567. }
  568. void rt_pic_irq_unmask(int irq)
  569. {
  570. struct rt_pic_irq *pirq = irq2pirq(irq);
  571. RT_ASSERT(pirq != RT_NULL);
  572. rt_hw_spin_lock(&pirq->rw_lock.lock);
  573. if (pirq->pic->ops->irq_unmask)
  574. {
  575. pirq->pic->ops->irq_unmask(pirq);
  576. }
  577. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  578. }
  579. void rt_pic_irq_eoi(int irq)
  580. {
  581. struct rt_pic_irq *pirq = irq2pirq(irq);
  582. RT_ASSERT(pirq != RT_NULL);
  583. rt_hw_spin_lock(&pirq->rw_lock.lock);
  584. if (pirq->pic->ops->irq_eoi)
  585. {
  586. pirq->pic->ops->irq_eoi(pirq);
  587. }
  588. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  589. }
  590. rt_err_t rt_pic_irq_set_priority(int irq, rt_uint32_t priority)
  591. {
  592. rt_err_t err = -RT_EINVAL;
  593. struct rt_pic_irq *pirq = irq2pirq(irq);
  594. if (pirq)
  595. {
  596. rt_hw_spin_lock(&pirq->rw_lock.lock);
  597. if (pirq->pic->ops->irq_set_priority)
  598. {
  599. err = pirq->pic->ops->irq_set_priority(pirq, priority);
  600. if (!err)
  601. {
  602. pirq->priority = priority;
  603. }
  604. }
  605. else
  606. {
  607. err = -RT_ENOSYS;
  608. }
  609. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  610. }
  611. return err;
  612. }
  613. rt_uint32_t rt_pic_irq_get_priority(int irq)
  614. {
  615. rt_uint32_t priority = RT_UINT32_MAX;
  616. struct rt_pic_irq *pirq = irq2pirq(irq);
  617. if (pirq)
  618. {
  619. rt_hw_spin_lock(&pirq->rw_lock.lock);
  620. priority = pirq->priority;
  621. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  622. }
  623. return priority;
  624. }
  625. rt_err_t rt_pic_irq_set_affinity(int irq, rt_bitmap_t *affinity)
  626. {
  627. rt_err_t err = -RT_EINVAL;
  628. struct rt_pic_irq *pirq;
  629. if (affinity && (pirq = irq2pirq(irq)))
  630. {
  631. rt_hw_spin_lock(&pirq->rw_lock.lock);
  632. if (pirq->pic->ops->irq_set_affinity)
  633. {
  634. err = pirq->pic->ops->irq_set_affinity(pirq, affinity);
  635. if (!err)
  636. {
  637. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  638. }
  639. }
  640. else
  641. {
  642. err = -RT_ENOSYS;
  643. }
  644. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  645. }
  646. return err;
  647. }
  648. rt_err_t rt_pic_irq_get_affinity(int irq, rt_bitmap_t *out_affinity)
  649. {
  650. rt_err_t err = -RT_EINVAL;
  651. struct rt_pic_irq *pirq;
  652. if (out_affinity && (pirq = irq2pirq(irq)))
  653. {
  654. rt_hw_spin_lock(&pirq->rw_lock.lock);
  655. rt_memcpy(out_affinity, pirq->affinity, sizeof(pirq->affinity));
  656. err = RT_EOK;
  657. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  658. }
  659. return err;
  660. }
  661. rt_err_t rt_pic_irq_set_triger_mode(int irq, rt_uint32_t mode)
  662. {
  663. rt_err_t err = -RT_EINVAL;
  664. struct rt_pic_irq *pirq;
  665. if ((~mode & RT_IRQ_MODE_MASK) && (pirq = irq2pirq(irq)))
  666. {
  667. rt_hw_spin_lock(&pirq->rw_lock.lock);
  668. if (pirq->pic->ops->irq_set_triger_mode)
  669. {
  670. err = pirq->pic->ops->irq_set_triger_mode(pirq, mode);
  671. if (!err)
  672. {
  673. pirq->mode = mode;
  674. }
  675. }
  676. else
  677. {
  678. err = -RT_ENOSYS;
  679. }
  680. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  681. }
  682. return err;
  683. }
  684. rt_uint32_t rt_pic_irq_get_triger_mode(int irq)
  685. {
  686. rt_uint32_t mode = RT_UINT32_MAX;
  687. struct rt_pic_irq *pirq = irq2pirq(irq);
  688. if (pirq)
  689. {
  690. rt_hw_spin_lock(&pirq->rw_lock.lock);
  691. mode = pirq->mode;
  692. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  693. }
  694. return mode;
  695. }
  696. void rt_pic_irq_send_ipi(int irq, rt_bitmap_t *cpumask)
  697. {
  698. struct rt_pic_irq *pirq;
  699. if (cpumask && (pirq = irq2pirq(irq)))
  700. {
  701. rt_hw_spin_lock(&pirq->rw_lock.lock);
  702. if (pirq->pic->ops->irq_send_ipi)
  703. {
  704. pirq->pic->ops->irq_send_ipi(pirq, cpumask);
  705. }
  706. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  707. }
  708. }
  709. rt_err_t rt_pic_irq_set_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
  710. {
  711. rt_err_t err;
  712. if (pic && hwirq >= 0)
  713. {
  714. if (pic->ops->irq_set_state)
  715. {
  716. err = pic->ops->irq_set_state(pic, hwirq, type, state);
  717. }
  718. else
  719. {
  720. err = -RT_ENOSYS;
  721. }
  722. }
  723. else
  724. {
  725. err = -RT_EINVAL;
  726. }
  727. return err;
  728. }
  729. rt_err_t rt_pic_irq_get_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
  730. {
  731. rt_err_t err;
  732. if (pic && hwirq >= 0)
  733. {
  734. if (pic->ops->irq_get_state)
  735. {
  736. rt_bool_t state;
  737. if (!(err = pic->ops->irq_get_state(pic, hwirq, type, &state)) && out_state)
  738. {
  739. *out_state = state;
  740. }
  741. }
  742. else
  743. {
  744. err = -RT_ENOSYS;
  745. }
  746. }
  747. else
  748. {
  749. err = -RT_EINVAL;
  750. }
  751. return err;
  752. }
  753. rt_err_t rt_pic_irq_set_state(int irq, int type, rt_bool_t state)
  754. {
  755. rt_err_t err;
  756. struct rt_pic_irq *pirq = irq2pirq(irq);
  757. RT_ASSERT(pirq != RT_NULL);
  758. rt_hw_spin_lock(&pirq->rw_lock.lock);
  759. err = rt_pic_irq_set_state_raw(pirq->pic, pirq->hwirq, type, state);
  760. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  761. return err;
  762. }
  763. rt_err_t rt_pic_irq_get_state(int irq, int type, rt_bool_t *out_state)
  764. {
  765. rt_err_t err;
  766. struct rt_pic_irq *pirq = irq2pirq(irq);
  767. RT_ASSERT(pirq != RT_NULL);
  768. rt_hw_spin_lock(&pirq->rw_lock.lock);
  769. err = rt_pic_irq_get_state_raw(pirq->pic, pirq->hwirq, type, out_state);
  770. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  771. return err;
  772. }
  773. void rt_pic_irq_parent_enable(struct rt_pic_irq *pirq)
  774. {
  775. RT_ASSERT(pirq != RT_NULL);
  776. pirq = pirq->parent;
  777. if (pirq->pic->ops->irq_enable)
  778. {
  779. pirq->pic->ops->irq_enable(pirq);
  780. }
  781. }
  782. void rt_pic_irq_parent_disable(struct rt_pic_irq *pirq)
  783. {
  784. RT_ASSERT(pirq != RT_NULL);
  785. pirq = pirq->parent;
  786. if (pirq->pic->ops->irq_disable)
  787. {
  788. pirq->pic->ops->irq_disable(pirq);
  789. }
  790. }
  791. void rt_pic_irq_parent_ack(struct rt_pic_irq *pirq)
  792. {
  793. RT_ASSERT(pirq != RT_NULL);
  794. pirq = pirq->parent;
  795. if (pirq->pic->ops->irq_ack)
  796. {
  797. pirq->pic->ops->irq_ack(pirq);
  798. }
  799. }
  800. void rt_pic_irq_parent_mask(struct rt_pic_irq *pirq)
  801. {
  802. RT_ASSERT(pirq != RT_NULL);
  803. pirq = pirq->parent;
  804. if (pirq->pic->ops->irq_mask)
  805. {
  806. pirq->pic->ops->irq_mask(pirq);
  807. }
  808. }
  809. void rt_pic_irq_parent_unmask(struct rt_pic_irq *pirq)
  810. {
  811. RT_ASSERT(pirq != RT_NULL);
  812. pirq = pirq->parent;
  813. if (pirq->pic->ops->irq_unmask)
  814. {
  815. pirq->pic->ops->irq_unmask(pirq);
  816. }
  817. }
  818. void rt_pic_irq_parent_eoi(struct rt_pic_irq *pirq)
  819. {
  820. RT_ASSERT(pirq != RT_NULL);
  821. pirq = pirq->parent;
  822. if (pirq->pic->ops->irq_eoi)
  823. {
  824. pirq->pic->ops->irq_eoi(pirq);
  825. }
  826. }
  827. rt_err_t rt_pic_irq_parent_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
  828. {
  829. rt_err_t err = -RT_ENOSYS;
  830. RT_ASSERT(pirq != RT_NULL);
  831. pirq = pirq->parent;
  832. if (pirq->pic->ops->irq_set_priority)
  833. {
  834. if (!(err = pirq->pic->ops->irq_set_priority(pirq, priority)))
  835. {
  836. pirq->priority = priority;
  837. }
  838. }
  839. return err;
  840. }
  841. rt_err_t rt_pic_irq_parent_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
  842. {
  843. rt_err_t err = -RT_ENOSYS;
  844. RT_ASSERT(pirq != RT_NULL);
  845. pirq = pirq->parent;
  846. if (pirq->pic->ops->irq_set_affinity)
  847. {
  848. if (!(err = pirq->pic->ops->irq_set_affinity(pirq, affinity)))
  849. {
  850. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  851. }
  852. }
  853. return err;
  854. }
  855. rt_err_t rt_pic_irq_parent_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
  856. {
  857. rt_err_t err = -RT_ENOSYS;
  858. RT_ASSERT(pirq != RT_NULL);
  859. pirq = pirq->parent;
  860. if (pirq->pic->ops->irq_set_triger_mode)
  861. {
  862. if (!(err = pirq->pic->ops->irq_set_triger_mode(pirq, mode)))
  863. {
  864. pirq->mode = mode;
  865. }
  866. }
  867. return err;
  868. }
  869. #ifdef RT_USING_OFW
  870. RT_OFW_STUB_RANGE_EXPORT(pic, _pic_ofw_start, _pic_ofw_end);
  871. static rt_err_t ofw_pic_init(void)
  872. {
  873. struct rt_ofw_node *ic_np;
  874. rt_ofw_foreach_node_by_prop(ic_np, "interrupt-controller")
  875. {
  876. rt_ofw_stub_probe_range(ic_np, &_pic_ofw_start, &_pic_ofw_end);
  877. }
  878. return RT_EOK;
  879. }
  880. #else
  881. static rt_err_t ofw_pic_init(void)
  882. {
  883. return RT_EOK;
  884. }
  885. #endif /* !RT_USING_OFW */
  886. rt_err_t rt_pic_init(void)
  887. {
  888. rt_err_t err;
  889. LOG_D("init start");
  890. err = ofw_pic_init();
  891. LOG_D("init end");
  892. return err;
  893. }
  894. #if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH)
  895. static int list_irq(int argc, char**argv)
  896. {
  897. rt_size_t irq_nr = 0;
  898. rt_bool_t dump_all = RT_FALSE;
  899. const char *const irq_modes[] =
  900. {
  901. [RT_IRQ_MODE_NONE] = "None",
  902. [RT_IRQ_MODE_EDGE_RISING] = "Edge-Rising",
  903. [RT_IRQ_MODE_EDGE_FALLING] = "Edge-Falling",
  904. [RT_IRQ_MODE_EDGE_BOTH] = "Edge-Both",
  905. [RT_IRQ_MODE_LEVEL_HIGH] = "Level-High",
  906. [RT_IRQ_MODE_LEVEL_LOW] = "Level-Low",
  907. };
  908. static char info[RT_CONSOLEBUF_SIZE];
  909. #ifdef RT_USING_SMP
  910. static char cpumask[RT_CPUS_NR + 1] = { [RT_CPUS_NR] = '\0' };
  911. #endif
  912. if (argc > 1)
  913. {
  914. if (!rt_strcmp(argv[1], "all"))
  915. {
  916. dump_all = RT_TRUE;
  917. }
  918. }
  919. rt_kprintf("%-*.s %-*.s %s %-*.s %-*.s %-*.s %-*.sUsers%-*.s",
  920. 6, "IRQ",
  921. 6, "HW-IRQ",
  922. "MSI",
  923. _pic_name_max, "PIC",
  924. 12, "Mode",
  925. #ifdef RT_USING_SMP
  926. RT_CPUS_NR, "CPUs",
  927. #else
  928. 0, 0,
  929. #endif
  930. #ifdef RT_USING_INTERRUPT_INFO
  931. 11, "Count",
  932. 5, ""
  933. #else
  934. 0, 0,
  935. 10, "-Number"
  936. #endif
  937. );
  938. #if defined(RT_USING_SMP) && defined(RT_USING_INTERRUPT_INFO)
  939. for (int i = 0; i < RT_CPUS_NR; i++)
  940. {
  941. rt_kprintf(" cpu%2d ", i);
  942. }
  943. #endif
  944. #ifdef RT_USING_PIC_STATISTICS
  945. rt_kprintf(" max/ns avg/ns min/ns");
  946. #endif
  947. rt_kputs("\n");
  948. for (int i = 0; i < RT_ARRAY_SIZE(_pirq_hash); ++i)
  949. {
  950. struct rt_pic_irq *pirq = &_pirq_hash[i];
  951. if (!pirq->pic || !(dump_all || pirq->isr.action.handler))
  952. {
  953. continue;
  954. }
  955. rt_snprintf(info, sizeof(info), "%-6d %-6d %c %-*.s %-*.s ",
  956. pirq->irq,
  957. pirq->hwirq,
  958. pirq->msi_desc ? 'Y' : 'N',
  959. _pic_name_max, pirq->pic->ops->name,
  960. 12, irq_modes[pirq->mode]);
  961. #ifdef RT_USING_SMP
  962. for (int group = 0, id = 0; group < RT_ARRAY_SIZE(pirq->affinity); ++group)
  963. {
  964. rt_bitmap_t mask = pirq->affinity[group];
  965. for (int idx = 0; id < RT_CPUS_NR && idx < RT_BITMAP_BIT_LEN(1); ++idx, ++id)
  966. {
  967. cpumask[RT_ARRAY_SIZE(cpumask) - id - 2] = '0' + ((mask >> idx) & 1);
  968. }
  969. }
  970. #endif /* RT_USING_SMP */
  971. rt_kputs(info);
  972. #ifdef RT_USING_SMP
  973. rt_kputs(cpumask);
  974. #endif
  975. #ifdef RT_USING_INTERRUPT_INFO
  976. rt_kprintf(" %-10d ", pirq->isr.action.counter);
  977. rt_kprintf("%-*.s", 10, pirq->isr.action.name);
  978. #ifdef RT_USING_SMP
  979. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  980. {
  981. rt_kprintf(" %-10d", pirq->isr.action.cpu_counter[cpuid]);
  982. }
  983. #endif
  984. #ifdef RT_USING_PIC_STATISTICS
  985. rt_kprintf(" %-10d %-10d %-10d", pirq->stat.max_irq_time_ns, pirq->stat.sum_irq_time_ns/pirq->isr.action.counter, pirq->stat.min_irq_time_ns);
  986. #endif
  987. rt_kputs("\n");
  988. if (!rt_list_isempty(&pirq->isr.list))
  989. {
  990. struct rt_pic_isr *repeat_isr;
  991. rt_list_for_each_entry(repeat_isr, &pirq->isr.list, list)
  992. {
  993. rt_kputs(info);
  994. #ifdef RT_USING_SMP
  995. rt_kputs(cpumask);
  996. #endif
  997. rt_kprintf("%-10d ", repeat_isr->action.counter);
  998. rt_kprintf("%-*.s", 10, repeat_isr->action.name);
  999. #ifdef RT_USING_SMP
  1000. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  1001. {
  1002. rt_kprintf(" %-10d", repeat_isr->action.cpu_counter[cpuid]);
  1003. }
  1004. #endif
  1005. #ifdef RT_USING_PIC_STATISTICS
  1006. rt_kprintf(" --- --- ---");
  1007. #endif
  1008. rt_kputs("\n");
  1009. }
  1010. }
  1011. #else
  1012. rt_kprintf(" %d\n", rt_list_len(&pirq->isr.list));
  1013. #endif
  1014. ++irq_nr;
  1015. }
  1016. rt_kprintf("%d IRQs found\n", irq_nr);
  1017. return 0;
  1018. }
  1019. MSH_CMD_EXPORT(list_irq, dump using or args = all of irq information);
  1020. #endif /* RT_USING_CONSOLE && RT_USING_MSH */