bcm283x.c 16 KB

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  1. /*
  2. * Copyright (c) 2006-2019, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-29 zdzn first version
  9. */
  10. #include "bcm283x.h"
  11. rt_uint32_t bcm283x_peri_read(volatile rt_ubase_t addr)
  12. {
  13. rt_uint32_t ret;
  14. __sync_synchronize();
  15. ret = HWREG32(addr);
  16. __sync_synchronize();
  17. return ret;
  18. }
  19. rt_uint32_t bcm283x_peri_read_nb(volatile rt_ubase_t addr)
  20. {
  21. return HWREG32(addr);
  22. }
  23. void bcm283x_peri_write(volatile rt_ubase_t addr, rt_uint32_t value)
  24. {
  25. __sync_synchronize();
  26. HWREG32(addr) = value;
  27. __sync_synchronize();
  28. }
  29. void bcm283x_peri_write_nb(volatile rt_ubase_t addr, rt_uint32_t value)
  30. {
  31. HWREG32(addr) = value;
  32. }
  33. void bcm283x_peri_set_bits(volatile rt_ubase_t addr, rt_uint32_t value, rt_uint32_t mask)
  34. {
  35. rt_uint32_t v = bcm283x_peri_read(addr);
  36. v = (v & ~mask) | (value & mask);
  37. bcm283x_peri_write(addr, v);
  38. }
  39. void bcm283x_gpio_fsel(rt_uint8_t pin, rt_uint8_t mode)
  40. {
  41. volatile rt_ubase_t addr = (BCM283X_GPIO_BASE + BCM283X_GPIO_GPFSEL0 + (pin / 10) * 4);
  42. rt_uint8_t shift = (pin % 10) * 3;
  43. rt_uint32_t mask = BCM283X_GPIO_FSEL_MASK << shift;
  44. rt_uint32_t value = mode << shift;
  45. bcm283x_peri_set_bits(addr, value, mask);
  46. }
  47. void bcm283x_gpio_set(rt_uint8_t pin)
  48. {
  49. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPSET0 + (pin / 32) * 4;
  50. rt_uint8_t shift = pin % 32;
  51. bcm283x_peri_write(addr, 1 << shift);
  52. }
  53. void bcm283x_gpio_clr(rt_uint8_t pin)
  54. {
  55. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPCLR0 + (pin / 32) * 4;
  56. rt_uint8_t shift = pin % 32;
  57. bcm283x_peri_write(addr, 1 << shift);
  58. }
  59. rt_uint8_t bcm283x_gpio_lev(rt_uint8_t pin)
  60. {
  61. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM2835_GPIO_GPLEV0 + (pin / 32) * 4;
  62. rt_uint8_t shift = pin % 32;
  63. rt_uint32_t value = bcm283x_peri_read(addr);
  64. return (value & (1 << shift)) ? HIGH : LOW;
  65. }
  66. rt_uint8_t bcm283x_gpio_eds(rt_uint8_t pin)
  67. {
  68. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
  69. rt_uint8_t shift = pin % 32;
  70. rt_uint32_t value = bcm283x_peri_read(addr);
  71. return (value & (1 << shift)) ? HIGH : LOW;
  72. }
  73. /* Write a 1 to clear the bit in EDS */
  74. void bcm283x_gpio_set_eds(rt_uint8_t pin)
  75. {
  76. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPEDS0 + (pin / 32) * 4;
  77. rt_uint8_t shift = pin % 32;
  78. rt_uint32_t value = 1 << shift;
  79. bcm283x_peri_write(addr, value);
  80. }
  81. /* Rising edge detect enable */
  82. void bcm283x_gpio_ren(rt_uint8_t pin)
  83. {
  84. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
  85. rt_uint8_t shift = pin % 32;
  86. rt_uint32_t value = 1 << shift;
  87. bcm283x_peri_set_bits(addr, value, value);
  88. }
  89. void bcm283x_gpio_clr_ren(rt_uint8_t pin)
  90. {
  91. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPREN0 + (pin / 32) * 4;
  92. rt_uint8_t shift = pin % 32;
  93. rt_uint32_t value = 1 << shift;
  94. bcm283x_peri_set_bits(addr, 0, value);
  95. }
  96. /* Falling edge detect enable */
  97. void bcm283x_gpio_fen(rt_uint8_t pin)
  98. {
  99. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
  100. rt_uint8_t shift = pin % 32;
  101. rt_uint32_t value = 1 << shift;
  102. bcm283x_peri_set_bits(addr, value, value);
  103. }
  104. void bcm283x_gpio_clr_fen(rt_uint8_t pin)
  105. {
  106. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPFEN0 + (pin / 32) * 4;
  107. rt_uint8_t shift = pin % 32;
  108. rt_uint32_t value = 1 << shift;
  109. bcm283x_peri_set_bits(addr, 0, value);
  110. }
  111. /* High detect enable */
  112. void bcm283x_gpio_hen(rt_uint8_t pin)
  113. {
  114. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
  115. rt_uint8_t shift = pin % 32;
  116. rt_uint32_t value = 1 << shift;
  117. bcm283x_peri_set_bits(addr, value, value);
  118. }
  119. void bcm283x_gpio_clr_hen(rt_uint8_t pin)
  120. {
  121. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPHEN0 + (pin / 32) * 4;
  122. rt_uint8_t shift = pin % 32;
  123. rt_uint32_t value = 1 << shift;
  124. bcm283x_peri_set_bits(addr, 0, value);
  125. }
  126. /* Low detect enable */
  127. void bcm283x_gpio_len(rt_uint8_t pin)
  128. {
  129. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
  130. rt_uint8_t shift = pin % 32;
  131. rt_uint32_t value = 1 << shift;
  132. bcm283x_peri_set_bits(addr, value, value);
  133. }
  134. void bcm283x_gpio_clr_len(rt_uint8_t pin)
  135. {
  136. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPLEN0 + (pin / 32) * 4;
  137. rt_uint8_t shift = pin % 32;
  138. rt_uint32_t value = 1 << shift;
  139. bcm283x_peri_set_bits(addr, 0, value);
  140. }
  141. /* Async rising edge detect enable */
  142. void bcm283x_gpio_aren(rt_uint8_t pin)
  143. {
  144. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
  145. rt_uint8_t shift = pin % 32;
  146. rt_uint32_t value = 1 << shift;
  147. bcm283x_peri_set_bits(addr, value, value);
  148. }
  149. void bcm283x_gpio_clr_aren(rt_uint8_t pin)
  150. {
  151. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAREN0 + (pin / 32) * 4;
  152. rt_uint8_t shift = pin % 32;
  153. rt_uint32_t value = 1 << shift;
  154. bcm283x_peri_set_bits(addr, 0, value);
  155. }
  156. /* Async falling edge detect enable */
  157. void bcm283x_gpio_afen(rt_uint8_t pin)
  158. {
  159. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
  160. rt_uint8_t shift = pin % 32;
  161. rt_uint32_t value = 1 << shift;
  162. bcm283x_peri_set_bits(addr, value, value);
  163. }
  164. void bcm283x_gpio_clr_afen(rt_uint8_t pin)
  165. {
  166. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPAFEN0 + (pin / 32) * 4;
  167. rt_uint8_t shift = pin % 32;
  168. rt_uint32_t value = 1 << shift;
  169. bcm283x_peri_set_bits(addr, 0, value);
  170. }
  171. /* Set pullup/down */
  172. void bcm283x_gpio_pud(rt_uint8_t pud)
  173. {
  174. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUD;
  175. bcm283x_peri_write(addr, pud);
  176. }
  177. /* Pullup/down clock
  178. // Clocks the value of pud into the GPIO pin
  179. */
  180. void bcm283x_gpio_pudclk(rt_uint8_t pin, rt_uint8_t on)
  181. {
  182. volatile rt_ubase_t addr = BCM283X_GPIO_BASE + BCM283X_GPIO_GPPUDCLK0 + (pin / 32) * 4;
  183. rt_uint8_t shift = pin % 32;
  184. bcm283x_peri_write(addr, (on? 1 : 0) << shift);
  185. }
  186. void bcm283x_gpio_set_pud(rt_uint8_t pin, rt_uint8_t pud)
  187. {
  188. bcm283x_gpio_pud(pud);
  189. bcm283x_clo_delayMicros(10);
  190. bcm283x_gpio_pudclk(pin, 1);
  191. bcm283x_clo_delayMicros(10);
  192. bcm283x_gpio_pud(BCM283X_GPIO_PUD_OFF);
  193. bcm283x_gpio_pudclk(pin, 0);
  194. }
  195. void bcm283x_gpio_write(rt_uint8_t pin, rt_uint8_t val)
  196. {
  197. if (val)
  198. bcm283x_gpio_set(pin);
  199. else
  200. bcm283x_gpio_clr(pin);
  201. }
  202. rt_uint64_t bcm283x_st_read(void)
  203. {
  204. volatile rt_ubase_t addr;
  205. rt_uint32_t hi, lo;
  206. rt_uint64_t st;
  207. addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
  208. hi = bcm283x_peri_read(addr);
  209. addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
  210. lo = bcm283x_peri_read(addr);
  211. addr = BCM283X_ST_BASE + BCM283X_ST_CHI;
  212. st = bcm283x_peri_read(addr);
  213. /* Test for overflow */
  214. if (st == hi)
  215. {
  216. rt_kprintf(">> 1crash???\n");
  217. st <<= 32;
  218. st += lo;
  219. rt_kprintf(">> 2crash!!!\n");
  220. }
  221. else
  222. {
  223. st <<= 32;
  224. addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
  225. st += bcm283x_peri_read(addr);
  226. }
  227. return st;
  228. }
  229. /* microseconds */
  230. void bcm283x_delayMicroseconds(rt_uint64_t micros)
  231. {
  232. rt_uint64_t start;
  233. start = bcm283x_st_read();
  234. rt_kprintf("bcm283x_st_read result: %d\n", start);
  235. /* Not allowed to access timer registers (result is not as precise)*/
  236. if (start==0)
  237. return;
  238. bcm283x_st_delay(start, micros);
  239. }
  240. void bcm283x_clo_delayMicros(rt_uint32_t micros)
  241. {
  242. volatile rt_uint32_t addr;
  243. rt_uint32_t compare;
  244. addr = BCM283X_ST_BASE + BCM283X_ST_CLO;
  245. compare = bcm283x_peri_read(addr) + micros;
  246. while(bcm283x_peri_read(addr) < compare);
  247. }
  248. void bcm283x_st_delay(rt_uint64_t offset_micros, rt_uint64_t micros)
  249. {
  250. rt_uint64_t compare = offset_micros + micros;
  251. while(bcm283x_st_read() < compare);
  252. }
  253. /* Read an number of bytes from I2C */
  254. rt_uint8_t bcm283x_i2c_read(rt_uint32_t base, rt_uint8_t* buf, rt_uint32_t len)
  255. {
  256. volatile rt_uint32_t dlen = base + BCM283X_BSC_DLEN;
  257. volatile rt_uint32_t fifo = base + BCM283X_BSC_FIFO;
  258. volatile rt_uint32_t status = base + BCM283X_BSC_S;
  259. volatile rt_uint32_t control = base + BCM283X_BSC_C;
  260. rt_uint32_t remaining = len;
  261. rt_uint32_t i = 0;
  262. rt_uint8_t reason = BCM283X_I2C_REASON_OK;
  263. /* Clear FIFO */
  264. bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
  265. /* Clear Status */
  266. bcm283x_peri_write_nb(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
  267. /* Set Data Length */
  268. bcm283x_peri_write_nb(dlen, len);
  269. /* Start read */
  270. bcm283x_peri_write_nb(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ);
  271. /* wait for transfer to complete */
  272. while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
  273. {
  274. /* we must empty the FIFO as it is populated and not use any delay */
  275. while (remaining && bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD)
  276. {
  277. /* Read from FIFO, no barrier */
  278. buf[i] = bcm283x_peri_read_nb(fifo);
  279. i++;
  280. remaining--;
  281. }
  282. }
  283. /* transfer has finished - grab any remaining stuff in FIFO */
  284. while (remaining && (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_RXD))
  285. {
  286. /* Read from FIFO, no barrier */
  287. buf[i] = bcm283x_peri_read_nb(fifo);
  288. i++;
  289. remaining--;
  290. }
  291. /* Received a NACK */
  292. if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
  293. {
  294. reason = BCM283X_I2C_REASON_ERROR_NACK;
  295. }
  296. /* Received Clock Stretch Timeout */
  297. else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
  298. {
  299. reason = BCM283X_I2C_REASON_ERROR_CLKT;
  300. }
  301. /* Not all data is received */
  302. else if (remaining)
  303. {
  304. reason = BCM283X_I2C_REASON_ERROR_DATA;
  305. }
  306. bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
  307. return reason;
  308. }
  309. int bcm283x_i2c_begin(int no)
  310. {
  311. if (0 == no)
  312. {
  313. bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_ALT0); /* SDA */
  314. bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_ALT0); /* SCL */
  315. }
  316. else
  317. {
  318. bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_ALT0); /* SDA */
  319. bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_ALT0); /* SCL */
  320. }
  321. return 0;
  322. }
  323. void bcm283x_i2c_end(int no)
  324. {
  325. if (0 == no)
  326. {
  327. bcm283x_gpio_fsel(BCM_GPIO_PIN_0, BCM283X_GPIO_FSEL_INPT); /* SDA */
  328. bcm283x_gpio_fsel(BCM_GPIO_PIN_1, BCM283X_GPIO_FSEL_INPT); /* SCL */
  329. }
  330. else
  331. {
  332. bcm283x_gpio_fsel(BCM_GPIO_PIN_2, BCM283X_GPIO_FSEL_INPT); /* SDA */
  333. bcm283x_gpio_fsel(BCM_GPIO_PIN_3, BCM283X_GPIO_FSEL_INPT); /* SCL */
  334. }
  335. }
  336. void bcm283x_i2c_setSlaveAddress(int no, rt_uint8_t saddr)
  337. {
  338. volatile rt_uint32_t addr;
  339. if (0 == no)
  340. addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_A;
  341. else
  342. addr = PER_BASE + BCM283X_BSC1_BASE + BCM283X_BSC_A;
  343. bcm283x_peri_write(addr, saddr);
  344. }
  345. void bcm283x_i2c_setClockDivider(int no, rt_uint16_t divider)
  346. {
  347. volatile rt_uint32_t addr;
  348. if (0 == no)
  349. addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
  350. else
  351. addr = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DIV;
  352. bcm283x_peri_write(addr, divider);
  353. }
  354. void bcm283x_i2c_set_baudrate(int no, rt_uint32_t baudrate)
  355. {
  356. rt_uint32_t divider;
  357. divider = (BCM283X_CORE_CLK_HZ / baudrate) & 0xFFFE;
  358. bcm283x_i2c_setClockDivider(no, (rt_uint16_t)divider);
  359. }
  360. /* Writes an number of bytes to I2C */
  361. rt_uint8_t bcm283x_i2c_write(rt_uint32_t base, const rt_uint8_t * buf, rt_uint32_t len)
  362. {
  363. volatile rt_uint32_t dlen = base + BCM283X_BSC_DLEN;
  364. volatile rt_uint32_t fifo = base + BCM283X_BSC_FIFO;
  365. volatile rt_uint32_t status = base + BCM283X_BSC_S;
  366. volatile rt_uint32_t control = base + BCM283X_BSC_C;
  367. rt_uint32_t remaining = len;
  368. rt_uint32_t i = 0;
  369. rt_uint8_t reason = BCM283X_I2C_REASON_OK;
  370. /* Clear FIFO */
  371. bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
  372. /* Clear Status */
  373. bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
  374. /* Set Data Length */
  375. bcm283x_peri_write(dlen, len);
  376. /* pre populate FIFO with max buffer */
  377. while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
  378. {
  379. bcm283x_peri_write_nb(fifo, buf[i]);
  380. i++;
  381. remaining--;
  382. }
  383. /* Enable device and start transfer */
  384. bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
  385. /* Transfer is over when BCM2835_BSC_S_DONE */
  386. while(!(bcm283x_peri_read(status) & BCM283X_BSC_S_DONE))
  387. {
  388. while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_TXD))
  389. {
  390. /* Write to FIFO */
  391. bcm283x_peri_write(fifo, buf[i]);
  392. i++;
  393. remaining--;
  394. }
  395. }
  396. /* Received a NACK */
  397. if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
  398. {
  399. reason = BCM283X_I2C_REASON_ERROR_NACK;
  400. }
  401. /* Received Clock Stretch Timeout */
  402. else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
  403. {
  404. reason = BCM283X_I2C_REASON_ERROR_CLKT;
  405. }
  406. /* Not all data is sent */
  407. else if (remaining)
  408. {
  409. reason = BCM283X_I2C_REASON_ERROR_DATA;
  410. }
  411. bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
  412. return reason;
  413. }
  414. rt_uint8_t bcm283x_i2c_write_read_rs(char* cmds, rt_uint32_t cmds_len, char* buf, rt_uint32_t buf_len)
  415. {
  416. volatile rt_uint32_t dlen = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_DLEN;
  417. volatile rt_uint32_t fifo = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_FIFO;
  418. volatile rt_uint32_t status = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_S;
  419. volatile rt_uint32_t control = PER_BASE + BCM283X_BSC0_BASE + BCM283X_BSC_C;
  420. rt_uint32_t remaining = cmds_len;
  421. rt_uint32_t i = 0;
  422. rt_uint8_t reason = BCM283X_I2C_REASON_OK;
  423. /* Clear FIFO */
  424. bcm283x_peri_set_bits(control, BCM283X_BSC_C_CLEAR_1, BCM283X_BSC_C_CLEAR_1);
  425. /* Clear Status */
  426. bcm283x_peri_write(status, BCM283X_BSC_S_CLKT | BCM283X_BSC_S_ERR | BCM283X_BSC_S_DONE);
  427. /* Set Data Length */
  428. bcm283x_peri_write(dlen, cmds_len);
  429. /* pre populate FIFO with max buffer */
  430. while(remaining && (i < BCM283X_BSC_FIFO_SIZE))
  431. {
  432. bcm283x_peri_write_nb(fifo, cmds[i]);
  433. i++;
  434. remaining--;
  435. }
  436. /* Enable device and start transfer */
  437. bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST);
  438. /* poll for transfer has started (way to do repeated start, from BCM2835 datasheet) */
  439. while (!(bcm283x_peri_read(status) & BCM283X_BSC_S_TA))
  440. {
  441. /* Linux may cause us to miss entire transfer stage */
  442. if (bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE)
  443. break;
  444. }
  445. remaining = buf_len;
  446. i = 0;
  447. /* Send a repeated start with read bit set in address */
  448. bcm283x_peri_write(dlen, buf_len);
  449. bcm283x_peri_write(control, BCM283X_BSC_C_I2CEN | BCM283X_BSC_C_ST | BCM283X_BSC_C_READ);
  450. /* Wait for write to complete and first byte back. */
  451. bcm283x_clo_delayMicros(100);
  452. /* wait for transfer to complete */
  453. while (!(bcm283x_peri_read_nb(status) & BCM283X_BSC_S_DONE))
  454. {
  455. /* we must empty the FIFO as it is populated and not use any delay */
  456. while (remaining && bcm283x_peri_read(status) & BCM283X_BSC_S_RXD)
  457. {
  458. /* Read from FIFO, no barrier */
  459. buf[i] = bcm283x_peri_read_nb(fifo);
  460. i++;
  461. remaining--;
  462. }
  463. }
  464. /* transfer has finished - grab any remaining stuff in FIFO */
  465. while (remaining && (bcm283x_peri_read(status) & BCM283X_BSC_S_RXD))
  466. {
  467. /* Read from FIFO */
  468. buf[i] = bcm283x_peri_read(fifo);
  469. i++;
  470. remaining--;
  471. }
  472. /* Received a NACK */
  473. if (bcm283x_peri_read(status) & BCM283X_BSC_S_ERR)
  474. {
  475. reason = BCM283X_I2C_REASON_ERROR_NACK;
  476. }
  477. /* Received Clock Stretch Timeout */
  478. else if (bcm283x_peri_read(status) & BCM283X_BSC_S_CLKT)
  479. {
  480. reason = BCM283X_I2C_REASON_ERROR_CLKT;
  481. }
  482. /* Not all data is sent */
  483. else if (remaining)
  484. {
  485. reason = BCM283X_I2C_REASON_ERROR_DATA;
  486. }
  487. bcm283x_peri_set_bits(control, BCM283X_BSC_S_DONE, BCM283X_BSC_S_DONE);
  488. return reason;
  489. }