pin_mux.c 11 KB

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  1. /*
  2. * Copyright 2017 NXP
  3. * All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. /*
  8. * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  9. !!GlobalInfo
  10. product: Pins v3.0
  11. processor: RV32M1
  12. package_id: RV32M1
  13. mcu_data: ksdk2_0
  14. processor_version: 0.0.0
  15. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  16. */
  17. #include "fsl_common.h"
  18. #include "fsl_port.h"
  19. #include "pin_mux.h"
  20. /*FUNCTION**********************************************************************
  21. *
  22. * Function Name : BOARD_InitBootPins
  23. * Description : Calls initialization functions.
  24. *
  25. *END**************************************************************************/
  26. void BOARD_InitBootPins(void) {
  27. BOARD_InitPins();
  28. }
  29. #define PIN6_IDX 6u /*!< Pin number for pin 6 in a port */
  30. #define PIN7_IDX 7u /*!< Pin number for pin 7 in a port */
  31. #define PIN8_IDX 8u /*!< Pin number for pin 8 in a port */
  32. #define PIN9_IDX 9u /*!< Pin number for pin 9 in a port */
  33. #define PIN10_IDX 10u /*!< Pin number for pin 10 in a port */
  34. #define PIN11_IDX 11u /*!< Pin number for pin 11 in a port */
  35. #define PIN22_IDX 22u /*!< Pin number for pin 22 in a port */
  36. #define PIN23_IDX 23u /*!< Pin number for pin 23 in a port */
  37. #define PIN24_IDX 24u /*!< Pin number for pin 24 in a port */
  38. #define PIN25_IDX 25u /*!< Pin number for pin 25 in a port */
  39. #define PIN26_IDX 26u /*!< Pin number for pin 26 in a port */
  40. #define PIN27_IDX 27u /*!< Pin number for pin 27 in a port */
  41. /*
  42. * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
  43. BOARD_InitPins:
  44. - options: {callFromInitBoot: 'true', coreID: cm4, enableClock: 'true'}
  45. - pin_list:
  46. - {pin_num: N2, peripheral: LPUART0, signal: RX, pin_signal: LPCMP0_IN0/PTC7/LLWU_P15/LPSPI0_PCS3/LPUART0_RX/LPI2C1_HREQ/TPM0_CH0/LPTMR1_ALT1}
  47. - {pin_num: P3, peripheral: LPUART0, signal: TX, pin_signal: LPCMP0_IN1/PTC8/LPSPI0_SCK/LPUART0_TX/LPI2C0_HREQ/TPM0_CH1}
  48. - {pin_num: B5, peripheral: LPUART1, signal: RX, pin_signal: PTA25/LPUART1_RX/LPSPI3_SOUT/LPI2C2_SDAS/FB_AD31}
  49. - {pin_num: A5, peripheral: LPUART1, signal: TX, pin_signal: PTA26/LPUART1_TX/LPSPI3_PCS2/LPI2C2_SCLS/FB_AD30}
  50. - {pin_num: U11, peripheral: SDHC0, signal: CMD, pin_signal: ADC0_SE12/PTD9/SDHC0_CMD/LPSPI2_SIN/LPI2C1_SCLS/TRACE_DATA0/TPM2_CH2/FXIO0_D29, slew_rate: fast, open_drain: disable,
  51. drive_strength: low, pull_select: up, pull_enable: enable}
  52. - {pin_num: P10, peripheral: SDHC0, signal: 'DATA, 0', pin_signal: ADC0_SE10/PTD7/SDHC0_D0/LPSPI2_SOUT/EMVSIM0_PD/TRACE_DATA2/TPM2_CH4/FXIO0_D27, slew_rate: fast,
  53. open_drain: disable, pull_select: up, pull_enable: enable}
  54. - {pin_num: U9, peripheral: SDHC0, signal: 'DATA, 1', pin_signal: ADC0_SE9/PTD6/SDHC0_D1/LPSPI2_SCK/EMVSIM0_IO/TRACE_DATA3/TPM2_CH5/FXIO0_D26, slew_rate: fast,
  55. open_drain: disable, pull_select: up, pull_enable: enable}
  56. - {pin_num: R11, peripheral: SDHC0, signal: 'DATA, 2', pin_signal: ADC0_SE14/PTD11/SDHC0_D2/USB0_SOF_OUT/LPI2C1_SCL/CLKOUT/TPM2_CH0/FXIO0_D31, slew_rate: fast,
  57. open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
  58. - {pin_num: P11, peripheral: SDHC0, signal: 'DATA, 3', pin_signal: ADC0_SE13/PTD10/LLWU_P20/SDHC0_D3/LPSPI2_PCS0/LPI2C1_SDA/TRACE_CLK_OUT/TPM2_CH1/FXIO0_D30, slew_rate: fast,
  59. open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
  60. - {pin_num: T9, peripheral: SDHC0, signal: DCLK, pin_signal: ADC0_SE11/PTD8/LLWU_P19/SDHC0_DCLK/LPSPI2_PCS2/LPI2C1_SDAS/TRACE_DATA1/TPM2_CH3/FXIO0_D28, slew_rate: fast,
  61. open_drain: disable, drive_strength: low, pull_select: up, pull_enable: enable}
  62. - {pin_num: P6, peripheral: GPIOC, signal: 'GPIO, 27', pin_signal: PTC27/TPM0_CH4, slew_rate: fast, open_drain: disable, pull_select: down, pull_enable: disable}
  63. * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
  64. */
  65. /*FUNCTION**********************************************************************
  66. *
  67. * Function Name : BOARD_InitPins
  68. * Description : Configures pin routing and optionally pin electrical features.
  69. *
  70. *END**************************************************************************/
  71. void BOARD_InitPins(void) {
  72. CLOCK_EnableClock(kCLOCK_PortA); /* Clock Gate Control: 0x01u */
  73. CLOCK_EnableClock(kCLOCK_PortC); /* Clock Gate Control: 0x01u */
  74. CLOCK_EnableClock(kCLOCK_PortD); /* Clock Gate Control: 0x01u */
  75. const port_pin_config_t portc27_pinP6_config = {
  76. kPORT_PullDisable, /* Internal pull-up/down resistor is disabled */
  77. kPORT_FastSlewRate, /* Fast slew rate is configured */
  78. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  79. kPORT_OpenDrainDisable, /* Open drain is disabled */
  80. kPORT_LowDriveStrength, /* Low drive strength is configured */
  81. kPORT_MuxAsGpio, /* Pin is configured as PTC27 */
  82. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  83. };
  84. PORT_SetPinConfig(PORTC, PIN27_IDX, &portc27_pinP6_config); /* PORTC27 (pin P6) is configured as PTC27 */
  85. PORT_SetPinMux(PORTC, PIN7_IDX, kPORT_MuxAlt3); /* PORTC7 (pin N2) is configured as LPUART0_RX */
  86. PORT_SetPinMux(PORTC, PIN8_IDX, kPORT_MuxAlt3); /* PORTC8 (pin P3) is configured as LPUART0_TX */
  87. const port_pin_config_t portd10_pinP11_config = {
  88. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  89. kPORT_FastSlewRate, /* Fast slew rate is configured */
  90. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  91. kPORT_OpenDrainDisable, /* Open drain is disabled */
  92. kPORT_LowDriveStrength, /* Low drive strength is configured */
  93. kPORT_MuxAlt2, /* Pin is configured as SDHC0_D3 */
  94. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  95. };
  96. PORT_SetPinConfig(PORTD, PIN10_IDX, &portd10_pinP11_config); /* PORTD10 (pin P11) is configured as SDHC0_D3 */
  97. const port_pin_config_t portd11_pinR11_config = {
  98. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  99. kPORT_FastSlewRate, /* Fast slew rate is configured */
  100. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  101. kPORT_OpenDrainDisable, /* Open drain is disabled */
  102. kPORT_LowDriveStrength, /* Low drive strength is configured */
  103. kPORT_MuxAlt2, /* Pin is configured as SDHC0_D2 */
  104. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  105. };
  106. PORT_SetPinConfig(PORTD, PIN11_IDX, &portd11_pinR11_config); /* PORTD11 (pin R11) is configured as SDHC0_D2 */
  107. const port_pin_config_t portd6_pinU9_config = {
  108. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  109. kPORT_FastSlewRate, /* Fast slew rate is configured */
  110. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  111. kPORT_OpenDrainDisable, /* Open drain is disabled */
  112. kPORT_LowDriveStrength, /* Low drive strength is configured */
  113. kPORT_MuxAlt2, /* Pin is configured as SDHC0_D1 */
  114. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  115. };
  116. PORT_SetPinConfig(PORTD, PIN6_IDX, &portd6_pinU9_config); /* PORTD6 (pin U9) is configured as SDHC0_D1 */
  117. const port_pin_config_t portd7_pinP10_config = {
  118. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  119. kPORT_FastSlewRate, /* Fast slew rate is configured */
  120. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  121. kPORT_OpenDrainDisable, /* Open drain is disabled */
  122. kPORT_LowDriveStrength, /* Low drive strength is configured */
  123. kPORT_MuxAlt2, /* Pin is configured as SDHC0_D0 */
  124. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  125. };
  126. PORT_SetPinConfig(PORTD, PIN7_IDX, &portd7_pinP10_config); /* PORTD7 (pin P10) is configured as SDHC0_D0 */
  127. const port_pin_config_t portd8_pinT9_config = {
  128. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  129. kPORT_FastSlewRate, /* Fast slew rate is configured */
  130. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  131. kPORT_OpenDrainDisable, /* Open drain is disabled */
  132. kPORT_LowDriveStrength, /* Low drive strength is configured */
  133. kPORT_MuxAlt2, /* Pin is configured as SDHC0_DCLK */
  134. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  135. };
  136. PORT_SetPinConfig(PORTD, PIN8_IDX, &portd8_pinT9_config); /* PORTD8 (pin T9) is configured as SDHC0_DCLK */
  137. const port_pin_config_t portd9_pinU11_config = {
  138. kPORT_PullUp, /* Internal pull-up resistor is enabled */
  139. kPORT_FastSlewRate, /* Fast slew rate is configured */
  140. kPORT_PassiveFilterDisable, /* Passive filter is disabled */
  141. kPORT_OpenDrainDisable, /* Open drain is disabled */
  142. kPORT_LowDriveStrength, /* Low drive strength is configured */
  143. kPORT_MuxAlt2, /* Pin is configured as SDHC0_CMD */
  144. kPORT_UnlockRegister /* Pin Control Register fields [15:0] are not locked */
  145. };
  146. PORT_SetPinConfig(PORTD, PIN9_IDX, &portd9_pinU11_config); /* PORTD9 (pin U11) is configured as SDHC0_CMD */
  147. PORT_SetPinMux(PORTA, PIN22_IDX, kPORT_MuxAsGpio); /* PORTA22 (pin D6) is configured as PTA24 */
  148. PORT_SetPinMux(PORTA, PIN23_IDX, kPORT_MuxAsGpio); /* PORTA23 (pin D6) is configured as PTA24 */
  149. PORT_SetPinMux(PORTA, PIN24_IDX, kPORT_MuxAsGpio); /* PORTA24 (pin D6) is configured as PTA24 */
  150. PORT_SetPinMux(PORTA, PIN25_IDX, kPORT_MuxAlt2); /* PORTA25 (pin B5) is configured as LPUART1_RX */
  151. PORT_SetPinMux(PORTA, PIN26_IDX, kPORT_MuxAlt2); /* PORTA26 (pin A5) is configured as LPUART1_TX */
  152. }
  153. /*******************************************************************************
  154. * EOF
  155. ******************************************************************************/