usbh_rtl8152.c 65 KB

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  1. /*
  2. * Copyright (c) 2024, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbh_core.h"
  7. #include "usbh_rtl8152.h"
  8. #undef USB_DBG_TAG
  9. #define USB_DBG_TAG "rtl8152"
  10. #include "usb_log.h"
  11. #define DEV_FORMAT "/dev/rtl8152"
  12. static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_rx_buffer[CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE];
  13. static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_tx_buffer[CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE];
  14. static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_inttx_buffer[2];
  15. USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_buf[32];
  16. static struct usbh_rtl8152 g_rtl8152_class;
  17. #define RTL8152_REQ_GET_REGS 0x05
  18. #define RTL8152_REQ_SET_REGS 0x05
  19. #define BYTE_EN_DWORD 0xff
  20. #define BYTE_EN_WORD 0x33
  21. #define BYTE_EN_BYTE 0x11
  22. #define BYTE_EN_SIX_BYTES 0x3f
  23. #define BYTE_EN_START_MASK 0x0f
  24. #define BYTE_EN_END_MASK 0xf0
  25. #define MCU_TYPE_PLA 0x0100
  26. #define MCU_TYPE_USB 0x0000
  27. /* Define these values to match your device */
  28. #define VENDOR_ID_REALTEK 0x0bda
  29. #define VENDOR_ID_MICROSOFT 0x045e
  30. #define VENDOR_ID_SAMSUNG 0x04e8
  31. #define VENDOR_ID_LENOVO 0x17ef
  32. #define VENDOR_ID_LINKSYS 0x13b1
  33. #define VENDOR_ID_NVIDIA 0x0955
  34. #define VENDOR_ID_TPLINK 0x2357
  35. #define VENDOR_ID_DLINK 0x2001
  36. #define VENDOR_ID_ASUS 0x0b05
  37. #define R8152_PHY_ID 32
  38. #define PLA_IDR 0xc000
  39. #define PLA_RCR 0xc010
  40. #define PLA_RCR1 0xc012
  41. #define PLA_RMS 0xc016
  42. #define PLA_RXFIFO_CTRL0 0xc0a0
  43. #define PLA_RXFIFO_FULL 0xc0a2
  44. #define PLA_RXFIFO_CTRL1 0xc0a4
  45. #define PLA_RX_FIFO_FULL 0xc0a6
  46. #define PLA_RXFIFO_CTRL2 0xc0a8
  47. #define PLA_RX_FIFO_EMPTY 0xc0aa
  48. #define PLA_DMY_REG0 0xc0b0
  49. #define PLA_FMC 0xc0b4
  50. #define PLA_CFG_WOL 0xc0b6
  51. #define PLA_TEREDO_CFG 0xc0bc
  52. #define PLA_TEREDO_WAKE_BASE 0xc0c4
  53. #define PLA_MAR 0xcd00
  54. #define PLA_BACKUP 0xd000
  55. #define PLA_BDC_CR 0xd1a0
  56. #define PLA_TEREDO_TIMER 0xd2cc
  57. #define PLA_REALWOW_TIMER 0xd2e8
  58. #define PLA_UPHY_TIMER 0xd388
  59. #define PLA_SUSPEND_FLAG 0xd38a
  60. #define PLA_INDICATE_FALG 0xd38c
  61. #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
  62. #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
  63. #define PLA_EXTRA_STATUS 0xd398
  64. #define PLA_GPHY_CTRL 0xd3ae
  65. #define PLA_POL_GPIO_CTRL 0xdc6a
  66. #define PLA_EFUSE_DATA 0xdd00
  67. #define PLA_EFUSE_CMD 0xdd02
  68. #define PLA_LEDSEL 0xdd90
  69. #define PLA_LED_FEATURE 0xdd92
  70. #define PLA_PHYAR 0xde00
  71. #define PLA_BOOT_CTRL 0xe004
  72. #define PLA_LWAKE_CTRL_REG 0xe007
  73. #define PLA_GPHY_INTR_IMR 0xe022
  74. #define PLA_EEE_CR 0xe040
  75. #define PLA_EEE_TXTWSYS 0xe04c
  76. #define PLA_EEE_TXTWSYS_2P5G 0xe058
  77. #define PLA_EEEP_CR 0xe080
  78. #define PLA_MAC_PWR_CTRL 0xe0c0
  79. #define PLA_MAC_PWR_CTRL2 0xe0ca
  80. #define PLA_MAC_PWR_CTRL3 0xe0cc
  81. #define PLA_MAC_PWR_CTRL4 0xe0ce
  82. #define PLA_WDT6_CTRL 0xe428
  83. #define PLA_TCR0 0xe610
  84. #define PLA_TCR1 0xe612
  85. #define PLA_MTPS 0xe615
  86. #define PLA_TXFIFO_CTRL 0xe618
  87. #define PLA_TXFIFO_FULL 0xe61a
  88. #define PLA_RSTTALLY 0xe800
  89. #define PLA_CR 0xe813
  90. #define PLA_CRWECR 0xe81c
  91. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  92. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  93. #define PLA_CONFIG5 0xe822
  94. #define PLA_PHY_PWR 0xe84c
  95. #define PLA_OOB_CTRL 0xe84f
  96. #define PLA_CPCR 0xe854
  97. #define PLA_MISC_0 0xe858
  98. #define PLA_MISC_1 0xe85a
  99. #define PLA_OCP_GPHY_BASE 0xe86c
  100. #define PLA_TALLYCNT 0xe890
  101. #define PLA_SFF_STS_7 0xe8de
  102. #define PLA_PHYSTATUS 0xe908
  103. #define PLA_CONFIG6 0xe90a /* CONFIG6 */
  104. #define PLA_USB_CFG 0xe952
  105. #define PLA_BP_BA 0xfc26
  106. #define PLA_BP_0 0xfc28
  107. #define PLA_BP_1 0xfc2a
  108. #define PLA_BP_2 0xfc2c
  109. #define PLA_BP_3 0xfc2e
  110. #define PLA_BP_4 0xfc30
  111. #define PLA_BP_5 0xfc32
  112. #define PLA_BP_6 0xfc34
  113. #define PLA_BP_7 0xfc36
  114. #define PLA_BP_EN 0xfc38
  115. #define USB_USB2PHY 0xb41e
  116. #define USB_SSPHYLINK1 0xb426
  117. #define USB_SSPHYLINK2 0xb428
  118. #define USB_L1_CTRL 0xb45e
  119. #define USB_U2P3_CTRL 0xb460
  120. #define USB_CSR_DUMMY1 0xb464
  121. #define USB_CSR_DUMMY2 0xb466
  122. #define USB_DEV_STAT 0xb808
  123. #define USB_CONNECT_TIMER 0xcbf8
  124. #define USB_MSC_TIMER 0xcbfc
  125. #define USB_BURST_SIZE 0xcfc0
  126. #define USB_FW_FIX_EN0 0xcfca
  127. #define USB_FW_FIX_EN1 0xcfcc
  128. #define USB_LPM_CONFIG 0xcfd8
  129. #define USB_ECM_OPTION 0xcfee
  130. #define USB_CSTMR 0xcfef /* RTL8153A */
  131. #define USB_MISC_2 0xcfff
  132. #define USB_ECM_OP 0xd26b
  133. #define USB_GPHY_CTRL 0xd284
  134. #define USB_SPEED_OPTION 0xd32a
  135. #define USB_FW_CTRL 0xd334 /* RTL8153B */
  136. #define USB_FC_TIMER 0xd340
  137. #define USB_USB_CTRL 0xd406
  138. #define USB_PHY_CTRL 0xd408
  139. #define USB_TX_AGG 0xd40a
  140. #define USB_RX_BUF_TH 0xd40c
  141. #define USB_USB_TIMER 0xd428
  142. #define USB_RX_EARLY_TIMEOUT 0xd42c
  143. #define USB_RX_EARLY_SIZE 0xd42e
  144. #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
  145. #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
  146. #define USB_TX_DMA 0xd434
  147. #define USB_UPT_RXDMA_OWN 0xd437
  148. #define USB_UPHY3_MDCMDIO 0xd480
  149. #define USB_TOLERANCE 0xd490
  150. #define USB_LPM_CTRL 0xd41a
  151. #define USB_BMU_RESET 0xd4b0
  152. #define USB_BMU_CONFIG 0xd4b4
  153. #define USB_U1U2_TIMER 0xd4da
  154. #define USB_FW_TASK 0xd4e8 /* RTL8153B */
  155. #define USB_RX_AGGR_NUM 0xd4ee
  156. #define USB_UPS_CTRL 0xd800
  157. #define USB_POWER_CUT 0xd80a
  158. #define USB_MISC_0 0xd81a
  159. #define USB_MISC_1 0xd81f
  160. #define USB_AFE_CTRL2 0xd824
  161. #define USB_UPHY_XTAL 0xd826
  162. #define USB_UPS_CFG 0xd842
  163. #define USB_UPS_FLAGS 0xd848
  164. #define USB_WDT1_CTRL 0xe404
  165. #define USB_WDT11_CTRL 0xe43c
  166. #define USB_BP_BA PLA_BP_BA
  167. #define USB_BP_0 PLA_BP_0
  168. #define USB_BP_1 PLA_BP_1
  169. #define USB_BP_2 PLA_BP_2
  170. #define USB_BP_3 PLA_BP_3
  171. #define USB_BP_4 PLA_BP_4
  172. #define USB_BP_5 PLA_BP_5
  173. #define USB_BP_6 PLA_BP_6
  174. #define USB_BP_7 PLA_BP_7
  175. #define USB_BP_EN PLA_BP_EN /* RTL8153A */
  176. #define USB_BP_8 0xfc38 /* RTL8153B */
  177. #define USB_BP_9 0xfc3a
  178. #define USB_BP_10 0xfc3c
  179. #define USB_BP_11 0xfc3e
  180. #define USB_BP_12 0xfc40
  181. #define USB_BP_13 0xfc42
  182. #define USB_BP_14 0xfc44
  183. #define USB_BP_15 0xfc46
  184. #define USB_BP2_EN 0xfc48
  185. /* OCP Registers */
  186. #define OCP_ALDPS_CONFIG 0x2010
  187. #define OCP_EEE_CONFIG1 0x2080
  188. #define OCP_EEE_CONFIG2 0x2092
  189. #define OCP_EEE_CONFIG3 0x2094
  190. #define OCP_BASE_MII 0xa400
  191. #define OCP_EEE_AR 0xa41a
  192. #define OCP_EEE_DATA 0xa41c
  193. #define OCP_PHY_STATUS 0xa420
  194. #define OCP_INTR_EN 0xa424
  195. #define OCP_NCTL_CFG 0xa42c
  196. #define OCP_POWER_CFG 0xa430
  197. #define OCP_EEE_CFG 0xa432
  198. #define OCP_SRAM_ADDR 0xa436
  199. #define OCP_SRAM_DATA 0xa438
  200. #define OCP_DOWN_SPEED 0xa442
  201. #define OCP_EEE_ABLE 0xa5c4
  202. #define OCP_EEE_ADV 0xa5d0
  203. #define OCP_EEE_LPABLE 0xa5d2
  204. #define OCP_10GBT_CTRL 0xa5d4
  205. #define OCP_10GBT_STAT 0xa5d6
  206. #define OCP_EEE_ADV2 0xa6d4
  207. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  208. #define OCP_PHY_PATCH_STAT 0xb800
  209. #define OCP_PHY_PATCH_CMD 0xb820
  210. #define OCP_PHY_LOCK 0xb82e
  211. #define OCP_ADC_IOFFSET 0xbcfc
  212. #define OCP_ADC_CFG 0xbc06
  213. #define OCP_SYSCLK_CFG 0xc416
  214. /* SRAM Register */
  215. #define SRAM_GREEN_CFG 0x8011
  216. #define SRAM_LPF_CFG 0x8012
  217. #define SRAM_GPHY_FW_VER 0x801e
  218. #define SRAM_10M_AMP1 0x8080
  219. #define SRAM_10M_AMP2 0x8082
  220. #define SRAM_IMPEDANCE 0x8084
  221. #define SRAM_PHY_LOCK 0xb82e
  222. /* PLA_RCR */
  223. #define RCR_AAP 0x00000001
  224. #define RCR_APM 0x00000002
  225. #define RCR_AM 0x00000004
  226. #define RCR_AB 0x00000008
  227. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  228. #define SLOT_EN BIT(11)
  229. /* PLA_RCR1 */
  230. #define OUTER_VLAN BIT(7)
  231. #define INNER_VLAN BIT(6)
  232. /* PLA_RXFIFO_CTRL0 */
  233. #define RXFIFO_THR1_NORMAL 0x00080002
  234. #define RXFIFO_THR1_OOB 0x01800003
  235. /* PLA_RXFIFO_FULL */
  236. #define RXFIFO_FULL_MASK 0xfff
  237. /* PLA_RXFIFO_CTRL1 */
  238. #define RXFIFO_THR2_FULL 0x00000060
  239. #define RXFIFO_THR2_HIGH 0x00000038
  240. #define RXFIFO_THR2_OOB 0x0000004a
  241. #define RXFIFO_THR2_NORMAL 0x00a0
  242. /* PLA_RXFIFO_CTRL2 */
  243. #define RXFIFO_THR3_FULL 0x00000078
  244. #define RXFIFO_THR3_HIGH 0x00000048
  245. #define RXFIFO_THR3_OOB 0x0000005a
  246. #define RXFIFO_THR3_NORMAL 0x0110
  247. /* PLA_TXFIFO_CTRL */
  248. #define TXFIFO_THR_NORMAL 0x00400008
  249. #define TXFIFO_THR_NORMAL2 0x01000008
  250. /* PLA_DMY_REG0 */
  251. #define ECM_ALDPS 0x0002
  252. /* PLA_FMC */
  253. #define FMC_FCR_MCU_EN 0x0001
  254. /* PLA_EEEP_CR */
  255. #define EEEP_CR_EEEP_TX 0x0002
  256. /* PLA_WDT6_CTRL */
  257. #define WDT6_SET_MODE 0x0010
  258. /* PLA_TCR0 */
  259. #define TCR0_TX_EMPTY 0x0800
  260. #define TCR0_AUTO_FIFO 0x0080
  261. /* PLA_TCR1 */
  262. #define VERSION_MASK 0x7cf0
  263. #define IFG_MASK (BIT(3) | BIT(9) | BIT(8))
  264. #define IFG_144NS BIT(9)
  265. #define IFG_96NS (BIT(9) | BIT(8))
  266. /* PLA_MTPS */
  267. #define MTPS_JUMBO (12 * 1024 / 64)
  268. #define MTPS_DEFAULT (6 * 1024 / 64)
  269. /* PLA_RSTTALLY */
  270. #define TALLY_RESET 0x0001
  271. /* PLA_CR */
  272. #define CR_RST 0x10
  273. #define CR_RE 0x08
  274. #define CR_TE 0x04
  275. /* PLA_CRWECR */
  276. #define CRWECR_NORAML 0x00
  277. #define CRWECR_CONFIG 0xc0
  278. /* PLA_OOB_CTRL */
  279. #define NOW_IS_OOB 0x80
  280. #define TXFIFO_EMPTY 0x20
  281. #define RXFIFO_EMPTY 0x10
  282. #define LINK_LIST_READY 0x02
  283. #define DIS_MCU_CLROOB 0x01
  284. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  285. /* PLA_MISC_1 */
  286. #define RXDY_GATED_EN 0x0008
  287. /* PLA_SFF_STS_7 */
  288. #define RE_INIT_LL 0x8000
  289. #define MCU_BORW_EN 0x4000
  290. /* PLA_CPCR */
  291. #define FLOW_CTRL_EN BIT(0)
  292. #define CPCR_RX_VLAN 0x0040
  293. /* PLA_CFG_WOL */
  294. #define MAGIC_EN 0x0001
  295. /* PLA_TEREDO_CFG */
  296. #define TEREDO_SEL 0x8000
  297. #define TEREDO_WAKE_MASK 0x7f00
  298. #define TEREDO_RS_EVENT_MASK 0x00fe
  299. #define OOB_TEREDO_EN 0x0001
  300. /* PLA_BDC_CR */
  301. #define ALDPS_PROXY_MODE 0x0001
  302. /* PLA_EFUSE_CMD */
  303. #define EFUSE_READ_CMD BIT(15)
  304. #define EFUSE_DATA_BIT16 BIT(7)
  305. /* PLA_CONFIG34 */
  306. #define LINK_ON_WAKE_EN 0x0010
  307. #define LINK_OFF_WAKE_EN 0x0008
  308. /* PLA_CONFIG6 */
  309. #define LANWAKE_CLR_EN BIT(0)
  310. /* PLA_USB_CFG */
  311. #define EN_XG_LIP BIT(1)
  312. #define EN_G_LIP BIT(2)
  313. /* PLA_CONFIG5 */
  314. #define BWF_EN 0x0040
  315. #define MWF_EN 0x0020
  316. #define UWF_EN 0x0010
  317. #define LAN_WAKE_EN 0x0002
  318. /* PLA_LED_FEATURE */
  319. #define LED_MODE_MASK 0x0700
  320. /* PLA_PHY_PWR */
  321. #define TX_10M_IDLE_EN 0x0080
  322. #define PFM_PWM_SWITCH 0x0040
  323. #define TEST_IO_OFF BIT(4)
  324. /* PLA_MAC_PWR_CTRL */
  325. #define D3_CLK_GATED_EN 0x00004000
  326. #define MCU_CLK_RATIO 0x07010f07
  327. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  328. #define ALDPS_SPDWN_RATIO 0x0f87
  329. /* PLA_MAC_PWR_CTRL2 */
  330. #define EEE_SPDWN_RATIO 0x8007
  331. #define MAC_CLK_SPDWN_EN BIT(15)
  332. #define EEE_SPDWN_RATIO_MASK 0xff
  333. /* PLA_MAC_PWR_CTRL3 */
  334. #define PLA_MCU_SPDWN_EN BIT(14)
  335. #define PKT_AVAIL_SPDWN_EN 0x0100
  336. #define SUSPEND_SPDWN_EN 0x0004
  337. #define U1U2_SPDWN_EN 0x0002
  338. #define L1_SPDWN_EN 0x0001
  339. /* PLA_MAC_PWR_CTRL4 */
  340. #define PWRSAVE_SPDWN_EN 0x1000
  341. #define RXDV_SPDWN_EN 0x0800
  342. #define TX10MIDLE_EN 0x0100
  343. #define IDLE_SPDWN_EN BIT(6)
  344. #define TP100_SPDWN_EN 0x0020
  345. #define TP500_SPDWN_EN 0x0010
  346. #define TP1000_SPDWN_EN 0x0008
  347. #define EEE_SPDWN_EN 0x0001
  348. /* PLA_GPHY_INTR_IMR */
  349. #define GPHY_STS_MSK 0x0001
  350. #define SPEED_DOWN_MSK 0x0002
  351. #define SPDWN_RXDV_MSK 0x0004
  352. #define SPDWN_LINKCHG_MSK 0x0008
  353. /* PLA_PHYAR */
  354. #define PHYAR_FLAG 0x80000000
  355. /* PLA_EEE_CR */
  356. #define EEE_RX_EN 0x0001
  357. #define EEE_TX_EN 0x0002
  358. /* PLA_BOOT_CTRL */
  359. #define AUTOLOAD_DONE 0x0002
  360. /* PLA_LWAKE_CTRL_REG */
  361. #define LANWAKE_PIN BIT(7)
  362. /* PLA_SUSPEND_FLAG */
  363. #define LINK_CHG_EVENT BIT(0)
  364. /* PLA_INDICATE_FALG */
  365. #define UPCOMING_RUNTIME_D3 BIT(0)
  366. /* PLA_MACDBG_PRE and PLA_MACDBG_POST */
  367. #define DEBUG_OE BIT(0)
  368. #define DEBUG_LTSSM 0x0082
  369. /* PLA_EXTRA_STATUS */
  370. #define CUR_LINK_OK BIT(15)
  371. #define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */
  372. #define LINK_CHANGE_FLAG BIT(8)
  373. #define POLL_LINK_CHG BIT(0)
  374. /* PLA_GPHY_CTRL */
  375. #define GPHY_FLASH BIT(1)
  376. /* PLA_POL_GPIO_CTRL */
  377. #define DACK_DET_EN BIT(15)
  378. #define POL_GPHY_PATCH BIT(4)
  379. /* USB_USB2PHY */
  380. #define USB2PHY_SUSPEND 0x0001
  381. #define USB2PHY_L1 0x0002
  382. /* USB_SSPHYLINK1 */
  383. #define DELAY_PHY_PWR_CHG BIT(1)
  384. /* USB_SSPHYLINK2 */
  385. #define pwd_dn_scale_mask 0x3ffe
  386. #define pwd_dn_scale(x) ((x) << 1)
  387. /* USB_CSR_DUMMY1 */
  388. #define DYNAMIC_BURST 0x0001
  389. /* USB_CSR_DUMMY2 */
  390. #define EP4_FULL_FC 0x0001
  391. /* USB_DEV_STAT */
  392. #define STAT_SPEED_MASK 0x0006
  393. #define STAT_SPEED_HIGH 0x0000
  394. #define STAT_SPEED_FULL 0x0002
  395. /* USB_FW_FIX_EN0 */
  396. #define FW_FIX_SUSPEND BIT(14)
  397. /* USB_FW_FIX_EN1 */
  398. #define FW_IP_RESET_EN BIT(9)
  399. /* USB_LPM_CONFIG */
  400. #define LPM_U1U2_EN BIT(0)
  401. /* USB_TX_AGG */
  402. #define TX_AGG_MAX_THRESHOLD 0x03
  403. /* USB_RX_BUF_TH */
  404. #define RX_THR_SUPPER 0x0c350180
  405. #define RX_THR_HIGH 0x7a120180
  406. #define RX_THR_SLOW 0xffff0180
  407. #define RX_THR_B 0x00010001
  408. /* USB_TX_DMA */
  409. #define TEST_MODE_DISABLE 0x00000001
  410. #define TX_SIZE_ADJUST1 0x00000100
  411. /* USB_BMU_RESET */
  412. #define BMU_RESET_EP_IN 0x01
  413. #define BMU_RESET_EP_OUT 0x02
  414. /* USB_BMU_CONFIG */
  415. #define ACT_ODMA BIT(1)
  416. /* USB_UPT_RXDMA_OWN */
  417. #define OWN_UPDATE BIT(0)
  418. #define OWN_CLEAR BIT(1)
  419. /* USB_FW_TASK */
  420. #define FC_PATCH_TASK BIT(1)
  421. /* USB_RX_AGGR_NUM */
  422. #define RX_AGGR_NUM_MASK 0x1ff
  423. /* USB_UPS_CTRL */
  424. #define POWER_CUT 0x0100
  425. /* USB_PM_CTRL_STATUS */
  426. #define RESUME_INDICATE 0x0001
  427. /* USB_ECM_OPTION */
  428. #define BYPASS_MAC_RESET BIT(5)
  429. /* USB_CSTMR */
  430. #define FORCE_SUPER BIT(0)
  431. /* USB_MISC_2 */
  432. #define UPS_FORCE_PWR_DOWN BIT(0)
  433. /* USB_ECM_OP */
  434. #define EN_ALL_SPEED BIT(0)
  435. /* USB_GPHY_CTRL */
  436. #define GPHY_PATCH_DONE BIT(2)
  437. #define BYPASS_FLASH BIT(5)
  438. #define BACKUP_RESTRORE BIT(6)
  439. /* USB_SPEED_OPTION */
  440. #define RG_PWRDN_EN BIT(8)
  441. #define ALL_SPEED_OFF BIT(9)
  442. /* USB_FW_CTRL */
  443. #define FLOW_CTRL_PATCH_OPT BIT(1)
  444. #define AUTO_SPEEDUP BIT(3)
  445. #define FLOW_CTRL_PATCH_2 BIT(8)
  446. /* USB_FC_TIMER */
  447. #define CTRL_TIMER_EN BIT(15)
  448. /* USB_USB_CTRL */
  449. #define CDC_ECM_EN BIT(3)
  450. #define RX_AGG_DISABLE 0x0010
  451. #define RX_ZERO_EN 0x0080
  452. /* USB_U2P3_CTRL */
  453. #define U2P3_ENABLE 0x0001
  454. #define RX_DETECT8 BIT(3)
  455. /* USB_POWER_CUT */
  456. #define PWR_EN 0x0001
  457. #define PHASE2_EN 0x0008
  458. #define UPS_EN BIT(4)
  459. #define USP_PREWAKE BIT(5)
  460. /* USB_MISC_0 */
  461. #define PCUT_STATUS 0x0001
  462. /* USB_RX_EARLY_TIMEOUT */
  463. #define COALESCE_SUPER 85000U
  464. #define COALESCE_HIGH 250000U
  465. #define COALESCE_SLOW 524280U
  466. /* USB_WDT1_CTRL */
  467. #define WTD1_EN BIT(0)
  468. /* USB_WDT11_CTRL */
  469. #define TIMER11_EN 0x0001
  470. /* USB_LPM_CTRL */
  471. /* bit 4 ~ 5: fifo empty boundary */
  472. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  473. /* bit 2 ~ 3: LMP timer */
  474. #define LPM_TIMER_MASK 0x0c
  475. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  476. #define LPM_TIMER_500US 0x0c /* 500 us */
  477. #define ROK_EXIT_LPM 0x02
  478. /* USB_AFE_CTRL2 */
  479. #define SEN_VAL_MASK 0xf800
  480. #define SEN_VAL_NORMAL 0xa000
  481. #define SEL_RXIDLE 0x0100
  482. /* USB_UPHY_XTAL */
  483. #define OOBS_POLLING BIT(8)
  484. /* USB_UPS_CFG */
  485. #define SAW_CNT_1MS_MASK 0x0fff
  486. #define MID_REVERSE BIT(5) /* RTL8156A */
  487. /* USB_UPS_FLAGS */
  488. #define UPS_FLAGS_R_TUNE BIT(0)
  489. #define UPS_FLAGS_EN_10M_CKDIV BIT(1)
  490. #define UPS_FLAGS_250M_CKDIV BIT(2)
  491. #define UPS_FLAGS_EN_ALDPS BIT(3)
  492. #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
  493. #define UPS_FLAGS_SPEED_MASK (0xf << 16)
  494. #define ups_flags_speed(x) ((x) << 16)
  495. #define UPS_FLAGS_EN_EEE BIT(20)
  496. #define UPS_FLAGS_EN_500M_EEE BIT(21)
  497. #define UPS_FLAGS_EN_EEE_CKDIV BIT(22)
  498. #define UPS_FLAGS_EEE_PLLOFF_100 BIT(23)
  499. #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24)
  500. #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25)
  501. #define UPS_FLAGS_EN_GREEN BIT(26)
  502. #define UPS_FLAGS_EN_FLOW_CTR BIT(27)
  503. enum spd_duplex {
  504. NWAY_10M_HALF,
  505. NWAY_10M_FULL,
  506. NWAY_100M_HALF,
  507. NWAY_100M_FULL,
  508. NWAY_1000M_FULL,
  509. FORCE_10M_HALF,
  510. FORCE_10M_FULL,
  511. FORCE_100M_HALF,
  512. FORCE_100M_FULL,
  513. FORCE_1000M_FULL,
  514. NWAY_2500M_FULL,
  515. };
  516. /* OCP_ALDPS_CONFIG */
  517. #define ENPWRSAVE 0x8000
  518. #define ENPDNPS 0x0200
  519. #define LINKENA 0x0100
  520. #define DIS_SDSAVE 0x0010
  521. /* OCP_PHY_STATUS */
  522. #define PHY_STAT_MASK 0x0007
  523. #define PHY_STAT_EXT_INIT 2
  524. #define PHY_STAT_LAN_ON 3
  525. #define PHY_STAT_PWRDN 5
  526. /* OCP_INTR_EN */
  527. #define INTR_SPEED_FORCE BIT(3)
  528. /* OCP_NCTL_CFG */
  529. #define PGA_RETURN_EN BIT(1)
  530. /* OCP_POWER_CFG */
  531. #define EEE_CLKDIV_EN 0x8000
  532. #define EN_ALDPS 0x0004
  533. #define EN_10M_PLLOFF 0x0001
  534. /* OCP_EEE_CONFIG1 */
  535. #define RG_TXLPI_MSK_HFDUP 0x8000
  536. #define RG_MATCLR_EN 0x4000
  537. #define EEE_10_CAP 0x2000
  538. #define EEE_NWAY_EN 0x1000
  539. #define TX_QUIET_EN 0x0200
  540. #define RX_QUIET_EN 0x0100
  541. #define sd_rise_time_mask 0x0070
  542. #define sd_rise_time(x) (MIN(x, 7) << 4) /* bit 4 ~ 6 */
  543. #define RG_RXLPI_MSK_HFDUP 0x0008
  544. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  545. /* OCP_EEE_CONFIG2 */
  546. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  547. #define RG_DACQUIET_EN 0x0400
  548. #define RG_LDVQUIET_EN 0x0200
  549. #define RG_CKRSEL 0x0020
  550. #define RG_EEEPRG_EN 0x0010
  551. /* OCP_EEE_CONFIG3 */
  552. #define fast_snr_mask 0xff80
  553. #define fast_snr(x) (MIN(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  554. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  555. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  556. /* OCP_EEE_AR */
  557. /* bit[15:14] function */
  558. #define FUN_ADDR 0x0000
  559. #define FUN_DATA 0x4000
  560. /* bit[4:0] device addr */
  561. /* OCP_EEE_CFG */
  562. #define CTAP_SHORT_EN 0x0040
  563. #define EEE10_EN 0x0010
  564. /* OCP_DOWN_SPEED */
  565. #define EN_EEE_CMODE BIT(14)
  566. #define EN_EEE_1000 BIT(13)
  567. #define EN_EEE_100 BIT(12)
  568. #define EN_10M_CLKDIV BIT(11)
  569. #define EN_10M_BGOFF 0x0080
  570. /* OCP_10GBT_CTRL */
  571. #define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
  572. /* OCP_PHY_STATE */
  573. #define TXDIS_STATE 0x01
  574. #define ABD_STATE 0x02
  575. /* OCP_PHY_PATCH_STAT */
  576. #define PATCH_READY BIT(6)
  577. /* OCP_PHY_PATCH_CMD */
  578. #define PATCH_REQUEST BIT(4)
  579. /* OCP_PHY_LOCK */
  580. #define PATCH_LOCK BIT(0)
  581. /* OCP_ADC_CFG */
  582. #define CKADSEL_L 0x0100
  583. #define ADC_EN 0x0080
  584. #define EN_EMI_L 0x0040
  585. /* OCP_SYSCLK_CFG */
  586. #define sysclk_div_expo(x) (MIN(x, 5) << 8)
  587. #define clk_div_expo(x) (MIN(x, 5) << 4)
  588. /* SRAM_GREEN_CFG */
  589. #define GREEN_ETH_EN BIT(15)
  590. #define R_TUNE_EN BIT(11)
  591. /* SRAM_LPF_CFG */
  592. #define LPF_AUTO_TUNE 0x8000
  593. /* SRAM_10M_AMP1 */
  594. #define GDAC_IB_UPALL 0x0008
  595. /* SRAM_10M_AMP2 */
  596. #define AMP_DN 0x0200
  597. /* SRAM_IMPEDANCE */
  598. #define RX_DRIVING_MASK 0x6000
  599. /* SRAM_PHY_LOCK */
  600. #define PHY_PATCH_LOCK 0x0001
  601. /* MAC PASSTHRU */
  602. #define AD_MASK 0xfee0
  603. #define BND_MASK 0x0004
  604. #define BD_MASK 0x0001
  605. #define EFUSE 0xcfdb
  606. #define PASS_THRU_MASK 0x1
  607. #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
  608. enum rtl_register_content {
  609. _2500bps = BIT(10),
  610. _1250bps = BIT(9),
  611. _500bps = BIT(8),
  612. _tx_flow = BIT(6),
  613. _rx_flow = BIT(5),
  614. _1000bps = 0x10,
  615. _100bps = 0x08,
  616. _10bps = 0x04,
  617. LINK_STATUS = 0x02,
  618. FULL_DUP = 0x01,
  619. };
  620. #define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
  621. #define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
  622. #define RTL8152_MAX_TX 4
  623. #define RTL8152_MAX_RX 10
  624. #define INTBUFSIZE 2
  625. #define TX_ALIGN 4
  626. #define RX_ALIGN 8
  627. #define RTL8152_RX_MAX_PENDING 4096
  628. #define RTL8152_RXFG_HEADSZ 256
  629. #define INTR_LINK 0x0004
  630. #define VLAN_ETH_HLEN 18
  631. #define ETH_FCS_LEN 4
  632. #define VLAN_ETH_FRAME_LEN 1514
  633. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
  634. #define RTL8153_RMS RTL8153_MAX_PACKET
  635. #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
  636. #define size_to_mtu(s) ((s)-VLAN_ETH_HLEN - ETH_FCS_LEN)
  637. #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
  638. struct rx_desc {
  639. uint32_t opts1;
  640. #define RD_CRC BIT(15)
  641. #define RX_LEN_MASK 0x7fff
  642. uint32_t opts2;
  643. #define RD_UDP_CS BIT(23)
  644. #define RD_TCP_CS BIT(22)
  645. #define RD_IPV6_CS BIT(20)
  646. #define RD_IPV4_CS BIT(19)
  647. uint32_t opts3;
  648. #define IPF BIT(23) /* IP checksum fail */
  649. #define UDPF BIT(22) /* UDP checksum fail */
  650. #define TCPF BIT(21) /* TCP checksum fail */
  651. #define RX_VLAN_TAG BIT(16)
  652. uint32_t opts4;
  653. uint32_t opts5;
  654. uint32_t opts6;
  655. };
  656. struct tx_desc {
  657. uint32_t opts1;
  658. #define TX_FS BIT(31) /* First segment of a packet */
  659. #define TX_LS BIT(30) /* Final segment of a packet */
  660. #define LGSEND BIT(29)
  661. #define GTSENDV4 BIT(28)
  662. #define GTSENDV6 BIT(27)
  663. #define GTTCPHO_SHIFT 18
  664. #define GTTCPHO_MAX 0x7fU
  665. #define TX_LEN_MAX 0x3ffffU
  666. uint32_t opts2;
  667. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  668. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  669. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  670. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  671. #define MSS_SHIFT 17
  672. #define MSS_MAX 0x7ffU
  673. #define TCPHO_SHIFT 17
  674. #define TCPHO_MAX 0x7ffU
  675. #define TX_VLAN_TAG BIT(16)
  676. };
  677. enum rtl_version {
  678. RTL_VER_UNKNOWN = 0,
  679. RTL_VER_01,
  680. RTL_VER_02,
  681. RTL_VER_03,
  682. RTL_VER_04,
  683. RTL_VER_05,
  684. RTL_VER_06,
  685. RTL_VER_07,
  686. RTL_VER_08,
  687. RTL_VER_09,
  688. RTL_TEST_01,
  689. RTL_VER_10,
  690. RTL_VER_11,
  691. RTL_VER_12,
  692. RTL_VER_13,
  693. RTL_VER_14,
  694. RTL_VER_15,
  695. RTL_VER_MAX
  696. };
  697. /* mii.h */
  698. /* Generic MII registers. */
  699. #define MII_BMCR 0x00 /* Basic mode control register */
  700. #define MII_BMSR 0x01 /* Basic mode status register */
  701. #define MII_PHYSID1 0x02 /* PHYS ID 1 */
  702. #define MII_PHYSID2 0x03 /* PHYS ID 2 */
  703. #define MII_ADVERTISE 0x04 /* Advertisement control reg */
  704. #define MII_LPA 0x05 /* Link partner ability reg */
  705. #define MII_EXPANSION 0x06 /* Expansion register */
  706. #define MII_CTRL1000 0x09 /* 1000BASE-T control */
  707. #define MII_STAT1000 0x0a /* 1000BASE-T status */
  708. #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */
  709. #define MII_MMD_DATA 0x0e /* MMD Access Data Register */
  710. #define MII_ESTATUS 0x0f /* Extended Status */
  711. #define MII_DCOUNTER 0x12 /* Disconnect counter */
  712. #define MII_FCSCOUNTER 0x13 /* False carrier counter */
  713. #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
  714. #define MII_RERRCOUNTER 0x15 /* Receive error counter */
  715. #define MII_SREVISION 0x16 /* Silicon revision */
  716. #define MII_RESV1 0x17 /* Reserved... */
  717. #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
  718. #define MII_PHYADDR 0x19 /* PHY address */
  719. #define MII_RESV2 0x1a /* Reserved... */
  720. #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
  721. #define MII_NCONFIG 0x1c /* Network interface config */
  722. /* Basic mode control register. */
  723. #define BMCR_RESV 0x003f /* Unused... */
  724. #define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
  725. #define BMCR_CTST 0x0080 /* Collision test */
  726. #define BMCR_FULLDPLX 0x0100 /* Full duplex */
  727. #define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
  728. #define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */
  729. #define BMCR_PDOWN 0x0800 /* Enable low power state */
  730. #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
  731. #define BMCR_SPEED100 0x2000 /* Select 100Mbps */
  732. #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
  733. #define BMCR_RESET 0x8000 /* Reset to default state */
  734. #define BMCR_SPEED10 0x0000 /* Select 10Mbps */
  735. /* Basic mode status register. */
  736. #define BMSR_ERCAP 0x0001 /* Ext-reg capability */
  737. #define BMSR_JCD 0x0002 /* Jabber detected */
  738. #define BMSR_LSTATUS 0x0004 /* Link status */
  739. #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
  740. #define BMSR_RFAULT 0x0010 /* Remote fault detected */
  741. #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
  742. #define BMSR_RESV 0x00c0 /* Unused... */
  743. #define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
  744. #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
  745. #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
  746. #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
  747. #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
  748. #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
  749. #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
  750. #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
  751. /* Advertisement control register. */
  752. #define ADVERTISE_SLCT 0x001f /* Selector bits */
  753. #define ADVERTISE_CSMA 0x0001 /* Only selector supported */
  754. #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
  755. #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
  756. #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
  757. #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
  758. #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
  759. #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
  760. #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
  761. #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
  762. #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
  763. #define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
  764. #define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
  765. #define ADVERTISE_RESV 0x1000 /* Unused... */
  766. #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
  767. #define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
  768. #define ADVERTISE_NPAGE 0x8000 /* Next page bit */
  769. #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
  770. ADVERTISE_CSMA)
  771. #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  772. ADVERTISE_100HALF | ADVERTISE_100FULL)
  773. /* 1000BASE-T Control register */
  774. #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
  775. #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
  776. #define CTL1000_AS_MASTER 0x0800
  777. #define CTL1000_ENABLE_MASTER 0x1000
  778. /* ethtool.h */
  779. /* The forced speed, 10Mb, 100Mb, gigabit. */
  780. #define SPEED_10 10
  781. #define SPEED_100 100
  782. #define SPEED_1000 1000
  783. #define SPEED_UNKNOWN -1
  784. /* Duplex, half or full. */
  785. #define DUPLEX_HALF 0x00
  786. #define DUPLEX_FULL 0x01
  787. #define DUPLEX_UNKNOWN 0xff
  788. /* Enable or disable autonegotiation. */
  789. #define AUTONEG_DISABLE 0x00
  790. #define AUTONEG_ENABLE 0x01
  791. static int usbh_rtl8152_read_regs(struct usbh_rtl8152 *rtl8152_class,
  792. uint16_t value,
  793. uint16_t index,
  794. uint16_t size,
  795. void *data)
  796. {
  797. struct usb_setup_packet *setup;
  798. int ret;
  799. if (!rtl8152_class || !rtl8152_class->hport) {
  800. return -USB_ERR_INVAL;
  801. }
  802. setup = rtl8152_class->hport->setup;
  803. setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE;
  804. setup->bRequest = RTL8152_REQ_GET_REGS;
  805. setup->wValue = value;
  806. setup->wIndex = index;
  807. setup->wLength = size;
  808. ret = usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf);
  809. if (ret < 8) {
  810. return ret;
  811. }
  812. memcpy(data, g_rtl8152_buf, ret - 8);
  813. return ret;
  814. }
  815. static int usbh_rtl8152_write_regs(struct usbh_rtl8152 *rtl8152_class,
  816. uint16_t value,
  817. uint16_t index,
  818. uint16_t size,
  819. void *data)
  820. {
  821. struct usb_setup_packet *setup;
  822. if (!rtl8152_class || !rtl8152_class->hport) {
  823. return -USB_ERR_INVAL;
  824. }
  825. setup = rtl8152_class->hport->setup;
  826. setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE;
  827. setup->bRequest = RTL8152_REQ_SET_REGS;
  828. setup->wValue = value;
  829. setup->wIndex = index;
  830. setup->wLength = size;
  831. memcpy(g_rtl8152_buf, data, size);
  832. return usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf);
  833. }
  834. static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size,
  835. void *data, uint16_t type)
  836. {
  837. uint16_t limit = 64;
  838. int ret = 0;
  839. uint8_t *buf = data;
  840. /* both size and indix must be 4 bytes align */
  841. if ((size & 3) || !size || (index & 3) || !buf)
  842. return -USB_ERR_INVAL;
  843. if ((uint32_t)index + (uint32_t)size > 0xffff)
  844. return -USB_ERR_INVAL;
  845. while (size) {
  846. if (size > limit) {
  847. ret = usbh_rtl8152_read_regs(tp, index, type, limit, buf);
  848. if (ret < 0)
  849. break;
  850. index += limit;
  851. buf += limit;
  852. size -= limit;
  853. } else {
  854. ret = usbh_rtl8152_read_regs(tp, index, type, size, buf);
  855. if (ret < 0)
  856. break;
  857. index += size;
  858. buf += size;
  859. size = 0;
  860. break;
  861. }
  862. }
  863. return ret;
  864. }
  865. static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen,
  866. uint16_t size, void *data, uint16_t type)
  867. {
  868. int ret;
  869. uint16_t byteen_start, byteen_end, byen;
  870. uint16_t limit = 512;
  871. uint8_t *buf = data;
  872. /* both size and indix must be 4 bytes align */
  873. if ((size & 3) || !size || (index & 3) || !buf)
  874. return -USB_ERR_INVAL;
  875. if ((uint32_t)index + (uint32_t)size > 0xffff)
  876. return -USB_ERR_INVAL;
  877. byteen_start = byteen & BYTE_EN_START_MASK;
  878. byteen_end = byteen & BYTE_EN_END_MASK;
  879. byen = byteen_start | (byteen_start << 4);
  880. /* Split the first DWORD if the byte_en is not 0xff */
  881. if (byen != BYTE_EN_DWORD) {
  882. ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf);
  883. if (ret < 0)
  884. goto error1;
  885. index += 4;
  886. buf += 4;
  887. size -= 4;
  888. }
  889. if (size) {
  890. byen = byteen_end | (byteen_end >> 4);
  891. /* Split the last DWORD if the byte_en is not 0xff */
  892. if (byen != BYTE_EN_DWORD)
  893. size -= 4;
  894. while (size) {
  895. if (size > limit) {
  896. ret = usbh_rtl8152_write_regs(tp, index,
  897. type | BYTE_EN_DWORD,
  898. limit, buf);
  899. if (ret < 0)
  900. goto error1;
  901. index += limit;
  902. buf += limit;
  903. size -= limit;
  904. } else {
  905. ret = usbh_rtl8152_write_regs(tp, index,
  906. type | BYTE_EN_DWORD,
  907. size, buf);
  908. if (ret < 0)
  909. goto error1;
  910. index += size;
  911. buf += size;
  912. size = 0;
  913. break;
  914. }
  915. }
  916. /* Set the last DWORD */
  917. if (byen != BYTE_EN_DWORD)
  918. ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, buf);
  919. }
  920. error1:
  921. return ret;
  922. }
  923. static inline int pla_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size, void *data)
  924. {
  925. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  926. }
  927. static inline int pla_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data)
  928. {
  929. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  930. }
  931. static inline int usb_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data)
  932. {
  933. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  934. }
  935. static uint32_t ocp_read_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index)
  936. {
  937. uint32_t data;
  938. generic_ocp_read(tp, index, sizeof(data), &data, type);
  939. return data;
  940. }
  941. static void ocp_write_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data)
  942. {
  943. uint32_t tmp = data;
  944. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  945. }
  946. static uint16_t ocp_read_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index)
  947. {
  948. uint32_t data;
  949. uint32_t tmp;
  950. uint16_t byen = BYTE_EN_WORD;
  951. uint8_t shift = index & 2;
  952. index &= ~3;
  953. byen <<= shift;
  954. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
  955. data = tmp;
  956. data >>= (shift * 8);
  957. data &= 0xffff;
  958. return (uint16_t)data;
  959. }
  960. static void ocp_write_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data)
  961. {
  962. uint32_t mask = 0xffff;
  963. uint32_t tmp;
  964. uint16_t byen = BYTE_EN_WORD;
  965. uint8_t shift = index & 2;
  966. data &= mask;
  967. if (index & 2) {
  968. byen <<= shift;
  969. mask <<= (shift * 8);
  970. data <<= (shift * 8);
  971. index &= ~3;
  972. }
  973. tmp = data;
  974. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  975. }
  976. static uint8_t ocp_read_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index)
  977. {
  978. uint32_t data;
  979. uint32_t tmp;
  980. uint8_t shift = index & 3;
  981. index &= ~3;
  982. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  983. data = tmp;
  984. data >>= (shift * 8);
  985. data &= 0xff;
  986. return (uint8_t)data;
  987. }
  988. static void ocp_write_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data)
  989. {
  990. uint32_t mask = 0xff;
  991. uint32_t tmp;
  992. uint16_t byen = BYTE_EN_BYTE;
  993. uint8_t shift = index & 3;
  994. data &= mask;
  995. if (index & 3) {
  996. byen <<= shift;
  997. mask <<= (shift * 8);
  998. data <<= (shift * 8);
  999. index &= ~3;
  1000. }
  1001. tmp = data;
  1002. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  1003. }
  1004. static uint16_t ocp_reg_read(struct usbh_rtl8152 *tp, uint16_t addr)
  1005. {
  1006. uint16_t ocp_base, ocp_index;
  1007. ocp_base = addr & 0xf000;
  1008. if (ocp_base != tp->ocp_base) {
  1009. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  1010. tp->ocp_base = ocp_base;
  1011. }
  1012. ocp_index = (addr & 0x0fff) | 0xb000;
  1013. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  1014. }
  1015. static void ocp_reg_write(struct usbh_rtl8152 *tp, uint16_t addr, uint16_t data)
  1016. {
  1017. uint16_t ocp_base, ocp_index;
  1018. ocp_base = addr & 0xf000;
  1019. if (ocp_base != tp->ocp_base) {
  1020. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  1021. tp->ocp_base = ocp_base;
  1022. }
  1023. ocp_index = (addr & 0x0fff) | 0xb000;
  1024. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  1025. }
  1026. static inline void r8152_mdio_write(struct usbh_rtl8152 *tp, uint32_t reg_addr, uint32_t value)
  1027. {
  1028. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  1029. }
  1030. static inline int r8152_mdio_read(struct usbh_rtl8152 *tp, uint32_t reg_addr)
  1031. {
  1032. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  1033. }
  1034. static uint8_t usbh_rtl8152_get_version(struct usbh_rtl8152 *rtl8152_class)
  1035. {
  1036. uint8_t version;
  1037. uint32_t temp;
  1038. uint32_t ocp_data;
  1039. usbh_rtl8152_read_regs(rtl8152_class, PLA_TCR0, MCU_TYPE_PLA, 4, &temp);
  1040. ocp_data = (temp >> 16) & VERSION_MASK;
  1041. switch (ocp_data) {
  1042. case 0x4c00:
  1043. version = RTL_VER_01;
  1044. break;
  1045. case 0x4c10:
  1046. version = RTL_VER_02;
  1047. break;
  1048. case 0x5c00:
  1049. version = RTL_VER_03;
  1050. break;
  1051. case 0x5c10:
  1052. version = RTL_VER_04;
  1053. break;
  1054. case 0x5c20:
  1055. version = RTL_VER_05;
  1056. break;
  1057. case 0x5c30:
  1058. version = RTL_VER_06;
  1059. break;
  1060. case 0x4800:
  1061. version = RTL_VER_07;
  1062. break;
  1063. case 0x6000:
  1064. version = RTL_VER_08;
  1065. break;
  1066. case 0x6010:
  1067. version = RTL_VER_09;
  1068. break;
  1069. case 0x7010:
  1070. version = RTL_TEST_01;
  1071. break;
  1072. case 0x7020:
  1073. version = RTL_VER_10;
  1074. break;
  1075. case 0x7030:
  1076. version = RTL_VER_11;
  1077. break;
  1078. case 0x7400:
  1079. version = RTL_VER_12;
  1080. break;
  1081. case 0x7410:
  1082. version = RTL_VER_13;
  1083. break;
  1084. case 0x6400:
  1085. version = RTL_VER_14;
  1086. break;
  1087. case 0x7420:
  1088. version = RTL_VER_15;
  1089. break;
  1090. default:
  1091. version = RTL_VER_UNKNOWN;
  1092. break;
  1093. }
  1094. return version;
  1095. }
  1096. #define WAKE_PHY (1 << 0)
  1097. #define WAKE_UCAST (1 << 1)
  1098. #define WAKE_MCAST (1 << 2)
  1099. #define WAKE_BCAST (1 << 3)
  1100. #define WAKE_ARP (1 << 4)
  1101. #define WAKE_MAGIC (1 << 5)
  1102. #define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */
  1103. #define WAKE_FILTER (1 << 7)
  1104. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1105. static uint32_t __rtl_get_wol(struct usbh_rtl8152 *tp)
  1106. {
  1107. uint32_t ocp_data;
  1108. uint32_t wolopts = 0;
  1109. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1110. if (ocp_data & LINK_ON_WAKE_EN)
  1111. wolopts |= WAKE_PHY;
  1112. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1113. if (ocp_data & UWF_EN)
  1114. wolopts |= WAKE_UCAST;
  1115. if (ocp_data & BWF_EN)
  1116. wolopts |= WAKE_BCAST;
  1117. if (ocp_data & MWF_EN)
  1118. wolopts |= WAKE_MCAST;
  1119. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1120. if (ocp_data & MAGIC_EN)
  1121. wolopts |= WAKE_MAGIC;
  1122. return wolopts;
  1123. }
  1124. static void r8152_aldps_en(struct usbh_rtl8152 *tp, bool enable)
  1125. {
  1126. if (enable) {
  1127. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | LINKENA | DIS_SDSAVE);
  1128. } else {
  1129. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
  1130. usb_osal_msleep(20);
  1131. }
  1132. }
  1133. static void r8152_power_cut_en(struct usbh_rtl8152 *tp, bool enable)
  1134. {
  1135. uint32_t ocp_data;
  1136. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1137. if (enable)
  1138. ocp_data |= POWER_CUT;
  1139. else
  1140. ocp_data &= ~POWER_CUT;
  1141. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1142. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1143. ocp_data &= ~RESUME_INDICATE;
  1144. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1145. }
  1146. static void rtl_tally_reset(struct usbh_rtl8152 *tp)
  1147. {
  1148. uint32_t ocp_data;
  1149. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  1150. ocp_data |= TALLY_RESET;
  1151. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  1152. }
  1153. static void r8152b_reset_packet_filter(struct usbh_rtl8152 *tp)
  1154. {
  1155. uint32_t ocp_data;
  1156. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1157. ocp_data &= ~FMC_FCR_MCU_EN;
  1158. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1159. ocp_data |= FMC_FCR_MCU_EN;
  1160. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1161. }
  1162. static inline void r8153b_rx_agg_chg_indicate(struct usbh_rtl8152 *tp)
  1163. {
  1164. ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
  1165. OWN_UPDATE | OWN_CLEAR);
  1166. }
  1167. static void rxdy_gated_en(struct usbh_rtl8152 *tp, bool enable)
  1168. {
  1169. uint32_t ocp_data;
  1170. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1171. if (enable)
  1172. ocp_data |= RXDY_GATED_EN;
  1173. else
  1174. ocp_data &= ~RXDY_GATED_EN;
  1175. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1176. }
  1177. static inline uint16_t rtl8152_get_speed(struct usbh_rtl8152 *tp)
  1178. {
  1179. return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1180. }
  1181. static void rtl_eee_plus_en(struct usbh_rtl8152 *tp, bool enable)
  1182. {
  1183. uint32_t ocp_data;
  1184. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1185. if (enable)
  1186. ocp_data |= EEEP_CR_EEEP_TX;
  1187. else
  1188. ocp_data &= ~EEEP_CR_EEEP_TX;
  1189. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1190. }
  1191. static void rtl_set_eee_plus(struct usbh_rtl8152 *tp)
  1192. {
  1193. if (rtl8152_get_speed(tp) & _10bps)
  1194. rtl_eee_plus_en(tp, true);
  1195. else
  1196. rtl_eee_plus_en(tp, false);
  1197. }
  1198. static void rtl8152_nic_reset(struct usbh_rtl8152 *tp)
  1199. {
  1200. uint32_t ocp_data;
  1201. int i;
  1202. switch (tp->version) {
  1203. case RTL_TEST_01:
  1204. case RTL_VER_10:
  1205. case RTL_VER_11:
  1206. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1207. ocp_data &= ~CR_TE;
  1208. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1209. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
  1210. ocp_data &= ~BMU_RESET_EP_IN;
  1211. ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  1212. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1213. ocp_data |= CDC_ECM_EN;
  1214. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1215. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1216. ocp_data &= ~CR_RE;
  1217. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1218. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
  1219. ocp_data |= BMU_RESET_EP_IN;
  1220. ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
  1221. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1222. ocp_data &= ~CDC_ECM_EN;
  1223. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1224. break;
  1225. default:
  1226. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1227. for (i = 0; i < 1000; i++) {
  1228. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1229. break;
  1230. usb_osal_msleep(400);
  1231. }
  1232. break;
  1233. }
  1234. }
  1235. static void rtl_disable(struct usbh_rtl8152 *tp)
  1236. {
  1237. uint32_t ocp_data;
  1238. int i;
  1239. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1240. ocp_data &= ~RCR_ACPT_ALL;
  1241. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1242. rxdy_gated_en(tp, true);
  1243. for (i = 0; i < 1000; i++) {
  1244. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1245. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1246. break;
  1247. usb_osal_msleep(1);
  1248. }
  1249. for (i = 0; i < 1000; i++) {
  1250. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1251. break;
  1252. usb_osal_msleep(1);
  1253. }
  1254. rtl8152_nic_reset(tp);
  1255. }
  1256. static void rtl_rx_vlan_en(struct usbh_rtl8152 *tp, bool enable)
  1257. {
  1258. uint32_t ocp_data;
  1259. switch (tp->version) {
  1260. case RTL_VER_01:
  1261. case RTL_VER_02:
  1262. case RTL_VER_03:
  1263. case RTL_VER_04:
  1264. case RTL_VER_05:
  1265. case RTL_VER_06:
  1266. case RTL_VER_07:
  1267. case RTL_VER_08:
  1268. case RTL_VER_09:
  1269. case RTL_VER_14:
  1270. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1271. if (enable)
  1272. ocp_data |= CPCR_RX_VLAN;
  1273. else
  1274. ocp_data &= ~CPCR_RX_VLAN;
  1275. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1276. break;
  1277. case RTL_TEST_01:
  1278. case RTL_VER_10:
  1279. case RTL_VER_11:
  1280. case RTL_VER_12:
  1281. case RTL_VER_13:
  1282. case RTL_VER_15:
  1283. default:
  1284. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
  1285. if (enable)
  1286. ocp_data |= OUTER_VLAN | INNER_VLAN;
  1287. else
  1288. ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
  1289. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
  1290. break;
  1291. }
  1292. }
  1293. static void wait_oob_link_list_ready(struct usbh_rtl8152 *tp)
  1294. {
  1295. uint32_t ocp_data;
  1296. int i;
  1297. for (i = 0; i < 1000; i++) {
  1298. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1299. if (ocp_data & LINK_LIST_READY)
  1300. break;
  1301. usb_osal_msleep(1);
  1302. }
  1303. }
  1304. static void r8153_teredo_off(struct usbh_rtl8152 *tp)
  1305. {
  1306. uint32_t ocp_data;
  1307. switch (tp->version) {
  1308. case RTL_VER_01:
  1309. case RTL_VER_02:
  1310. case RTL_VER_03:
  1311. case RTL_VER_04:
  1312. case RTL_VER_05:
  1313. case RTL_VER_06:
  1314. case RTL_VER_07:
  1315. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1316. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
  1317. OOB_TEREDO_EN);
  1318. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1319. break;
  1320. case RTL_VER_08:
  1321. case RTL_VER_09:
  1322. case RTL_TEST_01:
  1323. case RTL_VER_10:
  1324. case RTL_VER_11:
  1325. case RTL_VER_12:
  1326. case RTL_VER_13:
  1327. case RTL_VER_14:
  1328. case RTL_VER_15:
  1329. default:
  1330. /* The bit 0 ~ 7 are relative with teredo settings. They are
  1331. * W1C (write 1 to clear), so set all 1 to disable it.
  1332. */
  1333. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
  1334. break;
  1335. }
  1336. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1337. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1338. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1339. }
  1340. static void r8152b_exit_oob(struct usbh_rtl8152 *tp)
  1341. {
  1342. uint32_t ocp_data;
  1343. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1344. ocp_data &= ~RCR_ACPT_ALL;
  1345. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1346. rxdy_gated_en(tp, true);
  1347. r8153_teredo_off(tp);
  1348. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1349. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  1350. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1351. ocp_data &= ~NOW_IS_OOB;
  1352. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1353. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1354. ocp_data &= ~MCU_BORW_EN;
  1355. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1356. wait_oob_link_list_ready(tp);
  1357. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1358. ocp_data |= RE_INIT_LL;
  1359. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1360. wait_oob_link_list_ready(tp);
  1361. rtl8152_nic_reset(tp);
  1362. /* rx share fifo credit full threshold */
  1363. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  1364. if (tp->hport->speed == USB_SPEED_FULL ||
  1365. tp->hport->speed == USB_SPEED_LOW) {
  1366. /* rx share fifo credit near full threshold */
  1367. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1368. RXFIFO_THR2_FULL);
  1369. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1370. RXFIFO_THR3_FULL);
  1371. } else {
  1372. /* rx share fifo credit near full threshold */
  1373. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  1374. RXFIFO_THR2_HIGH);
  1375. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  1376. RXFIFO_THR3_HIGH);
  1377. }
  1378. /* TX share fifo free credit full threshold */
  1379. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  1380. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  1381. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  1382. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  1383. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  1384. rtl_rx_vlan_en(tp, true);
  1385. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1386. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  1387. ocp_data |= TCR0_AUTO_FIFO;
  1388. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  1389. }
  1390. static void r8152b_enter_oob(struct usbh_rtl8152 *tp)
  1391. {
  1392. uint32_t ocp_data;
  1393. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1394. ocp_data &= ~NOW_IS_OOB;
  1395. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1396. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  1397. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  1398. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  1399. rtl_disable(tp);
  1400. wait_oob_link_list_ready(tp);
  1401. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  1402. ocp_data |= RE_INIT_LL;
  1403. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  1404. wait_oob_link_list_ready(tp);
  1405. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  1406. rtl_rx_vlan_en(tp, true);
  1407. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR);
  1408. ocp_data |= ALDPS_PROXY_MODE;
  1409. ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data);
  1410. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1411. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  1412. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  1413. rxdy_gated_en(tp, false);
  1414. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1415. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  1416. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1417. }
  1418. static void r8152b_init(struct usbh_rtl8152 *tp)
  1419. {
  1420. uint32_t ocp_data;
  1421. uint16_t data;
  1422. data = r8152_mdio_read(tp, MII_BMCR);
  1423. if (data & BMCR_PDOWN) {
  1424. data &= ~BMCR_PDOWN;
  1425. r8152_mdio_write(tp, MII_BMCR, data);
  1426. }
  1427. r8152_aldps_en(tp, false);
  1428. if (tp->version == RTL_VER_01) {
  1429. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  1430. ocp_data &= ~LED_MODE_MASK;
  1431. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  1432. }
  1433. r8152_power_cut_en(tp, false);
  1434. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  1435. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  1436. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  1437. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  1438. ocp_data &= ~MCU_CLK_RATIO_MASK;
  1439. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  1440. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  1441. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  1442. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  1443. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  1444. rtl_tally_reset(tp);
  1445. /* enable rx aggregation */
  1446. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  1447. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  1448. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  1449. }
  1450. static int rtl_enable(struct usbh_rtl8152 *tp)
  1451. {
  1452. uint32_t ocp_data;
  1453. r8152b_reset_packet_filter(tp);
  1454. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1455. ocp_data |= CR_RE | CR_TE;
  1456. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1457. switch (tp->version) {
  1458. case RTL_VER_01:
  1459. case RTL_VER_02:
  1460. case RTL_VER_03:
  1461. case RTL_VER_04:
  1462. case RTL_VER_05:
  1463. case RTL_VER_06:
  1464. case RTL_VER_07:
  1465. break;
  1466. default:
  1467. r8153b_rx_agg_chg_indicate(tp);
  1468. break;
  1469. }
  1470. rxdy_gated_en(tp, false);
  1471. return 0;
  1472. }
  1473. static int rtl8152_enable(struct usbh_rtl8152 *tp)
  1474. {
  1475. rtl_set_eee_plus(tp);
  1476. return rtl_enable(tp);
  1477. }
  1478. static void rtl8152_disable(struct usbh_rtl8152 *tp)
  1479. {
  1480. r8152_aldps_en(tp, false);
  1481. rtl_disable(tp);
  1482. r8152_aldps_en(tp, true);
  1483. }
  1484. static void rtl8152_up(struct usbh_rtl8152 *tp)
  1485. {
  1486. r8152_aldps_en(tp, false);
  1487. r8152b_exit_oob(tp);
  1488. r8152_aldps_en(tp, true);
  1489. }
  1490. static void rtl8152_down(struct usbh_rtl8152 *tp)
  1491. {
  1492. r8152_power_cut_en(tp, false);
  1493. r8152_aldps_en(tp, false);
  1494. r8152b_enter_oob(tp);
  1495. r8152_aldps_en(tp, true);
  1496. }
  1497. static int rtl_ops_init(struct usbh_rtl8152 *tp)
  1498. {
  1499. struct rtl_ops *ops = &tp->rtl_ops;
  1500. int ret = 0;
  1501. switch (tp->version) {
  1502. case RTL_VER_01:
  1503. case RTL_VER_02:
  1504. case RTL_VER_07:
  1505. ops->init = r8152b_init;
  1506. ops->enable = rtl8152_enable;
  1507. ops->disable = rtl8152_disable;
  1508. ops->up = rtl8152_up;
  1509. ops->down = rtl8152_down;
  1510. // ops->unload = rtl8152_unload;
  1511. // ops->eee_get = r8152_get_eee;
  1512. // ops->eee_set = r8152_set_eee;
  1513. // ops->in_nway = rtl8152_in_nway;
  1514. // ops->hw_phy_cfg = r8152b_hw_phy_cfg;
  1515. // ops->autosuspend_en = rtl_runtime_suspend_enable;
  1516. tp->rx_buf_sz = 16 * 1024;
  1517. tp->eee_en = true;
  1518. //tp->eee_adv = MDIO_EEE_100TX;
  1519. break;
  1520. // case RTL_VER_03:
  1521. // case RTL_VER_04:
  1522. // case RTL_VER_05:
  1523. // case RTL_VER_06:
  1524. // break;
  1525. // case RTL_VER_08:
  1526. // case RTL_VER_09:
  1527. // break;
  1528. // case RTL_VER_11:
  1529. // case RTL_VER_10:
  1530. // break;
  1531. // case RTL_VER_12:
  1532. // case RTL_VER_13:
  1533. // case RTL_VER_15:
  1534. // break;
  1535. // case RTL_VER_14:
  1536. // break;
  1537. default:
  1538. ret = -USB_ERR_NODEV;
  1539. USB_LOG_ERR("Unsupport rtl version:%d\r\n", tp->version);
  1540. break;
  1541. }
  1542. return ret;
  1543. }
  1544. static void rtl8152_set_rx_mode(struct usbh_rtl8152 *tp)
  1545. {
  1546. uint32_t ocp_data;
  1547. uint32_t mc_filter[2];
  1548. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1549. ocp_data &= ~RCR_ACPT_ALL;
  1550. ocp_data |= RCR_AB | RCR_APM;
  1551. ocp_data |= RCR_AM;
  1552. mc_filter[1] = 0xffffffff;
  1553. mc_filter[0] = 0xffffffff;
  1554. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(mc_filter), mc_filter);
  1555. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1556. }
  1557. static int rtl8152_set_speed(struct usbh_rtl8152 *tp, uint8_t autoneg, uint16_t speed, uint8_t duplex)
  1558. {
  1559. uint16_t bmcr, anar, gbcr;
  1560. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  1561. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  1562. ADVERTISE_100HALF | ADVERTISE_100FULL);
  1563. if (tp->supports_gmii) {
  1564. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  1565. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  1566. } else {
  1567. gbcr = 0;
  1568. }
  1569. if (autoneg == AUTONEG_DISABLE) {
  1570. if (speed == SPEED_10) {
  1571. bmcr = 0;
  1572. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1573. } else if (speed == SPEED_100) {
  1574. bmcr = BMCR_SPEED100;
  1575. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1576. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  1577. bmcr = BMCR_SPEED1000;
  1578. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  1579. } else {
  1580. return -USB_ERR_INVAL;
  1581. }
  1582. if (duplex == DUPLEX_FULL)
  1583. bmcr |= BMCR_FULLDPLX;
  1584. } else {
  1585. if (speed == SPEED_10) {
  1586. if (duplex == DUPLEX_FULL)
  1587. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1588. else
  1589. anar |= ADVERTISE_10HALF;
  1590. } else if (speed == SPEED_100) {
  1591. if (duplex == DUPLEX_FULL) {
  1592. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1593. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1594. } else {
  1595. anar |= ADVERTISE_10HALF;
  1596. anar |= ADVERTISE_100HALF;
  1597. }
  1598. } else if (speed == SPEED_1000 && tp->supports_gmii) {
  1599. if (duplex == DUPLEX_FULL) {
  1600. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  1601. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  1602. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  1603. } else {
  1604. anar |= ADVERTISE_10HALF;
  1605. anar |= ADVERTISE_100HALF;
  1606. gbcr |= ADVERTISE_1000HALF;
  1607. }
  1608. } else {
  1609. return -USB_ERR_INVAL;
  1610. }
  1611. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1612. }
  1613. if (tp->supports_gmii)
  1614. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  1615. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  1616. r8152_mdio_write(tp, MII_BMCR, bmcr);
  1617. return 0;
  1618. }
  1619. int r8152_write_hwaddr(struct usbh_rtl8152 *tp, unsigned char *mac)
  1620. {
  1621. unsigned char enetaddr[8] = { 0 };
  1622. memcpy(enetaddr, mac, 6);
  1623. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1624. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
  1625. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1626. return 0;
  1627. }
  1628. int usbh_rtl8152_get_connect_status(struct usbh_rtl8152 *rtl8152_class)
  1629. {
  1630. int ret;
  1631. usbh_int_urb_fill(&rtl8152_class->intin_urb, rtl8152_class->hport, rtl8152_class->intin, g_rtl8152_inttx_buffer, 2, USB_OSAL_WAITING_FOREVER, NULL, NULL);
  1632. ret = usbh_submit_urb(&rtl8152_class->intin_urb);
  1633. if (ret < 0) {
  1634. return ret;
  1635. }
  1636. if (g_rtl8152_inttx_buffer[0] & INTR_LINK) {
  1637. rtl8152_class->connect_status = true;
  1638. } else {
  1639. rtl8152_class->connect_status = false;
  1640. }
  1641. return 0;
  1642. }
  1643. static int usbh_rtl8152_connect(struct usbh_hubport *hport, uint8_t intf)
  1644. {
  1645. struct usb_endpoint_descriptor *ep_desc;
  1646. char mac_buffer[12];
  1647. int ret;
  1648. struct usbh_rtl8152 *rtl8152_class = &g_rtl8152_class;
  1649. memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152));
  1650. rtl8152_class->hport = hport;
  1651. rtl8152_class->intf = intf;
  1652. hport->config.intf[intf].priv = rtl8152_class;
  1653. rtl8152_class->version = usbh_rtl8152_get_version(rtl8152_class);
  1654. if (rtl8152_class->version == RTL_VER_UNKNOWN) {
  1655. USB_LOG_ERR("Unknown version 0x%04x\r\n", rtl8152_class->version);
  1656. return -USB_ERR_NOTSUPP;
  1657. } else {
  1658. USB_LOG_INFO("rtl8152 version 0x%04x\r\n", rtl8152_class->version);
  1659. }
  1660. /* MTU range: 68 - 1500 or 9194 */
  1661. rtl8152_class->min_mtu = 68;
  1662. switch (rtl8152_class->version) {
  1663. case RTL_VER_03:
  1664. case RTL_VER_04:
  1665. case RTL_VER_05:
  1666. case RTL_VER_06:
  1667. case RTL_VER_08:
  1668. case RTL_VER_09:
  1669. case RTL_VER_14:
  1670. rtl8152_class->max_mtu = size_to_mtu(9 * 1024);
  1671. break;
  1672. case RTL_VER_10:
  1673. case RTL_VER_11:
  1674. rtl8152_class->max_mtu = size_to_mtu(15 * 1024);
  1675. break;
  1676. case RTL_VER_12:
  1677. case RTL_VER_13:
  1678. case RTL_VER_15:
  1679. rtl8152_class->max_mtu = size_to_mtu(16 * 1024);
  1680. break;
  1681. case RTL_VER_01:
  1682. case RTL_VER_02:
  1683. case RTL_VER_07:
  1684. default:
  1685. rtl8152_class->max_mtu = 1500;
  1686. break;
  1687. }
  1688. rtl8152_class->saved_wolopts = __rtl_get_wol(rtl8152_class);
  1689. if (rtl_ops_init(rtl8152_class) < 0) {
  1690. return -USB_ERR_NODEV;
  1691. }
  1692. rtl8152_class->rtl_ops.init(rtl8152_class);
  1693. rtl8152_class->rtl_ops.up(rtl8152_class);
  1694. if (rtl8152_class->rx_buf_sz > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) {
  1695. USB_LOG_ERR("rx_buf_sz is overflow, default is %d\r\n", CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE);
  1696. return -USB_ERR_NOMEM;
  1697. }
  1698. memset(mac_buffer, 0, 12);
  1699. ret = usbh_get_string_desc(rtl8152_class->hport, 3, (uint8_t *)mac_buffer);
  1700. if (ret < 0) {
  1701. return ret;
  1702. }
  1703. for (int i = 0, j = 0; i < 12; i += 2, j++) {
  1704. char byte_str[3];
  1705. byte_str[0] = mac_buffer[i];
  1706. byte_str[1] = mac_buffer[i + 1];
  1707. byte_str[2] = '\0';
  1708. uint32_t byte = strtoul(byte_str, NULL, 16);
  1709. rtl8152_class->mac[j] = (unsigned char)byte;
  1710. }
  1711. r8152_write_hwaddr(rtl8152_class, rtl8152_class->mac);
  1712. USB_LOG_INFO("RTL8152 MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n",
  1713. rtl8152_class->mac[0],
  1714. rtl8152_class->mac[1],
  1715. rtl8152_class->mac[2],
  1716. rtl8152_class->mac[3],
  1717. rtl8152_class->mac[4],
  1718. rtl8152_class->mac[5]);
  1719. for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) {
  1720. ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc;
  1721. if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  1722. if (ep_desc->bEndpointAddress & 0x80) {
  1723. USBH_EP_INIT(rtl8152_class->intin, ep_desc);
  1724. } else {
  1725. return -USB_ERR_NOTSUPP;
  1726. }
  1727. } else {
  1728. if (ep_desc->bEndpointAddress & 0x80) {
  1729. USBH_EP_INIT(rtl8152_class->bulkin, ep_desc);
  1730. } else {
  1731. USBH_EP_INIT(rtl8152_class->bulkout, ep_desc);
  1732. }
  1733. }
  1734. }
  1735. strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN);
  1736. USB_LOG_INFO("Register RTL8152 Class:%s\r\n", hport->config.intf[intf].devname);
  1737. usbh_rtl8152_run(rtl8152_class);
  1738. return 0;
  1739. }
  1740. static int usbh_rtl8152_disconnect(struct usbh_hubport *hport, uint8_t intf)
  1741. {
  1742. int ret = 0;
  1743. struct usbh_rtl8152 *rtl8152_class = (struct usbh_rtl8152 *)hport->config.intf[intf].priv;
  1744. if (rtl8152_class) {
  1745. if (rtl8152_class->bulkin) {
  1746. usbh_kill_urb(&rtl8152_class->bulkin_urb);
  1747. }
  1748. if (rtl8152_class->bulkout) {
  1749. usbh_kill_urb(&rtl8152_class->bulkout_urb);
  1750. }
  1751. if (rtl8152_class->intin) {
  1752. usbh_kill_urb(&rtl8152_class->intin_urb);
  1753. }
  1754. if (hport->config.intf[intf].devname[0] != '\0') {
  1755. USB_LOG_INFO("Unregister rtl8152 Class:%s\r\n", hport->config.intf[intf].devname);
  1756. usbh_rtl8152_stop(rtl8152_class);
  1757. }
  1758. memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152));
  1759. }
  1760. return ret;
  1761. }
  1762. void usbh_rtl8152_rx_thread(void *argument)
  1763. {
  1764. uint32_t g_rtl8152_rx_length;
  1765. int ret;
  1766. uint16_t len;
  1767. uint16_t data_offset;
  1768. #if CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE <= (16 * 1024)
  1769. uint32_t transfer_size = CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE;
  1770. #else
  1771. uint32_t transfer_size = (16 * 1024);
  1772. #endif
  1773. (void)argument;
  1774. USB_LOG_INFO("Create rtl8152 rx thread\r\n");
  1775. // clang-format off
  1776. find_class:
  1777. // clang-format on
  1778. g_rtl8152_class.connect_status = false;
  1779. if (usbh_find_class_instance("/dev/rtl8152") == NULL) {
  1780. goto delete;
  1781. }
  1782. while (g_rtl8152_class.connect_status == false) {
  1783. ret = usbh_rtl8152_get_connect_status(&g_rtl8152_class);
  1784. if (ret < 0) {
  1785. usb_osal_msleep(100);
  1786. goto find_class;
  1787. }
  1788. usb_osal_msleep(128);
  1789. }
  1790. if (g_rtl8152_class.rtl_ops.enable) {
  1791. g_rtl8152_class.rtl_ops.enable(&g_rtl8152_class);
  1792. } else {
  1793. goto delete;
  1794. }
  1795. rtl8152_set_rx_mode(&g_rtl8152_class);
  1796. rtl8152_set_speed(&g_rtl8152_class, AUTONEG_ENABLE, g_rtl8152_class.supports_gmii ? SPEED_1000 : SPEED_100, DUPLEX_FULL);
  1797. g_rtl8152_rx_length = 0;
  1798. while (1) {
  1799. usbh_bulk_urb_fill(&g_rtl8152_class.bulkin_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkin, &g_rtl8152_rx_buffer[g_rtl8152_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL);
  1800. ret = usbh_submit_urb(&g_rtl8152_class.bulkin_urb);
  1801. if (ret < 0) {
  1802. goto find_class;
  1803. }
  1804. g_rtl8152_rx_length += g_rtl8152_class.bulkin_urb.actual_length;
  1805. /* A transfer is complete because last packet is a short packet.
  1806. * Short packet is not zero, match g_rtl8152_rx_length % USB_GET_MAXPACKETSIZE(g_rtl8152_class.bulkin->wMaxPacketSize).
  1807. * Short packet is zero, check if g_rtl8152_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 1024 < 2048.
  1808. */
  1809. if (g_rtl8152_rx_length % USB_GET_MAXPACKETSIZE(g_rtl8152_class.bulkin->wMaxPacketSize) ||
  1810. (g_rtl8152_class.bulkin_urb.actual_length < transfer_size)) {
  1811. data_offset = 0;
  1812. USB_LOG_DBG("rxlen:%d\r\n", g_rtl8152_rx_length);
  1813. while (g_rtl8152_rx_length > 0) {
  1814. struct rx_desc *rx_desc = (struct rx_desc *)&g_rtl8152_rx_buffer[data_offset];
  1815. len = rx_desc->opts1 & RX_LEN_MASK;
  1816. USB_LOG_DBG("data_offset:%d, eth len:%d\r\n", data_offset, len);
  1817. uint8_t *buf = (uint8_t *)&g_rtl8152_rx_buffer[data_offset + sizeof(struct rx_desc)];
  1818. usbh_rtl8152_eth_input(buf, len);
  1819. data_offset += (len + sizeof(struct rx_desc));
  1820. g_rtl8152_rx_length -= (len + sizeof(struct rx_desc));
  1821. if (len & (RX_ALIGN - 1)) {
  1822. data_offset += (RX_ALIGN - (len & (RX_ALIGN - 1)));
  1823. g_rtl8152_rx_length -= (RX_ALIGN - (len & (RX_ALIGN - 1)));
  1824. }
  1825. }
  1826. } else {
  1827. #if CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE <= (16 * 1024)
  1828. if (g_rtl8152_rx_length == CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) {
  1829. #else
  1830. if ((g_rtl8152_rx_length + (16 * 1024)) > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) {
  1831. #endif
  1832. USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE\r\n");
  1833. while (1) {
  1834. }
  1835. }
  1836. }
  1837. }
  1838. // clang-format off
  1839. delete:
  1840. USB_LOG_INFO("Delete rtl8152 rx thread\r\n");
  1841. usb_osal_thread_delete(NULL);
  1842. // clang-format on
  1843. }
  1844. uint8_t *usbh_rtl8152_get_eth_txbuf(void)
  1845. {
  1846. return (g_rtl8152_tx_buffer + sizeof(struct tx_desc));
  1847. }
  1848. int usbh_rtl8152_eth_output(uint32_t buflen)
  1849. {
  1850. struct tx_desc *tx_desc;
  1851. if (g_rtl8152_class.connect_status == false) {
  1852. return -USB_ERR_NOTCONN;
  1853. }
  1854. tx_desc = (struct tx_desc *)g_rtl8152_tx_buffer;
  1855. tx_desc->opts1 = buflen | TX_FS | TX_LS;
  1856. tx_desc->opts2 = 0;
  1857. USB_LOG_DBG("txlen:%d\r\n", buflen + sizeof(struct tx_desc));
  1858. usbh_bulk_urb_fill(&g_rtl8152_class.bulkout_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkout, g_rtl8152_tx_buffer, buflen + sizeof(struct tx_desc), USB_OSAL_WAITING_FOREVER, NULL, NULL);
  1859. return usbh_submit_urb(&g_rtl8152_class.bulkout_urb);
  1860. }
  1861. __WEAK void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class)
  1862. {
  1863. (void)rtl8152_class;
  1864. }
  1865. __WEAK void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class)
  1866. {
  1867. (void)rtl8152_class;
  1868. }
  1869. static const uint16_t rtl_id_table[][2] = {
  1870. { 0x0BDA, 0x8152 },
  1871. { 0, 0 },
  1872. };
  1873. static const struct usbh_class_driver rtl8152_class_driver = {
  1874. .driver_name = "rtl8152",
  1875. .connect = usbh_rtl8152_connect,
  1876. .disconnect = usbh_rtl8152_disconnect
  1877. };
  1878. CLASS_INFO_DEFINE const struct usbh_class_info rtl8152_class_info = {
  1879. .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS,
  1880. .bInterfaceClass = 0xff,
  1881. .bInterfaceSubClass = 0x00,
  1882. .bInterfaceProtocol = 0x00,
  1883. .id_table = rtl_id_table,
  1884. .class_driver = &rtl8152_class_driver
  1885. };