usb_glue_bouffalo.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143
  1. /*
  2. * Copyright (c) 2024, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "bflb_core.h"
  7. #include "usbh_core.h"
  8. #include "hardware/usb_v2_reg.h"
  9. #ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
  10. #error "usb host must enable CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE"
  11. #endif
  12. #define BLFB_USB_BASE ((uint32_t)0x20072000)
  13. #define BFLB_PDS_BASE ((uint32_t)0x2000e000)
  14. #define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */
  15. #define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
  16. /* 0x500 : usb_ctl */
  17. #define PDS_REG_USB_SW_RST_N (1 << 0U)
  18. #define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
  19. #define PDS_REG_USB_WAKEUP (1 << 2U)
  20. #define PDS_REG_USB_L1_WAKEUP (1 << 3U)
  21. #define PDS_REG_USB_DRVBUS_POL (1 << 4U)
  22. #define PDS_REG_USB_IDDIG (1 << 5U)
  23. /* 0x504 : usb_phy_ctrl */
  24. #define PDS_REG_USB_PHY_PONRST (1 << 0U)
  25. #define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U)
  26. #define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
  27. #define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
  28. #define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U)
  29. #define PDS_REG_USB_PHY_PLLALIV (1 << 5U)
  30. #define PDS_REG_PU_USB20_PSW (1 << 6U)
  31. #define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)
  32. #define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)
  33. extern void USBH_IRQHandler(uint8_t busid);
  34. void USBH_IRQ(int irq, void *arg) {
  35. USBH_IRQHandler(0);
  36. }
  37. static void bflb_usb_phy_init(void)
  38. {
  39. uint32_t regval;
  40. /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */
  41. /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
  42. /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */
  43. /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */
  44. /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */
  45. /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */
  46. /* #1.2ms; wait UCLK */
  47. /* wait(soc616_b0.usb_uclk); */
  48. regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  49. regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
  50. putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  51. regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  52. regval |= PDS_REG_PU_USB20_PSW;
  53. putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  54. regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  55. regval |= PDS_REG_USB_PHY_PONRST;
  56. putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
  57. /* greater than 5T */
  58. bflb_mtimer_delay_us(1);
  59. regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  60. regval &= ~PDS_REG_USB_SW_RST_N;
  61. putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  62. /* greater than 5T */
  63. bflb_mtimer_delay_us(1);
  64. regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  65. regval |= PDS_REG_USB_EXT_SUSP_N;
  66. putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  67. /* wait UCLK 1.2ms */
  68. bflb_mtimer_delay_ms(3);
  69. regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  70. regval |= PDS_REG_USB_SW_RST_N;
  71. putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  72. bflb_mtimer_delay_ms(2);
  73. }
  74. void usb_hc_low_level_init(struct usbh_bus *bus)
  75. {
  76. uint32_t regval;
  77. bflb_usb_phy_init();
  78. bflb_irq_attach(37, USBH_IRQ, NULL);
  79. bflb_irq_enable(37);
  80. /* enable device-A for host */
  81. regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  82. regval &= ~PDS_REG_USB_IDDIG;
  83. putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
  84. regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
  85. regval |= USB_A_BUS_DROP_HOV;
  86. regval &= ~USB_A_BUS_REQ_HOV;
  87. putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
  88. bflb_mtimer_delay_ms(10);
  89. /* enable vbus and bus control */
  90. regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
  91. regval &= ~USB_A_BUS_DROP_HOV;
  92. regval |= USB_A_BUS_REQ_HOV;
  93. putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
  94. regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
  95. regval |= USB_MDEV_INT;
  96. regval |= USB_MOTG_INT;
  97. regval &= ~USB_MHC_INT;
  98. putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
  99. }
  100. uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
  101. {
  102. uint8_t speed = 3;
  103. speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
  104. if (speed == 0) {
  105. return USB_SPEED_FULL;
  106. } else if (speed == 1) {
  107. return USB_SPEED_LOW;
  108. } else if (speed == 2) {
  109. return USB_SPEED_HIGH;
  110. }
  111. return USB_SPEED_HIGH;
  112. }