usb_dc_fsdev.c 18 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbd_core.h"
  7. #ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
  8. #error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h"
  9. #endif
  10. #define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
  11. #include "usb_fsdev_reg.h"
  12. #ifndef CONFIG_USB_FSDEV_RAM_SIZE
  13. #define CONFIG_USB_FSDEV_RAM_SIZE 512
  14. #endif
  15. #ifndef CONFIG_USBDEV_EP_NUM
  16. #define CONFIG_USBDEV_EP_NUM 8
  17. #endif
  18. #define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base)
  19. #define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
  20. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  21. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  22. /* Endpoint state */
  23. struct fsdev_ep_state {
  24. uint16_t ep_mps; /* Endpoint max packet size */
  25. uint8_t ep_type; /* Endpoint type */
  26. uint8_t ep_stalled; /* Endpoint stall flag */
  27. uint8_t ep_enable; /* Endpoint enable */
  28. uint16_t ep_pma_buf_len; /* Previously allocated buffer size */
  29. uint16_t ep_pma_addr; /* ep pmd allocated addr */
  30. uint8_t *xfer_buf;
  31. uint32_t xfer_len;
  32. uint32_t actual_xfer_len;
  33. };
  34. /* Driver state */
  35. struct fsdev_udc {
  36. struct usb_setup_packet setup;
  37. volatile uint8_t dev_addr; /*!< USB Address */
  38. volatile uint32_t pma_offset; /*!< pma offset */
  39. struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
  40. struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
  41. } g_fsdev_udc;
  42. __WEAK void usb_dc_low_level_init(void)
  43. {
  44. }
  45. __WEAK void usb_dc_low_level_deinit(void)
  46. {
  47. }
  48. int usb_dc_init(uint8_t busid)
  49. {
  50. usb_dc_low_level_init();
  51. /* Init Device */
  52. /* CNTR_FRES = 1 */
  53. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  54. /* CNTR_FRES = 0 */
  55. USB->CNTR = 0U;
  56. /* Clear pending interrupts */
  57. USB->ISTR = 0U;
  58. /*Set Btable Address*/
  59. USB->BTABLE = BTABLE_ADDRESS;
  60. uint32_t winterruptmask;
  61. /* Set winterruptmask variable */
  62. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  63. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  64. USB_CNTR_SOFM | USB_CNTR_ESOFM |
  65. USB_CNTR_RESETM;
  66. /* Set interrupt mask */
  67. USB->CNTR = (uint16_t)winterruptmask;
  68. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  69. USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
  70. return 0;
  71. }
  72. int usb_dc_deinit(uint8_t busid)
  73. {
  74. /* disable all interrupts and force USB reset */
  75. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  76. /* clear interrupt status register */
  77. USB->ISTR = 0U;
  78. /* switch-off device */
  79. USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
  80. usb_dc_low_level_deinit();
  81. return 0;
  82. }
  83. int usbd_set_address(uint8_t busid, const uint8_t addr)
  84. {
  85. if (addr == 0U) {
  86. /* set device address and enable function */
  87. USB->DADDR = (uint16_t)USB_DADDR_EF;
  88. }
  89. g_fsdev_udc.dev_addr = addr;
  90. return 0;
  91. }
  92. int usbd_set_remote_wakeup(uint8_t busid)
  93. {
  94. return -1;
  95. }
  96. uint8_t usbd_get_port_speed(uint8_t busid)
  97. {
  98. return USB_SPEED_FULL;
  99. }
  100. int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
  101. {
  102. uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
  103. if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) {
  104. USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress);
  105. return -1;
  106. }
  107. uint16_t wEpRegVal;
  108. /* initialize Endpoint */
  109. switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) {
  110. case USB_ENDPOINT_TYPE_CONTROL:
  111. wEpRegVal = USB_EP_CONTROL;
  112. break;
  113. case USB_ENDPOINT_TYPE_BULK:
  114. wEpRegVal = USB_EP_BULK;
  115. break;
  116. case USB_ENDPOINT_TYPE_INTERRUPT:
  117. wEpRegVal = USB_EP_INTERRUPT;
  118. break;
  119. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  120. wEpRegVal = USB_EP_ISOCHRONOUS;
  121. USB_LOG_ERR("Do not support iso in fsdev\r\n");
  122. return -1;
  123. default:
  124. break;
  125. }
  126. PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
  127. PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
  128. if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
  129. g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  130. g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  131. g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
  132. if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
  133. if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
  134. USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
  135. return -1;
  136. }
  137. g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  138. g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  139. /*Set the endpoint Receive buffer address */
  140. PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  141. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  142. }
  143. /*Set the endpoint Receive buffer counter*/
  144. PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize));
  145. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  146. } else {
  147. g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  148. g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  149. g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
  150. if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
  151. if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) {
  152. USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress);
  153. return -1;
  154. }
  155. g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  156. g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  157. /*Set the endpoint Transmit buffer address */
  158. PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  159. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  160. }
  161. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  162. if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  163. /* Configure NAK status for the Endpoint */
  164. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  165. } else {
  166. /* Configure TX Endpoint to disabled state */
  167. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  168. }
  169. }
  170. return 0;
  171. }
  172. int usbd_ep_close(uint8_t busid, const uint8_t ep)
  173. {
  174. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  175. if (USB_EP_DIR_IS_OUT(ep)) {
  176. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  177. /* Configure DISABLE status for the Endpoint*/
  178. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
  179. } else {
  180. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  181. /* Configure DISABLE status for the Endpoint*/
  182. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  183. }
  184. return 0;
  185. }
  186. int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
  187. {
  188. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  189. if (USB_EP_DIR_IS_OUT(ep)) {
  190. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
  191. } else {
  192. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
  193. }
  194. return 0;
  195. }
  196. int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
  197. {
  198. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  199. if (USB_EP_DIR_IS_OUT(ep)) {
  200. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  201. /* Configure VALID status for the Endpoint */
  202. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  203. } else {
  204. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  205. if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  206. /* Configure NAK status for the Endpoint */
  207. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  208. }
  209. }
  210. return 0;
  211. }
  212. int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
  213. {
  214. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  215. if (USB_EP_DIR_IS_OUT(ep)) {
  216. if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) {
  217. *stalled = 1;
  218. } else {
  219. *stalled = 0;
  220. }
  221. } else {
  222. if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) {
  223. *stalled = 1;
  224. } else {
  225. *stalled = 0;
  226. }
  227. }
  228. return 0;
  229. }
  230. int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
  231. {
  232. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  233. if (!data && data_len) {
  234. return -1;
  235. }
  236. if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) {
  237. return -2;
  238. }
  239. g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
  240. g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
  241. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
  242. data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  243. fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
  244. PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
  245. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  246. return 0;
  247. }
  248. int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
  249. {
  250. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  251. if (!data && data_len) {
  252. return -1;
  253. }
  254. if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) {
  255. return -2;
  256. }
  257. g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
  258. g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
  259. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
  260. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  261. return 0;
  262. }
  263. void USBD_IRQHandler(uint8_t busid)
  264. {
  265. uint16_t wIstr, wEPVal;
  266. uint8_t ep_idx;
  267. uint8_t read_count;
  268. uint16_t write_count;
  269. uint16_t store_ep[8];
  270. wIstr = USB->ISTR;
  271. if (wIstr & USB_ISTR_CTR) {
  272. while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
  273. wIstr = USB->ISTR;
  274. /* extract highest priority endpoint number */
  275. ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
  276. if (ep_idx == 0U) {
  277. if ((wIstr & USB_ISTR_DIR) == 0U) {
  278. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  279. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  280. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  281. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  282. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  283. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  284. if (g_fsdev_udc.setup.wLength == 0) {
  285. /* In status, start reading setup */
  286. usbd_ep_start_read(0, 0x00, NULL, 0);
  287. } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
  288. /* In status, start reading setup */
  289. usbd_ep_start_read(0, 0x00, NULL, 0);
  290. }
  291. if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
  292. USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
  293. g_fsdev_udc.dev_addr = 0U;
  294. }
  295. } else {
  296. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  297. if ((wEPVal & USB_EP_SETUP) != 0U) {
  298. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  299. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  300. fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  301. usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup);
  302. } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  303. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  304. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  305. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  306. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  307. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  308. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  309. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  310. if (read_count == 0) {
  311. /* Out status, start reading setup */
  312. usbd_ep_start_read(0, 0x00, NULL, 0);
  313. }
  314. }
  315. }
  316. } else {
  317. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  318. if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  319. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  320. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  321. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  322. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  323. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  324. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  325. if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
  326. (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
  327. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  328. } else {
  329. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  330. }
  331. }
  332. if ((wEPVal & USB_EP_CTR_TX) != 0U) {
  333. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  334. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  335. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  336. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  337. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  338. if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
  339. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  340. } else {
  341. write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  342. fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
  343. PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
  344. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  345. }
  346. }
  347. }
  348. }
  349. }
  350. if (wIstr & USB_ISTR_RESET) {
  351. memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
  352. g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
  353. usbd_event_reset_handler(0);
  354. /* start reading setup packet */
  355. PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
  356. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  357. }
  358. if (wIstr & USB_ISTR_PMAOVR) {
  359. USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
  360. }
  361. if (wIstr & USB_ISTR_ERR) {
  362. USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
  363. }
  364. if (wIstr & USB_ISTR_WKUP) {
  365. USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
  366. USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
  367. USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
  368. }
  369. if (wIstr & USB_ISTR_SUSP) {
  370. /* WA: To Clear Wakeup flag if raised with suspend signal */
  371. /* Store Endpoint register */
  372. for (uint8_t i = 0U; i < 8U; i++) {
  373. store_ep[i] = PCD_GET_ENDPOINT(USB, i);
  374. }
  375. /* FORCE RESET */
  376. USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
  377. /* CLEAR RESET */
  378. USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
  379. /* wait for reset flag in ISTR */
  380. while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
  381. }
  382. /* Clear Reset Flag */
  383. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  384. /* Restore Registre */
  385. for (uint8_t i = 0U; i < 8U; i++) {
  386. PCD_SET_ENDPOINT(USB, i, store_ep[i]);
  387. }
  388. /* Force low-power mode in the macrocell */
  389. USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
  390. /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
  391. USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
  392. USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
  393. }
  394. if (wIstr & USB_ISTR_SOF) {
  395. USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
  396. }
  397. if (wIstr & USB_ISTR_ESOF) {
  398. USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
  399. }
  400. }
  401. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  402. {
  403. uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
  404. uint32_t BaseAddr = (uint32_t)USBx;
  405. uint32_t i, temp1, temp2;
  406. __IO uint16_t *pdwVal;
  407. uint8_t *pBuf = pbUsrBuf;
  408. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  409. for (i = n; i != 0U; i--) {
  410. temp1 = *pBuf;
  411. pBuf++;
  412. temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
  413. *pdwVal = (uint16_t)temp2;
  414. pdwVal++;
  415. #if PMA_ACCESS > 1U
  416. pdwVal++;
  417. #endif
  418. pBuf++;
  419. }
  420. }
  421. /**
  422. * @brief Copy data from packet memory area (PMA) to user memory buffer
  423. * @param USBx USB peripheral instance register address.
  424. * @param pbUsrBuf pointer to user memory area.
  425. * @param wPMABufAddr address into PMA.
  426. * @param wNBytes no. of bytes to be copied.
  427. * @retval None
  428. */
  429. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  430. {
  431. uint32_t n = (uint32_t)wNBytes >> 1;
  432. uint32_t BaseAddr = (uint32_t)USBx;
  433. uint32_t i, temp;
  434. __IO uint16_t *pdwVal;
  435. uint8_t *pBuf = pbUsrBuf;
  436. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  437. for (i = n; i != 0U; i--) {
  438. temp = *(__IO uint16_t *)pdwVal;
  439. pdwVal++;
  440. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  441. pBuf++;
  442. *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
  443. pBuf++;
  444. #if PMA_ACCESS > 1U
  445. pdwVal++;
  446. #endif
  447. }
  448. if ((wNBytes % 2U) != 0U) {
  449. temp = *pdwVal;
  450. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  451. }
  452. }