drv_spi.c 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023-07-27 Chushicheng the first version
  9. */
  10. #include "drv_spi.h"
  11. #include "pico/binary_info.h"
  12. #include "hardware/gpio.h"
  13. #include "hardware/spi.h"
  14. #include "hardware/dma.h"
  15. #ifdef BSP_USING_SPI
  16. #define DBG_TAG "drv.spi"
  17. #define DBG_LVL DBG_INFO
  18. #include <rtdbg.h>
  19. struct pico_spi
  20. {
  21. struct rt_spi_bus parent;
  22. spi_inst_t *handle;
  23. rt_uint8_t spi_rx_pin;
  24. rt_uint8_t spi_tx_pin;
  25. rt_uint8_t spi_sck_pin;
  26. rt_uint8_t spi_cs_pin;
  27. rt_uint8_t dma_tx;
  28. rt_uint8_t dma_rx;
  29. char *device_name;
  30. };
  31. static struct pico_spi pico_spi_obj[] =
  32. {
  33. #ifdef BSP_USING_SPI0
  34. {
  35. .handle = spi0,
  36. .spi_rx_pin = 4,
  37. .spi_tx_pin = 3,
  38. .spi_sck_pin = 2,
  39. .spi_cs_pin = 5,
  40. .device_name = "spi0",
  41. },
  42. #endif
  43. #ifdef BSP_USING_SPI1
  44. {
  45. .handle = spi1,
  46. .spi_rx_pin = 12,
  47. .spi_tx_pin = 11,
  48. .spi_sck_pin = 10,
  49. .spi_cs_pin = 13,
  50. .device_name = "spi1",
  51. },
  52. #endif
  53. };
  54. static rt_err_t pico_spi_init(struct pico_spi *spi_drv, struct rt_spi_configuration *cfg)
  55. {
  56. RT_ASSERT(spi_drv != RT_NULL);
  57. RT_ASSERT(cfg != RT_NULL);
  58. spi_inst_t *spi_handle = spi_drv->handle;
  59. spi_cpol_t cpol;
  60. spi_cpha_t cpha;
  61. rt_uint8_t dma_transfer_size;
  62. if (cfg->mode & RT_SPI_SLAVE)
  63. {
  64. spi_set_slave(spi_handle, true);
  65. }
  66. else
  67. {
  68. spi_set_slave(spi_handle, false);
  69. }
  70. if (cfg->mode & RT_SPI_CPHA)
  71. {
  72. cpha = SPI_CPHA_1;
  73. }
  74. else
  75. {
  76. cpha = SPI_CPHA_0;
  77. }
  78. if (cfg->mode & RT_SPI_CPOL)
  79. {
  80. cpol = SPI_CPOL_1;
  81. }
  82. else
  83. {
  84. cpol = SPI_CPOL_0;
  85. }
  86. if (cfg->data_width >= 4
  87. && cfg->data_width <= 16)
  88. {
  89. spi_set_format(spi_handle, cfg->data_width, cpol, cpha, SPI_MSB_FIRST);
  90. }
  91. else
  92. {
  93. return -RT_EIO;
  94. }
  95. LOG_D("spi baudrate:%d", cfg->max_hz);
  96. spi_init(spi_handle, cfg->max_hz);
  97. gpio_set_function(spi_drv->spi_rx_pin, GPIO_FUNC_SPI);
  98. gpio_init(spi_drv->spi_cs_pin);
  99. gpio_set_function(spi_drv->spi_sck_pin, GPIO_FUNC_SPI);
  100. gpio_set_function(spi_drv->spi_tx_pin, GPIO_FUNC_SPI);
  101. // Make the SPI pins available to picotool
  102. bi_decl(bi_3pins_with_func(spi_drv->spi_rx_pin, spi_drv->spi_tx_pin, spi_drv->spi_sck_pin, GPIO_FUNC_SPI));
  103. // Make the CS pin available to picotool
  104. bi_decl(bi_1pin_with_name(spi_drv->spi_cs_pin, "SPI CS"));
  105. // Grab some unused dma channels
  106. spi_drv->dma_tx = dma_claim_unused_channel(true);
  107. spi_drv->dma_rx = dma_claim_unused_channel(true);
  108. /* DMA configuration */
  109. if(cfg->data_width == 8)
  110. {
  111. dma_transfer_size = DMA_SIZE_8;
  112. }
  113. else if(cfg->data_width == 16)
  114. {
  115. dma_transfer_size = DMA_SIZE_16;
  116. }
  117. else if(cfg->data_width == 32)
  118. {
  119. dma_transfer_size = DMA_SIZE_32;
  120. }
  121. dma_channel_config c = dma_channel_get_default_config(spi_drv->dma_tx);
  122. channel_config_set_transfer_data_size(&c, dma_transfer_size);
  123. channel_config_set_dreq(&c, spi_get_index(spi_handle) ? DREQ_SPI1_TX : DREQ_SPI0_TX);
  124. dma_channel_set_config(spi_drv->dma_tx, &c, false);
  125. c = dma_channel_get_default_config(spi_drv->dma_rx);
  126. channel_config_set_transfer_data_size(&c, dma_transfer_size);
  127. channel_config_set_dreq(&c, spi_get_index(spi_handle) ? DREQ_SPI1_RX : DREQ_SPI0_RX);
  128. channel_config_set_read_increment(&c, false);
  129. channel_config_set_write_increment(&c, true);
  130. dma_channel_set_config(spi_drv->dma_rx, &c, false);
  131. return RT_EOK;
  132. }
  133. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin)
  134. {
  135. rt_err_t ret = RT_EOK;
  136. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  137. ret = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, cs_pin, RT_NULL);
  138. return ret;
  139. }
  140. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  141. {
  142. int i;
  143. RT_ASSERT(device != RT_NULL);
  144. RT_ASSERT(device->bus != RT_NULL);
  145. struct pico_spi *spi = rt_container_of(device->bus, struct pico_spi, parent);
  146. if(message->cs_take && (device->cs_pin != PIN_NONE))
  147. {
  148. rt_pin_write(device->cs_pin, PIN_LOW);
  149. }
  150. dma_channel_config c = dma_get_channel_config(spi->dma_tx);
  151. dma_channel_configure(spi->dma_tx, &c,
  152. &spi_get_hw(spi->handle)->dr, // write address
  153. (uint8_t *)(message->send_buf), // read address
  154. message->length, // element count (each element is of size transfer_data_size)
  155. false); // don't start yet
  156. c = dma_get_channel_config(spi->dma_rx);
  157. dma_channel_configure(spi->dma_rx, &c,
  158. (uint8_t *)(message->recv_buf), // write address
  159. &spi_get_hw(spi->handle)->dr, // read address
  160. message->length, // element count (each element is of size transfer_data_size)
  161. false); // don't start yet
  162. dma_start_channel_mask((1u << spi->dma_tx) | (1u << spi->dma_rx));
  163. dma_channel_wait_for_finish_blocking(spi->dma_tx);
  164. dma_channel_wait_for_finish_blocking(spi->dma_rx);
  165. if(message->cs_release && (device->cs_pin != PIN_NONE))
  166. {
  167. rt_pin_write(device->cs_pin, PIN_HIGH);
  168. }
  169. return message->length;
  170. }
  171. static rt_err_t spi_configure(struct rt_spi_device *device,
  172. struct rt_spi_configuration *configuration)
  173. {
  174. rt_err_t ret = RT_EOK;
  175. struct pico_spi *spi = rt_container_of(device->bus, struct pico_spi, parent);
  176. ret = pico_spi_init(spi, configuration);
  177. return ret;
  178. }
  179. static const struct rt_spi_ops pico_spi_ops =
  180. {
  181. .configure = spi_configure,
  182. .xfer = spixfer,
  183. };
  184. int rt_hw_spi_init(void)
  185. {
  186. int result = RT_EOK;
  187. for (rt_size_t i = 0; i < sizeof(pico_spi_obj) / sizeof(struct pico_spi); i++)
  188. {
  189. LOG_D("%s initing", pico_spi_obj[i].device_name);
  190. /* register spi device */
  191. if (rt_spi_bus_register(&pico_spi_obj[i].parent, pico_spi_obj[i].device_name, &pico_spi_ops) == RT_EOK)
  192. {
  193. LOG_D("%s init success", pico_spi_obj[i].device_name);
  194. }
  195. else
  196. {
  197. LOG_E("%s register failed", pico_spi_obj[i].device_name);
  198. result = -RT_ERROR;
  199. }
  200. }
  201. return result;
  202. }
  203. INIT_BOARD_EXPORT(rt_hw_spi_init);
  204. #endif /* BSP_USING_SPI */