drv_adc.c 9.3 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-05 zylx first version
  9. * 2018-12-12 greedyhao Porting for stm32f7xx
  10. * 2019-02-01 yuneizhilin fix the stm32_adc_init function initialization issue
  11. * 2020-06-17 thread-liu Porting for stm32mp1xx
  12. * 2020-10-14 Dozingfiretruck Porting for stm32wbxx
  13. * 2022-05-22 Stanley Lwin Add stm32_adc_get_vref
  14. */
  15. #include <board.h>
  16. #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
  17. #include "drv_config.h"
  18. //#define DRV_DEBUG
  19. #define LOG_TAG "drv.adc"
  20. #include <drv_log.h>
  21. static ADC_HandleTypeDef adc_config[] =
  22. {
  23. #ifdef BSP_USING_ADC1
  24. ADC1_CONFIG,
  25. #endif
  26. #ifdef BSP_USING_ADC2
  27. ADC2_CONFIG,
  28. #endif
  29. #ifdef BSP_USING_ADC3
  30. ADC3_CONFIG,
  31. #endif
  32. };
  33. struct stm32_adc
  34. {
  35. ADC_HandleTypeDef ADC_Handler;
  36. struct rt_adc_device stm32_adc_device;
  37. };
  38. static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
  39. static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  40. {
  41. ADC_HandleTypeDef *stm32_adc_handler;
  42. RT_ASSERT(device != RT_NULL);
  43. stm32_adc_handler = device->parent.user_data;
  44. if (enabled)
  45. {
  46. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
  47. ADC_Enable(stm32_adc_handler);
  48. #else
  49. __HAL_ADC_ENABLE(stm32_adc_handler);
  50. #endif
  51. }
  52. else
  53. {
  54. #if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined (SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
  55. ADC_Disable(stm32_adc_handler);
  56. #else
  57. __HAL_ADC_DISABLE(stm32_adc_handler);
  58. #endif
  59. }
  60. return RT_EOK;
  61. }
  62. static rt_uint8_t stm32_adc_get_resolution(struct rt_adc_device *device)
  63. {
  64. ADC_HandleTypeDef *stm32_adc_handler;
  65. RT_ASSERT(device != RT_NULL);
  66. stm32_adc_handler = device->parent.user_data;
  67. switch(stm32_adc_handler->Init.Resolution)
  68. {
  69. case ADC_RESOLUTION_12B:
  70. return 12;
  71. case ADC_RESOLUTION_10B:
  72. return 10;
  73. case ADC_RESOLUTION_8B:
  74. return 8;
  75. case ADC_RESOLUTION_6B:
  76. return 6;
  77. default:
  78. return 0;
  79. }
  80. }
  81. static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
  82. {
  83. rt_uint32_t stm32_channel = 0;
  84. switch (channel)
  85. {
  86. case 0:
  87. stm32_channel = ADC_CHANNEL_0;
  88. break;
  89. case 1:
  90. stm32_channel = ADC_CHANNEL_1;
  91. break;
  92. case 2:
  93. stm32_channel = ADC_CHANNEL_2;
  94. break;
  95. case 3:
  96. stm32_channel = ADC_CHANNEL_3;
  97. break;
  98. case 4:
  99. stm32_channel = ADC_CHANNEL_4;
  100. break;
  101. case 5:
  102. stm32_channel = ADC_CHANNEL_5;
  103. break;
  104. case 6:
  105. stm32_channel = ADC_CHANNEL_6;
  106. break;
  107. case 7:
  108. stm32_channel = ADC_CHANNEL_7;
  109. break;
  110. case 8:
  111. stm32_channel = ADC_CHANNEL_8;
  112. break;
  113. case 9:
  114. stm32_channel = ADC_CHANNEL_9;
  115. break;
  116. case 10:
  117. stm32_channel = ADC_CHANNEL_10;
  118. break;
  119. case 11:
  120. stm32_channel = ADC_CHANNEL_11;
  121. break;
  122. case 12:
  123. stm32_channel = ADC_CHANNEL_12;
  124. break;
  125. case 13:
  126. stm32_channel = ADC_CHANNEL_13;
  127. break;
  128. case 14:
  129. stm32_channel = ADC_CHANNEL_14;
  130. break;
  131. case 15:
  132. stm32_channel = ADC_CHANNEL_15;
  133. break;
  134. #ifdef ADC_CHANNEL_16
  135. case 16:
  136. stm32_channel = ADC_CHANNEL_16;
  137. break;
  138. #endif
  139. case 17:
  140. stm32_channel = ADC_CHANNEL_17;
  141. break;
  142. #ifdef ADC_CHANNEL_18
  143. case 18:
  144. stm32_channel = ADC_CHANNEL_18;
  145. break;
  146. #endif
  147. #ifdef ADC_CHANNEL_19
  148. case 19:
  149. stm32_channel = ADC_CHANNEL_19;
  150. break;
  151. #endif
  152. }
  153. return stm32_channel;
  154. }
  155. static rt_int16_t stm32_adc_get_vref (struct rt_adc_device *device)
  156. {
  157. RT_ASSERT(device);
  158. return 3300;
  159. }
  160. static rt_err_t stm32_adc_get_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  161. {
  162. ADC_ChannelConfTypeDef ADC_ChanConf;
  163. ADC_HandleTypeDef *stm32_adc_handler;
  164. RT_ASSERT(device != RT_NULL);
  165. RT_ASSERT(value != RT_NULL);
  166. stm32_adc_handler = device->parent.user_data;
  167. rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
  168. #ifndef ADC_CHANNEL_16
  169. if (channel == 16)
  170. {
  171. LOG_E("ADC channel must not be 16.");
  172. return -RT_ERROR;
  173. }
  174. #endif
  175. /* ADC channel number is up to 17 */
  176. #if !defined(ADC_CHANNEL_18)
  177. if (channel <= 17)
  178. /* ADC channel number is up to 19 */
  179. #elif defined(ADC_CHANNEL_19)
  180. if (channel <= 19)
  181. /* ADC channel number is up to 18 */
  182. #else
  183. if (channel <= 18)
  184. #endif
  185. {
  186. /* set stm32 ADC channel */
  187. ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
  188. }
  189. else
  190. {
  191. #if !defined(ADC_CHANNEL_18)
  192. LOG_E("ADC channel must be between 0 and 17.");
  193. #elif defined(ADC_CHANNEL_19)
  194. LOG_E("ADC channel must be between 0 and 19.");
  195. #else
  196. LOG_E("ADC channel must be between 0 and 18.");
  197. #endif
  198. return -RT_ERROR;
  199. }
  200. #if defined(SOC_SERIES_STM32MP1) || defined (SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
  201. ADC_ChanConf.Rank = ADC_REGULAR_RANK_1;
  202. #else
  203. ADC_ChanConf.Rank = 1;
  204. #endif
  205. #if defined(SOC_SERIES_STM32F0)
  206. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_71CYCLES_5;
  207. #elif defined(SOC_SERIES_STM32F1)
  208. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
  209. #elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
  210. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
  211. #elif defined(SOC_SERIES_STM32L4)
  212. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
  213. #elif defined(SOC_SERIES_STM32MP1)
  214. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_810CYCLES_5;
  215. #elif defined(SOC_SERIES_STM32H7)
  216. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_64CYCLES_5;
  217. #elif defined (SOC_SERIES_STM32WB)
  218. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
  219. #endif
  220. #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
  221. ADC_ChanConf.Offset = 0;
  222. #endif
  223. #if defined(SOC_SERIES_STM32L4)
  224. ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
  225. ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
  226. #elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) || defined (SOC_SERIES_STM32WB)
  227. ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE; /* ADC channel affected to offset number */
  228. ADC_ChanConf.Offset = 0;
  229. ADC_ChanConf.SingleDiff = ADC_SINGLE_ENDED; /* ADC channel differential mode */
  230. #endif
  231. HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
  232. /* perform an automatic ADC calibration to improve the conversion accuracy */
  233. #if defined(SOC_SERIES_STM32L4) || defined (SOC_SERIES_STM32WB)
  234. if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_ChanConf.SingleDiff) != HAL_OK)
  235. {
  236. LOG_E("ADC calibration error!\n");
  237. return -RT_ERROR;
  238. }
  239. #elif defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
  240. /* Run the ADC linear calibration in single-ended mode */
  241. if (HAL_ADCEx_Calibration_Start(stm32_adc_handler, ADC_CALIB_OFFSET_LINEARITY, ADC_ChanConf.SingleDiff) != HAL_OK)
  242. {
  243. LOG_E("ADC open linear calibration error!\n");
  244. /* Calibration Error */
  245. return -RT_ERROR;
  246. }
  247. #endif
  248. /* start ADC */
  249. HAL_ADC_Start(stm32_adc_handler);
  250. /* Wait for the ADC to convert */
  251. HAL_ADC_PollForConversion(stm32_adc_handler, 100);
  252. /* get ADC value */
  253. *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
  254. return RT_EOK;
  255. }
  256. static const struct rt_adc_ops stm_adc_ops =
  257. {
  258. .enabled = stm32_adc_enabled,
  259. .convert = stm32_adc_get_value,
  260. .get_resolution = stm32_adc_get_resolution,
  261. .get_vref = stm32_adc_get_vref,
  262. };
  263. static int stm32_adc_init(void)
  264. {
  265. int result = RT_EOK;
  266. /* save adc name */
  267. char name_buf[5] = {'a', 'd', 'c', '0', 0};
  268. int i = 0;
  269. for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
  270. {
  271. /* ADC init */
  272. name_buf[3] = '0';
  273. stm32_adc_obj[i].ADC_Handler = adc_config[i];
  274. #if defined(ADC1)
  275. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC1)
  276. {
  277. name_buf[3] = '1';
  278. }
  279. #endif
  280. #if defined(ADC2)
  281. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC2)
  282. {
  283. name_buf[3] = '2';
  284. }
  285. #endif
  286. #if defined(ADC3)
  287. if (stm32_adc_obj[i].ADC_Handler.Instance == ADC3)
  288. {
  289. name_buf[3] = '3';
  290. }
  291. #endif
  292. if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
  293. {
  294. LOG_E("%s init failed", name_buf);
  295. result = -RT_ERROR;
  296. }
  297. else
  298. {
  299. /* register ADC device */
  300. if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
  301. {
  302. LOG_D("%s init success", name_buf);
  303. }
  304. else
  305. {
  306. LOG_E("%s register failed", name_buf);
  307. result = -RT_ERROR;
  308. }
  309. }
  310. }
  311. return result;
  312. }
  313. INIT_BOARD_EXPORT(stm32_adc_init);
  314. #endif /* BSP_USING_ADC */