drv_hwtimer.c 3.0 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2015-09-02 heyuanjie87 the first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "lpc_timer.h"
  13. #include "lpc_clkpwr.h"
  14. #include "drv_hwtimer.h"
  15. #ifdef RT_USING_HWTIMER
  16. static void NVIC_Configuration(void)
  17. {
  18. NVIC_EnableIRQ(TIMER0_IRQn);
  19. }
  20. static void timer_init(rt_hwtimer_t *timer, rt_uint32_t state)
  21. {
  22. LPC_TIM_TypeDef *tim;
  23. TIM_TIMERCFG_Type cfg;
  24. tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
  25. TIM_DeInit(tim);
  26. if (state == 1)
  27. {
  28. NVIC_Configuration();
  29. cfg.PrescaleOption = TIM_PRESCALE_TICKVAL;
  30. cfg.PrescaleValue = 0xFFFF;
  31. TIM_Init(tim, TIM_TIMER_MODE, &cfg);
  32. }
  33. }
  34. static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
  35. {
  36. LPC_TIM_TypeDef *tim;
  37. TIM_MATCHCFG_Type match;
  38. tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
  39. match.MatchChannel = 0;
  40. match.IntOnMatch = ENABLE;
  41. match.ResetOnMatch = ENABLE;
  42. match.StopOnMatch = (opmode == HWTIMER_MODE_ONESHOT) ? ENABLE : DISABLE;
  43. match.ExtMatchOutputType = 0;
  44. match.MatchValue = t;
  45. TIM_ConfigMatch(tim, &match);
  46. TIM_Cmd(tim, ENABLE);
  47. return RT_EOK;
  48. }
  49. static void timer_stop(rt_hwtimer_t *timer)
  50. {
  51. LPC_TIM_TypeDef *tim;
  52. tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
  53. TIM_Cmd(tim, DISABLE);
  54. }
  55. static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
  56. {
  57. LPC_TIM_TypeDef *tim;
  58. rt_err_t err = RT_EOK;
  59. tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
  60. switch (cmd)
  61. {
  62. case HWTIMER_CTRL_FREQ_SET:
  63. {
  64. uint32_t clk;
  65. uint32_t pre;
  66. clk = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER);
  67. pre = clk / *((uint32_t *)arg) - 1;
  68. tim->PR = pre;
  69. }
  70. break;
  71. default:
  72. {
  73. err = -RT_ENOSYS;
  74. }
  75. break;
  76. }
  77. return err;
  78. }
  79. static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
  80. {
  81. LPC_TIM_TypeDef *tim;
  82. tim = (LPC_TIM_TypeDef *)timer->parent.user_data;
  83. return tim->TC;
  84. }
  85. static const struct rt_hwtimer_info _info =
  86. {
  87. 1000000, /* the maximum count frequency can be set */
  88. 2000, /* the minimum count frequency can be set */
  89. 0xFFFFFF, /* the maximum counter value */
  90. HWTIMER_CNTMODE_UP,/* Increment or Decreasing count mode */
  91. };
  92. static const struct rt_hwtimer_ops _ops =
  93. {
  94. timer_init,
  95. timer_start,
  96. timer_stop,
  97. timer_counter_get,
  98. timer_ctrl,
  99. };
  100. static rt_hwtimer_t _timer0;
  101. int rt_hw_hwtimer_init(void)
  102. {
  103. _timer0.info = &_info;
  104. _timer0.ops = &_ops;
  105. rt_device_hwtimer_register(&_timer0, "timer0", LPC_TIM0);
  106. return 0;
  107. }
  108. void TIMER0_IRQHandler(void)
  109. {
  110. if (TIM_GetIntStatus(LPC_TIM0, TIM_MR0_INT) != RESET)
  111. {
  112. TIM_ClearIntPending(LPC_TIM0, TIM_MR0_INT);
  113. rt_device_hwtimer_isr(&_timer0);
  114. }
  115. }
  116. INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
  117. #endif /* RT_USING_HWTIMER */