board.c 2.3 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-16 bluebear233 first version
  9. */
  10. #include <rtthread.h>
  11. #include "NuMicro.h"
  12. #include "drv_uart.h"
  13. #include "board.h"
  14. #ifdef __CC_ARM
  15. extern int Image$$RW_IRAM1$$ZI$$Limit;
  16. #elif __ICCARM__
  17. #pragma section="HEAP"
  18. #else
  19. extern int __bss_end;
  20. extern int __ram_top;
  21. #endif
  22. /**
  23. * This function will initial Clock tree.
  24. */
  25. static void clock_init(void)
  26. {
  27. /* Unlock protected registers */
  28. SYS_UnlockReg();
  29. SystemInit();
  30. /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
  31. PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
  32. /* Enable External XTAL (4~24 MHz) */
  33. CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
  34. /* Waiting for 12MHz clock ready */
  35. CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
  36. /* Switch HCLK clock source to HXT */
  37. CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
  38. /* Set core clock as PLL_CLOCK from PLL */
  39. CLK_SetCoreClock(FREQ_192MHZ);
  40. /* Set both PCLK0 and PCLK1 as HCLK/4 */
  41. CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;
  42. SystemCoreClockUpdate();
  43. /* Lock protected registers */
  44. SYS_LockReg();
  45. }
  46. /**
  47. * This function will initial M487 board.
  48. */
  49. void rt_hw_board_init(void)
  50. {
  51. clock_init();
  52. #ifdef RT_USING_HEAP
  53. #ifdef __CC_ARM
  54. rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
  55. #elif __ICCARM__
  56. rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
  57. #else
  58. /* init memory system */
  59. rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
  60. #endif
  61. #endif /* RT_USING_HEAP */
  62. rt_hw_uart_init();
  63. #ifdef RT_USING_CONSOLE
  64. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  65. #endif
  66. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  67. NVIC_SetPriorityGrouping(7);
  68. #ifdef RT_USING_COMPONENTS_INIT
  69. rt_components_board_init();
  70. #endif
  71. }
  72. /**
  73. * This is the timer interrupt service routine.
  74. *
  75. */
  76. void SysTick_Handler(void)
  77. {
  78. /* enter interrupt */
  79. rt_interrupt_enter();
  80. rt_tick_increase();
  81. /* leave interrupt */
  82. rt_interrupt_leave();
  83. }
  84. void rt_hw_cpu_reset(void)
  85. {
  86. SYS_UnlockReg();
  87. SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
  88. }