at91_mci.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913
  1. /*
  2. * File : at91_mci.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-07-25 weety first version
  13. */
  14. #include <rtthread.h>
  15. #include <rthw.h>
  16. #include <drivers/mmcsd_core.h>
  17. #include <at91sam926x.h>
  18. #include "at91_mci.h"
  19. #define USE_SLOT_B
  20. //#define RT_MCI_DBG
  21. #ifdef RT_MCI_DBG
  22. #define mci_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
  23. #else
  24. #define mci_dbg(fmt, ...)
  25. #endif
  26. #define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31))
  27. extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
  28. extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
  29. #define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
  30. | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
  31. | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
  32. #define at91_mci_read(reg) readl(AT91SAM9260_BASE_MCI + (reg))
  33. #define at91_mci_write(reg, val) writel((val), AT91SAM9260_BASE_MCI + (reg))
  34. #define REQ_ST_INIT (1U << 0)
  35. #define REQ_ST_CMD (1U << 1)
  36. #define REQ_ST_STOP (1U << 2)
  37. struct at91_mci {
  38. struct rt_mmcsd_host *host;
  39. struct rt_mmcsd_req *req;
  40. struct rt_mmcsd_cmd *cmd;
  41. struct rt_timer timer;
  42. //struct rt_semaphore sem_ack;
  43. rt_uint32_t *buf;
  44. rt_uint32_t current_status;
  45. };
  46. /*
  47. * Reset the controller and restore most of the state
  48. */
  49. static void at91_reset_host()
  50. {
  51. rt_uint32_t mr;
  52. rt_uint32_t sdcr;
  53. rt_uint32_t dtor;
  54. rt_uint32_t imr;
  55. rt_uint32_t level;
  56. level = rt_hw_interrupt_disable();
  57. imr = at91_mci_read(AT91_MCI_IMR);
  58. at91_mci_write(AT91_MCI_IDR, 0xffffffff);
  59. /* save current state */
  60. mr = at91_mci_read(AT91_MCI_MR) & 0x7fff;
  61. sdcr = at91_mci_read(AT91_MCI_SDCR);
  62. dtor = at91_mci_read(AT91_MCI_DTOR);
  63. /* reset the controller */
  64. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
  65. /* restore state */
  66. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
  67. at91_mci_write(AT91_MCI_MR, mr);
  68. at91_mci_write(AT91_MCI_SDCR, sdcr);
  69. at91_mci_write(AT91_MCI_DTOR, dtor);
  70. at91_mci_write(AT91_MCI_IER, imr);
  71. /* make sure sdio interrupts will fire */
  72. at91_mci_read(AT91_MCI_SR);
  73. rt_hw_interrupt_enable(level);
  74. }
  75. /*
  76. * Enable the controller
  77. */
  78. static void at91_mci_enable()
  79. {
  80. rt_uint32_t mr;
  81. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
  82. at91_mci_write(AT91_MCI_IDR, 0xffffffff);
  83. at91_mci_write(AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
  84. mr = AT91_MCI_PDCMODE | 0x34a;
  85. mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
  86. at91_mci_write(AT91_MCI_MR, mr);
  87. /* use Slot A or B (only one at same time) */
  88. at91_mci_write(AT91_MCI_SDCR, 1); /* use slot b */
  89. }
  90. /*
  91. * Disable the controller
  92. */
  93. static void at91_mci_disable()
  94. {
  95. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
  96. }
  97. static void at91_timeout_timer(void *data)
  98. {
  99. struct at91_mci *mci;
  100. mci = (struct at91_mci *)data;
  101. if (mci->req)
  102. {
  103. rt_kprintf("Timeout waiting end of packet\n");
  104. if (mci->current_status == REQ_ST_CMD)
  105. {
  106. if (mci->req->cmd && mci->req->data)
  107. {
  108. mci->req->data->err = -RT_ETIMEOUT;
  109. }
  110. else
  111. {
  112. if (mci->req->cmd)
  113. mci->req->cmd->err = -RT_ETIMEOUT;
  114. }
  115. }
  116. else if (mci->current_status == REQ_ST_STOP)
  117. {
  118. mci->req->stop->err = -RT_ETIMEOUT;
  119. }
  120. at91_reset_host();
  121. mmcsd_req_complete(mci->host);
  122. }
  123. }
  124. /*
  125. * Prepare a dma read
  126. */
  127. static void at91_mci_init_dma_read(struct at91_mci *mci)
  128. {
  129. rt_uint8_t i;
  130. struct rt_mmcsd_cmd *cmd;
  131. struct rt_mmcsd_data *data;
  132. rt_uint32_t length;
  133. mci_dbg("pre dma read\n");
  134. cmd = mci->cmd;
  135. if (!cmd)
  136. {
  137. mci_dbg("no command\n");
  138. return;
  139. }
  140. data = cmd->data;
  141. if (!data)
  142. {
  143. mci_dbg("no data\n");
  144. return;
  145. }
  146. for (i = 0; i < 1; i++)
  147. {
  148. /* Check to see if this needs filling */
  149. if (i == 0)
  150. {
  151. if (at91_mci_read(AT91_PDC_RCR) != 0)
  152. {
  153. mci_dbg("Transfer active in current\n");
  154. continue;
  155. }
  156. }
  157. else {
  158. if (at91_mci_read(AT91_PDC_RNCR) != 0)
  159. {
  160. mci_dbg("Transfer active in next\n");
  161. continue;
  162. }
  163. }
  164. length = data->blksize * data->blks;
  165. mci_dbg("dma address = %08X, length = %d\n", data->buf, length);
  166. if (i == 0)
  167. {
  168. at91_mci_write(AT91_PDC_RPR, (rt_uint32_t)(data->buf));
  169. at91_mci_write(AT91_PDC_RCR, (data->blksize & 0x3) ? length : length / 4);
  170. }
  171. else
  172. {
  173. at91_mci_write(AT91_PDC_RNPR, (rt_uint32_t)(data->buf));
  174. at91_mci_write(AT91_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4);
  175. }
  176. }
  177. mci_dbg("pre dma read done\n");
  178. }
  179. /*
  180. * Send a command
  181. */
  182. static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd)
  183. {
  184. rt_uint32_t cmdr, mr;
  185. rt_uint32_t block_length;
  186. struct rt_mmcsd_data *data = cmd->data;
  187. struct rt_mmcsd_host *host = mci->host;
  188. rt_uint32_t blocks;
  189. rt_uint32_t ier = 0;
  190. rt_uint32_t length;
  191. mci->cmd = cmd;
  192. /* Needed for leaving busy state before CMD1 */
  193. if ((at91_mci_read(AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->cmd_code == 1))
  194. {
  195. mci_dbg("Clearing timeout\n");
  196. at91_mci_write(AT91_MCI_ARGR, 0);
  197. at91_mci_write(AT91_MCI_CMDR, AT91_MCI_OPDCMD);
  198. while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
  199. {
  200. /* spin */
  201. mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91_MCI_SR));
  202. }
  203. }
  204. cmdr = cmd->cmd_code;
  205. if (resp_type(cmd) == RESP_NONE)
  206. cmdr |= AT91_MCI_RSPTYP_NONE;
  207. else
  208. {
  209. /* if a response is expected then allow maximum response latancy */
  210. cmdr |= AT91_MCI_MAXLAT;
  211. /* set 136 bit response for R2, 48 bit response otherwise */
  212. if (resp_type(cmd) == RESP_R2)
  213. cmdr |= AT91_MCI_RSPTYP_136;
  214. else
  215. cmdr |= AT91_MCI_RSPTYP_48;
  216. }
  217. if (data)
  218. {
  219. block_length = data->blksize;
  220. blocks = data->blks;
  221. /* always set data start - also set direction flag for read */
  222. if (data->flags & DATA_DIR_READ)
  223. cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
  224. else if (data->flags & DATA_DIR_WRITE)
  225. cmdr |= AT91_MCI_TRCMD_START;
  226. if (data->flags & DATA_STREAM)
  227. cmdr |= AT91_MCI_TRTYP_STREAM;
  228. if (data->blks > 1)
  229. cmdr |= AT91_MCI_TRTYP_MULTIPLE;
  230. }
  231. else
  232. {
  233. block_length = 0;
  234. blocks = 0;
  235. }
  236. /*if (cmd->cmd_code == GO_IDLE_STATE)
  237. {
  238. cmdr |= AT91_MCI_SPCMD_INIT;
  239. }*/
  240. if (cmd->cmd_code == STOP_TRANSMISSION)
  241. cmdr |= AT91_MCI_TRCMD_STOP;
  242. if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN)
  243. cmdr |= AT91_MCI_OPDCMD;
  244. /*
  245. * Set the arguments and send the command
  246. */
  247. mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
  248. cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91_MCI_MR));
  249. if (!data)
  250. {
  251. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTDIS | AT91_PDC_RXTDIS);
  252. at91_mci_write(AT91_PDC_RPR, 0);
  253. at91_mci_write(AT91_PDC_RCR, 0);
  254. at91_mci_write(AT91_PDC_RNPR, 0);
  255. at91_mci_write(AT91_PDC_RNCR, 0);
  256. at91_mci_write(AT91_PDC_TPR, 0);
  257. at91_mci_write(AT91_PDC_TCR, 0);
  258. at91_mci_write(AT91_PDC_TNPR, 0);
  259. at91_mci_write(AT91_PDC_TNCR, 0);
  260. ier = AT91_MCI_CMDRDY;
  261. }
  262. else
  263. {
  264. /* zero block length and PDC mode */
  265. mr = at91_mci_read(AT91_MCI_MR) & 0x5fff;
  266. mr |= (data->blksize & 0x3) ? AT91_MCI_PDCFBYTE : 0;
  267. mr |= (block_length << 16);
  268. mr |= AT91_MCI_PDCMODE;
  269. at91_mci_write(AT91_MCI_MR, mr);
  270. at91_mci_write(AT91_MCI_BLKR,
  271. AT91_MCI_BLKR_BCNT(blocks) |
  272. AT91_MCI_BLKR_BLKLEN(block_length));
  273. /*
  274. * Disable the PDC controller
  275. */
  276. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
  277. if (cmdr & AT91_MCI_TRCMD_START)
  278. {
  279. if (cmdr & AT91_MCI_TRDIR)
  280. {
  281. /*
  282. * Handle a read
  283. */
  284. mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
  285. at91_mci_init_dma_read(mci);
  286. ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
  287. }
  288. else
  289. {
  290. /*
  291. * Handle a write
  292. */
  293. length = block_length * blocks;
  294. /*
  295. * at91mci MCI1 rev2xx Data Write Operation and
  296. * number of bytes erratum
  297. */
  298. if (length < 12)
  299. {
  300. length = 12;
  301. mci->buf = rt_malloc(length);
  302. if (!mci->buf)
  303. {
  304. rt_kprintf("rt alloc tx buffer failed\n");
  305. cmd->err = -RT_ENOMEM;
  306. mmcsd_req_complete(mci->host);
  307. return;
  308. }
  309. rt_memset(mci->buf, 0, 12);
  310. rt_memcpy(mci->buf, data->buf, length);
  311. mmu_clean_dcache((rt_uint32_t)mci->buf, length);
  312. at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(mci->buf));
  313. at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
  314. length : length / 4);
  315. }
  316. else
  317. {
  318. mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks);
  319. at91_mci_write(AT91_PDC_TPR, (rt_uint32_t)(data->buf));
  320. at91_mci_write(AT91_PDC_TCR, (data->blksize & 0x3) ?
  321. length : length / 4);
  322. }
  323. mci_dbg("Transmitting %d bytes\n", length);
  324. ier = AT91_MCI_CMDRDY;
  325. }
  326. }
  327. }
  328. /*
  329. * Send the command and then enable the PDC - not the other way round as
  330. * the data sheet says
  331. */
  332. at91_mci_write(AT91_MCI_ARGR, cmd->arg);
  333. at91_mci_write(AT91_MCI_CMDR, cmdr);
  334. if (cmdr & AT91_MCI_TRCMD_START)
  335. {
  336. if (cmdr & AT91_MCI_TRDIR)
  337. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTEN);
  338. }
  339. /* Enable selected interrupts */
  340. at91_mci_write(AT91_MCI_IER, AT91_MCI_ERRORS | ier);
  341. }
  342. /*
  343. * Process the next step in the request
  344. */
  345. static void at91_mci_process_next(struct at91_mci *mci)
  346. {
  347. if (mci->current_status == REQ_ST_INIT)
  348. {
  349. mci->current_status = REQ_ST_CMD;
  350. at91_mci_send_command(mci, mci->req->cmd);
  351. }
  352. else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop)
  353. {
  354. mci->current_status = REQ_ST_STOP;
  355. at91_mci_send_command(mci, mci->req->stop);
  356. }
  357. else
  358. {
  359. rt_timer_stop(&mci->timer);
  360. /* the mci controller hangs after some transfers,
  361. * and the workaround is to reset it after each transfer.
  362. */
  363. at91_reset_host();
  364. mmcsd_req_complete(mci->host);
  365. }
  366. }
  367. /*
  368. * Handle an MMC request
  369. */
  370. static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  371. {
  372. rt_uint32_t timeout = RT_TICK_PER_SECOND;
  373. struct at91_mci *mci = host->private_data;
  374. mci->req = req;
  375. mci->current_status = REQ_ST_INIT;
  376. rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout);
  377. rt_timer_start(&mci->timer);
  378. at91_mci_process_next(mci);
  379. }
  380. /*
  381. * Handle transmitted data
  382. */
  383. static void at91_mci_handle_transmitted(struct at91_mci *mci)
  384. {
  385. struct rt_mmcsd_cmd *cmd;
  386. struct rt_mmcsd_data *data;
  387. mci_dbg("Handling the transmit\n");
  388. /* Disable the transfer */
  389. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
  390. /* Now wait for cmd ready */
  391. at91_mci_write(AT91_MCI_IDR, AT91_MCI_TXBUFE);
  392. cmd = mci->cmd;
  393. if (!cmd) return;
  394. data = cmd->data;
  395. if (!data) return;
  396. if (data->blks > 1)
  397. {
  398. mci_dbg("multiple write : wait for BLKE...\n");
  399. at91_mci_write(AT91_MCI_IER, AT91_MCI_BLKE);
  400. } else
  401. at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
  402. }
  403. /*
  404. * Handle after a dma read
  405. */
  406. static void at91_mci_post_dma_read(struct at91_mci *mci)
  407. {
  408. struct rt_mmcsd_cmd *cmd;
  409. struct rt_mmcsd_data *data;
  410. mci_dbg("post dma read\n");
  411. cmd = mci->cmd;
  412. if (!cmd)
  413. {
  414. mci_dbg("no command\n");
  415. return;
  416. }
  417. data = cmd->data;
  418. if (!data)
  419. {
  420. mci_dbg("no data\n");
  421. return;
  422. }
  423. at91_mci_write(AT91_MCI_IDR, AT91_MCI_ENDRX);
  424. at91_mci_write(AT91_MCI_IER, AT91_MCI_RXBUFF);
  425. mci_dbg("post dma read done\n");
  426. }
  427. /*Handle after command sent ready*/
  428. static int at91_mci_handle_cmdrdy(struct at91_mci *mci)
  429. {
  430. if (!mci->cmd)
  431. return 1;
  432. else if (!mci->cmd->data)
  433. {
  434. if (mci->current_status == REQ_ST_STOP)
  435. {
  436. /*After multi block write, we must wait for NOTBUSY*/
  437. at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
  438. }
  439. else return 1;
  440. }
  441. else if (mci->cmd->data->flags & DATA_DIR_WRITE)
  442. {
  443. /*After sendding multi-block-write command, start DMA transfer*/
  444. at91_mci_write(AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
  445. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_TXTEN);
  446. }
  447. /* command not completed, have to wait */
  448. return 0;
  449. }
  450. /*
  451. * Handle a command that has been completed
  452. */
  453. static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status)
  454. {
  455. struct rt_mmcsd_cmd *cmd = mci->cmd;
  456. struct rt_mmcsd_data *data = cmd->data;
  457. at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
  458. cmd->resp[0] = at91_mci_read(AT91_MCI_RSPR(0));
  459. cmd->resp[1] = at91_mci_read(AT91_MCI_RSPR(1));
  460. cmd->resp[2] = at91_mci_read(AT91_MCI_RSPR(2));
  461. cmd->resp[3] = at91_mci_read(AT91_MCI_RSPR(3));
  462. if (mci->buf)
  463. {
  464. //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks);
  465. rt_free(mci->buf);
  466. mci->buf = RT_NULL;
  467. }
  468. mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n",
  469. status, at91_mci_read(AT91_MCI_SR),
  470. cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
  471. if (status & AT91_MCI_ERRORS)
  472. {
  473. if ((status & AT91_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4)))
  474. {
  475. cmd->err = 0;
  476. }
  477. else
  478. {
  479. if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE))
  480. {
  481. if (data)
  482. {
  483. if (status & AT91_MCI_DTOE)
  484. data->err = -RT_ETIMEOUT;
  485. else if (status & AT91_MCI_DCRCE)
  486. data->err = -RT_ERROR;
  487. }
  488. }
  489. else
  490. {
  491. if (status & AT91_MCI_RTOE)
  492. cmd->err = -RT_ETIMEOUT;
  493. else if (status & AT91_MCI_RCRCE)
  494. cmd->err = -RT_ERROR;
  495. else
  496. cmd->err = -RT_ERROR;
  497. }
  498. rt_kprintf("error detected and set to %d/%d (cmd = %d)\n",
  499. cmd->err, data ? data->err : 0,
  500. cmd->cmd_code);
  501. }
  502. }
  503. else
  504. cmd->err = 0;
  505. at91_mci_process_next(mci);
  506. }
  507. /*
  508. * Handle an interrupt
  509. */
  510. static void at91_mci_irq(int irq, void *param)
  511. {
  512. struct at91_mci *mci = (struct at91_mci *)param;
  513. rt_int32_t completed = 0;
  514. rt_uint32_t int_status, int_mask;
  515. int_status = at91_mci_read(AT91_MCI_SR);
  516. int_mask = at91_mci_read(AT91_MCI_IMR);
  517. mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
  518. int_status & int_mask);
  519. int_status = int_status & int_mask;
  520. if (int_status & AT91_MCI_ERRORS)
  521. {
  522. completed = 1;
  523. if (int_status & AT91_MCI_UNRE)
  524. mci_dbg("MMC: Underrun error\n");
  525. if (int_status & AT91_MCI_OVRE)
  526. mci_dbg("MMC: Overrun error\n");
  527. if (int_status & AT91_MCI_DTOE)
  528. mci_dbg("MMC: Data timeout\n");
  529. if (int_status & AT91_MCI_DCRCE)
  530. mci_dbg("MMC: CRC error in data\n");
  531. if (int_status & AT91_MCI_RTOE)
  532. mci_dbg("MMC: Response timeout\n");
  533. if (int_status & AT91_MCI_RENDE)
  534. mci_dbg("MMC: Response end bit error\n");
  535. if (int_status & AT91_MCI_RCRCE)
  536. mci_dbg("MMC: Response CRC error\n");
  537. if (int_status & AT91_MCI_RDIRE)
  538. mci_dbg("MMC: Response direction error\n");
  539. if (int_status & AT91_MCI_RINDE)
  540. mci_dbg("MMC: Response index error\n");
  541. }
  542. else
  543. {
  544. /* Only continue processing if no errors */
  545. if (int_status & AT91_MCI_TXBUFE)
  546. {
  547. mci_dbg("TX buffer empty\n");
  548. at91_mci_handle_transmitted(mci);
  549. }
  550. if (int_status & AT91_MCI_ENDRX)
  551. {
  552. mci_dbg("ENDRX\n");
  553. at91_mci_post_dma_read(mci);
  554. }
  555. if (int_status & AT91_MCI_RXBUFF)
  556. {
  557. mci_dbg("RX buffer full\n");
  558. at91_mci_write(AT91_PDC_PTCR, AT91_PDC_RXTDIS | AT91_PDC_TXTDIS);
  559. at91_mci_write(AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
  560. completed = 1;
  561. }
  562. if (int_status & AT91_MCI_ENDTX)
  563. mci_dbg("Transmit has ended\n");
  564. if (int_status & AT91_MCI_NOTBUSY)
  565. {
  566. mci_dbg("Card is ready\n");
  567. //at91_mci_update_bytes_xfered(host);
  568. completed = 1;
  569. }
  570. if (int_status & AT91_MCI_DTIP)
  571. mci_dbg("Data transfer in progress\n");
  572. if (int_status & AT91_MCI_BLKE)
  573. {
  574. mci_dbg("Block transfer has ended\n");
  575. if (mci->req->data && mci->req->data->blks > 1)
  576. {
  577. /* multi block write : complete multi write
  578. * command and send stop */
  579. completed = 1;
  580. }
  581. else
  582. {
  583. at91_mci_write(AT91_MCI_IER, AT91_MCI_NOTBUSY);
  584. }
  585. }
  586. /*if (int_status & AT91_MCI_SDIOIRQA)
  587. rt_mmcsd_signal_sdio_irq(host->mmc);*/
  588. if (int_status & AT91_MCI_SDIOIRQB)
  589. sdio_irq_wakeup(mci->host);
  590. if (int_status & AT91_MCI_TXRDY)
  591. mci_dbg("Ready to transmit\n");
  592. if (int_status & AT91_MCI_RXRDY)
  593. mci_dbg("Ready to receive\n");
  594. if (int_status & AT91_MCI_CMDRDY)
  595. {
  596. mci_dbg("Command ready\n");
  597. completed = at91_mci_handle_cmdrdy(mci);
  598. }
  599. }
  600. if (completed)
  601. {
  602. mci_dbg("Completed command\n");
  603. at91_mci_write(AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
  604. at91_mci_completed_command(mci, int_status);
  605. }
  606. else
  607. at91_mci_write(AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
  608. }
  609. /*
  610. * Set the IOCFG
  611. */
  612. static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
  613. {
  614. rt_uint32_t clkdiv;
  615. //struct at91_mci *mci = host->private_data;
  616. rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck"));
  617. if (io_cfg->clock == 0)
  618. {
  619. /* Disable the MCI controller */
  620. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIDIS);
  621. clkdiv = 0;
  622. }
  623. else
  624. {
  625. /* Enable the MCI controller */
  626. at91_mci_write(AT91_MCI_CR, AT91_MCI_MCIEN);
  627. if ((at91_master_clock % (io_cfg->clock * 2)) == 0)
  628. clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1;
  629. else
  630. clkdiv = (at91_master_clock / io_cfg->clock) / 2;
  631. mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv,
  632. at91_master_clock / (2 * (clkdiv + 1)));
  633. }
  634. if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4)
  635. {
  636. mci_dbg("MMC: Setting controller bus width to 4\n");
  637. at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
  638. }
  639. else
  640. {
  641. mci_dbg("MMC: Setting controller bus width to 1\n");
  642. at91_mci_write(AT91_MCI_SDCR, at91_mci_read(AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
  643. }
  644. /* Set the clock divider */
  645. at91_mci_write(AT91_MCI_MR, (at91_mci_read(AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
  646. /* maybe switch power to the card */
  647. switch (io_cfg->power_mode)
  648. {
  649. case MMCSD_POWER_OFF:
  650. break;
  651. case MMCSD_POWER_UP:
  652. break;
  653. case MMCSD_POWER_ON:
  654. /*at91_mci_write(AT91_MCI_ARGR, 0);
  655. at91_mci_write(AT91_MCI_CMDR, 0|AT91_MCI_SPCMD_INIT|AT91_MCI_OPDCMD);
  656. mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91_MCI_SR));
  657. while (!(at91_mci_read(AT91_MCI_SR) & AT91_MCI_CMDRDY))
  658. {
  659. }
  660. mci_dbg("at91 mci power on\n");*/
  661. break;
  662. default:
  663. rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode);
  664. break;
  665. }
  666. }
  667. static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable)
  668. {
  669. at91_mci_write(enable ? AT91_MCI_IER : AT91_MCI_IDR, AT91_MCI_SDIOIRQB);
  670. }
  671. static const struct rt_mmcsd_host_ops ops = {
  672. at91_mci_request,
  673. at91_mci_set_iocfg,
  674. RT_NULL,
  675. at91_mci_enable_sdio_irq,
  676. };
  677. void at91_mci_detect(int irq, void *param)
  678. {
  679. rt_kprintf("mmcsd gpio detected\n");
  680. }
  681. static void mci_gpio_init()
  682. {
  683. #ifdef USE_SLOT_B
  684. at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
  685. at91_sys_write(AT91_PIOA + PIO_PUDR, (1 << 8));
  686. at91_sys_write(AT91_PIOA + PIO_BSR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5));
  687. at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 8));
  688. at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8));
  689. at91_sys_write(AT91_PIOA + PIO_IDR, (1 << 6)|(1 << 7));
  690. at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7));
  691. at91_sys_write(AT91_PIOA + PIO_ODR, (1 << 6)|(1 << 7));
  692. at91_sys_write(AT91_PIOA + PIO_PER, (1 << 6)|(1 << 7));
  693. #else
  694. at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11));
  695. at91_sys_write(AT91_PIOA + PIO_ASR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
  696. at91_sys_write(AT91_PIOA + PIO_PDR, (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8));
  697. #endif
  698. }
  699. rt_int32_t at91_mci_init(void)
  700. {
  701. struct rt_mmcsd_host *host;
  702. struct at91_mci *mci;
  703. host = mmcsd_alloc_host();
  704. if (!host)
  705. {
  706. return -RT_ERROR;
  707. }
  708. mci = rt_malloc(sizeof(struct at91_mci));
  709. if (!mci)
  710. {
  711. rt_kprintf("alloc mci failed\n");
  712. goto err;
  713. }
  714. rt_memset(mci, 0, sizeof(struct at91_mci));
  715. host->ops = &ops;
  716. host->freq_min = 375000;
  717. host->freq_max = 25000000;
  718. host->valid_ocr = VDD_32_33 | VDD_33_34;
  719. host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \
  720. MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ;
  721. host->max_seg_size = 65535;
  722. host->max_dma_segs = 2;
  723. host->max_blk_size = 512;
  724. host->max_blk_count = 4096;
  725. mci->host = host;
  726. mci_gpio_init();
  727. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); //enable MCI clock
  728. at91_mci_disable();
  729. at91_mci_enable();
  730. /* instal interrupt */
  731. rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq,
  732. (void *)mci, "MMC");
  733. rt_hw_interrupt_umask(AT91SAM9260_ID_MCI);
  734. rt_hw_interrupt_install(gpio_to_irq(AT91_PIN_PA7),
  735. at91_mci_detect, RT_NULL, "MMC_DETECT");
  736. rt_hw_interrupt_umask(gpio_to_irq(AT91_PIN_PA7));
  737. rt_timer_init(&mci->timer, "mci_timer",
  738. at91_timeout_timer,
  739. mci,
  740. RT_TICK_PER_SECOND,
  741. RT_TIMER_FLAG_PERIODIC);
  742. //rt_timer_start(&mci->timer);
  743. //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
  744. host->private_data = mci;
  745. mmcsd_change(host);
  746. return 0;
  747. err:
  748. mmcsd_free_host(host);
  749. return -RT_ENOMEM;
  750. }
  751. #include "finsh.h"
  752. FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init);
  753. void mci_dump(void)
  754. {
  755. rt_uint32_t i;
  756. rt_kprintf("PIOA_PSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PSR));
  757. rt_kprintf("PIOA_ABSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_ABSR));
  758. rt_kprintf("PIOA_PUSR=0x%08x\n", at91_sys_read(AT91_PIOA+PIO_PUSR));
  759. for (i = 0; i <= 0x4c; i += 4) {
  760. rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i));
  761. }
  762. }
  763. FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci);