drv_gpio.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597
  1. /*
  2. * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the License); you may
  7. * not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. *
  18. * Change Logs:
  19. * Date Author Notes
  20. * 2019-01-23 wangyq the first version
  21. * 2019-11-01 wangyq update libraries
  22. * 2021-04-20 liuhy the second version
  23. */
  24. #include "board.h"
  25. #include "drv_gpio.h"
  26. /*管脚映射在 es_conf_info_map.h 的 pins[] 中*/
  27. #ifdef RT_USING_PIN
  28. struct pin_irq_map
  29. {
  30. rt_uint16_t pinbit;
  31. IRQn_Type irqno;
  32. };
  33. static const struct pin_irq_map pin_irq_map[] =
  34. {
  35. {GPIO_PIN_0, EXTI0_3_IRQn},
  36. {GPIO_PIN_1, EXTI0_3_IRQn},
  37. {GPIO_PIN_2, EXTI0_3_IRQn},
  38. {GPIO_PIN_3, EXTI0_3_IRQn},
  39. {GPIO_PIN_4, EXTI4_7_IRQn},
  40. {GPIO_PIN_5, EXTI4_7_IRQn},
  41. {GPIO_PIN_6, EXTI4_7_IRQn},
  42. {GPIO_PIN_7, EXTI4_7_IRQn},
  43. {GPIO_PIN_8, EXTI8_11_IRQn},
  44. {GPIO_PIN_9, EXTI8_11_IRQn},
  45. {GPIO_PIN_10, EXTI8_11_IRQn},
  46. {GPIO_PIN_11, EXTI8_11_IRQn},
  47. {GPIO_PIN_12, EXTI12_15_IRQn},
  48. {GPIO_PIN_13, EXTI12_15_IRQn},
  49. {GPIO_PIN_14, EXTI12_15_IRQn},
  50. {GPIO_PIN_15, EXTI12_15_IRQn},
  51. };
  52. struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
  53. {
  54. { -1, 0, RT_NULL, RT_NULL},
  55. { -1, 0, RT_NULL, RT_NULL},
  56. { -1, 0, RT_NULL, RT_NULL},
  57. { -1, 0, RT_NULL, RT_NULL},
  58. { -1, 0, RT_NULL, RT_NULL},
  59. { -1, 0, RT_NULL, RT_NULL},
  60. { -1, 0, RT_NULL, RT_NULL},
  61. { -1, 0, RT_NULL, RT_NULL},
  62. { -1, 0, RT_NULL, RT_NULL},
  63. { -1, 0, RT_NULL, RT_NULL},
  64. { -1, 0, RT_NULL, RT_NULL},
  65. { -1, 0, RT_NULL, RT_NULL},
  66. { -1, 0, RT_NULL, RT_NULL},
  67. { -1, 0, RT_NULL, RT_NULL},
  68. { -1, 0, RT_NULL, RT_NULL},
  69. { -1, 0, RT_NULL, RT_NULL},
  70. };
  71. #ifdef ES_CONF_EXTI_IRQ_0
  72. RT_WEAK void irq_pin0_callback(void* arg)
  73. {
  74. rt_kprintf("\r\nEXTI 0\r\n");
  75. }
  76. #endif
  77. #ifdef ES_CONF_EXTI_IRQ_1
  78. RT_WEAK void irq_pin1_callback(void* arg)
  79. {
  80. rt_kprintf("\r\nEXTI 1\r\n");
  81. }
  82. #endif
  83. #ifdef ES_CONF_EXTI_IRQ_2
  84. RT_WEAK void irq_pin2_callback(void* arg)
  85. {
  86. rt_kprintf("\r\nEXTI 2\r\n");
  87. }
  88. #endif
  89. #ifdef ES_CONF_EXTI_IRQ_3
  90. RT_WEAK void irq_pin3_callback(void* arg)
  91. {
  92. rt_kprintf("\r\nEXTI 3\r\n");
  93. }
  94. #endif
  95. #ifdef ES_CONF_EXTI_IRQ_4
  96. RT_WEAK void irq_pin4_callback(void* arg)
  97. {
  98. rt_kprintf("\r\nEXTI 4\r\n");
  99. }
  100. #endif
  101. #ifdef ES_CONF_EXTI_IRQ_5
  102. RT_WEAK void irq_pin5_callback(void* arg)
  103. {
  104. rt_kprintf("\r\nEXTI 5\r\n");
  105. }
  106. #endif
  107. #ifdef ES_CONF_EXTI_IRQ_6
  108. RT_WEAK void irq_pin6_callback(void* arg)
  109. {
  110. rt_kprintf("\r\nEXTI 6\r\n");
  111. }
  112. #endif
  113. #ifdef ES_CONF_EXTI_IRQ_7
  114. RT_WEAK void irq_pin7_callback(void* arg)
  115. {
  116. rt_kprintf("\r\nEXTI 7\r\n");
  117. }
  118. #endif
  119. #ifdef ES_CONF_EXTI_IRQ_8
  120. RT_WEAK void irq_pin8_callback(void* arg)
  121. {
  122. rt_kprintf("\r\nEXTI 8\r\n");
  123. }
  124. #endif
  125. #ifdef ES_CONF_EXTI_IRQ_9
  126. RT_WEAK void irq_pin9_callback(void* arg)
  127. {
  128. rt_kprintf("\r\nEXTI 9\r\n");
  129. }
  130. #endif
  131. #ifdef ES_CONF_EXTI_IRQ_10
  132. RT_WEAK void irq_pin10_callback(void* arg)
  133. {
  134. rt_kprintf("\r\nEXTI 10\r\n");
  135. }
  136. #endif
  137. #ifdef ES_CONF_EXTI_IRQ_11
  138. RT_WEAK void irq_pin11_callback(void* arg)
  139. {
  140. rt_kprintf("\r\nEXTI 11\r\n");
  141. }
  142. #endif
  143. #ifdef ES_CONF_EXTI_IRQ_12
  144. RT_WEAK void irq_pin12_callback(void* arg)
  145. {
  146. rt_kprintf("\r\nEXTI 12\r\n");
  147. }
  148. #endif
  149. #ifdef ES_CONF_EXTI_IRQ_13
  150. RT_WEAK void irq_pin13_callback(void* arg)
  151. {
  152. rt_kprintf("\r\nEXTI 13\r\n");
  153. }
  154. #endif
  155. #ifdef ES_CONF_EXTI_IRQ_14
  156. RT_WEAK void irq_pin14_callback(void* arg)
  157. {
  158. rt_kprintf("\r\nEXTI 14\r\n");
  159. }
  160. #endif
  161. #ifdef ES_CONF_EXTI_IRQ_15
  162. RT_WEAK void irq_pin15_callback(void* arg)
  163. {
  164. rt_kprintf("\r\nEXTI 15\r\n");
  165. }
  166. #endif
  167. #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
  168. const struct pin_index *get_pin(uint8_t pin)
  169. {
  170. const struct pin_index *index;
  171. if (pin < ITEM_NUM(pins))
  172. {
  173. index = &pins[pin];
  174. if (index->index == -1)
  175. index = RT_NULL;
  176. }
  177. else
  178. {
  179. index = RT_NULL;
  180. }
  181. return index;
  182. };
  183. void es32f0_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  184. {
  185. const struct pin_index *index;
  186. index = get_pin(pin);
  187. if (index == RT_NULL)
  188. {
  189. return;
  190. }
  191. ald_gpio_write_pin(index->gpio, index->pin, value);
  192. }
  193. int es32f0_pin_read(rt_device_t dev, rt_base_t pin)
  194. {
  195. int value;
  196. const struct pin_index *index;
  197. value = PIN_LOW;
  198. index = get_pin(pin);
  199. if (index == RT_NULL)
  200. {
  201. return value;
  202. }
  203. value = ald_gpio_read_pin(index->gpio, index->pin);
  204. return value;
  205. }
  206. void es32f0_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  207. {
  208. const struct pin_index *index;
  209. gpio_init_t gpio_initstruct;
  210. index = get_pin(pin);
  211. if (index == RT_NULL)
  212. {
  213. return;
  214. }
  215. /* Configure GPIO_InitStructure */
  216. gpio_initstruct.mode = GPIO_MODE_OUTPUT;
  217. gpio_initstruct.func = GPIO_FUNC_1;
  218. gpio_initstruct.odrv = GPIO_OUT_DRIVE_NORMAL;
  219. gpio_initstruct.type = GPIO_TYPE_CMOS;
  220. gpio_initstruct.pupd = GPIO_FLOATING;
  221. gpio_initstruct.odos = GPIO_PUSH_PULL;
  222. if (mode == PIN_MODE_OUTPUT)
  223. {
  224. /* output setting */
  225. gpio_initstruct.mode = GPIO_MODE_OUTPUT;
  226. gpio_initstruct.pupd = GPIO_FLOATING;
  227. }
  228. else if (mode == PIN_MODE_INPUT)
  229. {
  230. /* input setting: not pull. */
  231. gpio_initstruct.mode = GPIO_MODE_INPUT;
  232. gpio_initstruct.pupd = GPIO_FLOATING;
  233. }
  234. else if (mode == PIN_MODE_INPUT_PULLUP)
  235. {
  236. /* input setting: pull up. */
  237. gpio_initstruct.mode = GPIO_MODE_INPUT;
  238. gpio_initstruct.pupd = GPIO_PUSH_UP;
  239. }
  240. else if (mode == PIN_MODE_INPUT_PULLDOWN)
  241. {
  242. /* input setting: pull down. */
  243. gpio_initstruct.mode = GPIO_MODE_INPUT;
  244. gpio_initstruct.pupd = GPIO_PUSH_DOWN;
  245. }
  246. else if (mode == PIN_MODE_OUTPUT_OD)
  247. {
  248. /* output setting: od. */
  249. gpio_initstruct.mode = GPIO_MODE_OUTPUT;
  250. gpio_initstruct.pupd = GPIO_FLOATING;
  251. gpio_initstruct.odos = GPIO_OPEN_DRAIN;
  252. }
  253. ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
  254. }
  255. rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
  256. {
  257. rt_int32_t mapindex = gpio_pin & 0x00FF;
  258. if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
  259. {
  260. return RT_NULL;
  261. }
  262. return &pin_irq_map[mapindex];
  263. };
  264. rt_err_t es32f0_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  265. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  266. {
  267. const struct pin_index *index;
  268. rt_base_t level;
  269. rt_int32_t irqindex;
  270. index = get_pin(pin);
  271. if (index == RT_NULL)
  272. {
  273. return RT_ENOSYS;
  274. }
  275. /* pin no. convert to dec no. */
  276. for (irqindex = 0; irqindex < 16; irqindex++)
  277. {
  278. if ((0x01 << irqindex) == index->pin)
  279. {
  280. break;
  281. }
  282. }
  283. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  284. {
  285. return RT_ENOSYS;
  286. }
  287. level = rt_hw_interrupt_disable();
  288. if (pin_irq_hdr_tab[irqindex].pin == pin &&
  289. pin_irq_hdr_tab[irqindex].hdr == hdr &&
  290. pin_irq_hdr_tab[irqindex].mode == mode &&
  291. pin_irq_hdr_tab[irqindex].args == args)
  292. {
  293. rt_hw_interrupt_enable(level);
  294. return RT_EOK;
  295. }
  296. if (pin_irq_hdr_tab[irqindex].pin != -1)
  297. {
  298. rt_hw_interrupt_enable(level);
  299. return RT_EBUSY;
  300. }
  301. pin_irq_hdr_tab[irqindex].pin = pin;
  302. pin_irq_hdr_tab[irqindex].hdr = hdr;
  303. pin_irq_hdr_tab[irqindex].mode = mode;
  304. pin_irq_hdr_tab[irqindex].args = args;
  305. rt_hw_interrupt_enable(level);
  306. return RT_EOK;
  307. }
  308. rt_err_t es32f0_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
  309. {
  310. const struct pin_index *index;
  311. rt_base_t level;
  312. rt_int32_t irqindex = -1;
  313. index = get_pin(pin);
  314. if (index == RT_NULL)
  315. {
  316. return RT_ENOSYS;
  317. }
  318. irqindex = index->pin & 0x00FF;
  319. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  320. {
  321. return RT_ENOSYS;
  322. }
  323. level = rt_hw_interrupt_disable();
  324. if (pin_irq_hdr_tab[irqindex].pin == -1)
  325. {
  326. rt_hw_interrupt_enable(level);
  327. return RT_EOK;
  328. }
  329. pin_irq_hdr_tab[irqindex].pin = -1;
  330. pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
  331. pin_irq_hdr_tab[irqindex].mode = 0;
  332. pin_irq_hdr_tab[irqindex].args = RT_NULL;
  333. rt_hw_interrupt_enable(level);
  334. return RT_EOK;
  335. }
  336. rt_err_t es32f0_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  337. rt_uint32_t enabled)
  338. {
  339. const struct pin_index *index;
  340. const struct pin_irq_map *irqmap;
  341. rt_base_t level;
  342. rt_int32_t irqindex = -1;
  343. /* Configure GPIO_InitStructure & EXTI_InitStructure */
  344. gpio_init_t gpio_initstruct;
  345. exti_init_t exti_initstruct;
  346. exti_initstruct.filter = DISABLE;
  347. exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
  348. exti_initstruct.filter_time = 0x0;
  349. index = get_pin(pin);
  350. if (index == RT_NULL)
  351. {
  352. return RT_ENOSYS;
  353. }
  354. if (enabled == PIN_IRQ_ENABLE)
  355. {
  356. /* pin no. convert to dec no. */
  357. for (irqindex = 0; irqindex < 16; irqindex++)
  358. {
  359. if ((0x01 << irqindex) == index->pin)
  360. {
  361. break;
  362. }
  363. }
  364. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  365. {
  366. return RT_ENOSYS;
  367. }
  368. level = rt_hw_interrupt_disable();
  369. if (pin_irq_hdr_tab[irqindex].pin == -1)
  370. {
  371. rt_hw_interrupt_enable(level);
  372. return RT_ENOSYS;
  373. }
  374. irqmap = &pin_irq_map[irqindex];
  375. ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
  376. /* Configure GPIO_InitStructure */
  377. gpio_initstruct.mode = GPIO_MODE_INPUT;
  378. gpio_initstruct.func = GPIO_FUNC_1;
  379. switch (pin_irq_hdr_tab[irqindex].mode)
  380. {
  381. case PIN_IRQ_MODE_RISING:
  382. gpio_initstruct.pupd = GPIO_PUSH_DOWN;
  383. ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
  384. break;
  385. case PIN_IRQ_MODE_FALLING:
  386. gpio_initstruct.pupd = GPIO_PUSH_UP;
  387. ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
  388. break;
  389. case PIN_IRQ_MODE_RISING_FALLING:
  390. gpio_initstruct.pupd = GPIO_FLOATING;
  391. ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
  392. break;
  393. }
  394. ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
  395. NVIC_EnableIRQ(irqmap->irqno);
  396. rt_hw_interrupt_enable(level);
  397. }
  398. else if (enabled == PIN_IRQ_DISABLE)
  399. {
  400. irqmap = get_pin_irq_map(index->pin);
  401. if (irqmap == RT_NULL)
  402. {
  403. return RT_ENOSYS;
  404. }
  405. NVIC_DisableIRQ(irqmap->irqno);
  406. }
  407. else
  408. {
  409. return RT_ENOSYS;
  410. }
  411. return RT_EOK;
  412. }
  413. const static struct rt_pin_ops _es32f0_pin_ops =
  414. {
  415. es32f0_pin_mode,
  416. es32f0_pin_write,
  417. es32f0_pin_read,
  418. es32f0_pin_attach_irq,
  419. es32f0_pin_detach_irq,
  420. es32f0_pin_irq_enable,
  421. /*RT_NULL,*/
  422. };
  423. rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
  424. {
  425. uint16_t irqno;
  426. /* pin no. convert to dec no. */
  427. for (irqno = 0; irqno < 16; irqno++)
  428. {
  429. if ((0x01 << irqno) == GPIO_Pin)
  430. {
  431. break;
  432. }
  433. }
  434. if (irqno == 16)
  435. return;
  436. if (pin_irq_hdr_tab[irqno].hdr)
  437. {
  438. pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
  439. }
  440. }
  441. void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
  442. {
  443. if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
  444. {
  445. ald_gpio_exti_clear_flag_status(GPIO_Pin);
  446. pin_irq_hdr(GPIO_Pin);
  447. }
  448. }
  449. void EXTI0_3_Handler(void)
  450. {
  451. rt_interrupt_enter();
  452. GPIO_EXTI_Callback(GPIO_PIN_0);
  453. GPIO_EXTI_Callback(GPIO_PIN_1);
  454. GPIO_EXTI_Callback(GPIO_PIN_2);
  455. GPIO_EXTI_Callback(GPIO_PIN_3);
  456. rt_interrupt_leave();
  457. }
  458. void EXTI4_7_Handler(void)
  459. {
  460. rt_interrupt_enter();
  461. GPIO_EXTI_Callback(GPIO_PIN_4);
  462. GPIO_EXTI_Callback(GPIO_PIN_5);
  463. GPIO_EXTI_Callback(GPIO_PIN_6);
  464. GPIO_EXTI_Callback(GPIO_PIN_7);
  465. rt_interrupt_leave();
  466. }
  467. void EXTI8_11_Handler(void)
  468. {
  469. rt_interrupt_enter();
  470. GPIO_EXTI_Callback(GPIO_PIN_8);
  471. GPIO_EXTI_Callback(GPIO_PIN_9);
  472. GPIO_EXTI_Callback(GPIO_PIN_10);
  473. GPIO_EXTI_Callback(GPIO_PIN_11);
  474. rt_interrupt_leave();
  475. }
  476. void EXTI12_15_Handler(void)
  477. {
  478. rt_interrupt_enter();
  479. GPIO_EXTI_Callback(GPIO_PIN_12);
  480. GPIO_EXTI_Callback(GPIO_PIN_13);
  481. GPIO_EXTI_Callback(GPIO_PIN_14);
  482. GPIO_EXTI_Callback(GPIO_PIN_15);
  483. rt_interrupt_leave();
  484. }
  485. int rt_hw_pin_init(void)
  486. {
  487. int result;
  488. #ifdef ES_INIT_GPIOS
  489. rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t);
  490. #endif
  491. ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
  492. result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f0_pin_ops, RT_NULL);
  493. if(result != RT_EOK)return result;
  494. #ifdef ES_INIT_GPIOS
  495. for(i = 0;i < gpio_conf_num;i++)
  496. {
  497. rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode);
  498. if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD))
  499. rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level);
  500. if(!gpio_conf_all[i].irq_en)continue;
  501. rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL);
  502. rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en);
  503. }
  504. #endif
  505. return result;
  506. }
  507. INIT_BOARD_EXPORT(rt_hw_pin_init);
  508. #endif