mmcsd_core.c 13 KB

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  1. /*
  2. * File : mmcsd_core.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-07-25 weety first version
  13. */
  14. #include <rtthread.h>
  15. #include "mmcsd_core.h"
  16. #include "mmcsd_card.h"
  17. #include "mmcsd_cmd.h"
  18. #include "sd.h"
  19. #ifndef RT_MMCSD_STACK_SIZE
  20. #define RT_MMCSD_STACK_SIZE 1024
  21. #endif
  22. #ifndef RT_MMCSD_THREAD_PREORITY
  23. #define RT_MMCSD_THREAD_PREORITY 0x40
  24. #endif
  25. //static struct rt_semaphore mmcsd_sem;
  26. static struct rt_thread mmcsd_detect_thread;
  27. static rt_uint8_t mmcsd_stack[RT_MMCSD_STACK_SIZE];
  28. static struct rt_mailbox mmcsd_detect_mb;
  29. static rt_uint32_t mmcsd_detect_mb_pool[4];
  30. void mmcsd_host_lock(struct rt_mmcsd_host *host)
  31. {
  32. rt_sem_take(&host->bus_lock, RT_WAITING_FOREVER);
  33. }
  34. void mmcsd_host_unlock(struct rt_mmcsd_host *host)
  35. {
  36. rt_sem_release(&host->bus_lock);
  37. }
  38. void mmcsd_req_complete(struct rt_mmcsd_host *host)
  39. {
  40. rt_sem_release(&host->sem_ack);
  41. }
  42. void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  43. {
  44. req->cmd->err = 0;
  45. req->cmd->mrq = req;
  46. if (req->data)
  47. {
  48. req->cmd->data = req->data;
  49. req->data->err = 0;
  50. req->data->mrq = req;
  51. if (req->stop)
  52. {
  53. req->data->stop = req->stop;
  54. req->stop->err = 0;
  55. req->stop->mrq = req;
  56. }
  57. }
  58. host->ops->request(host, req);
  59. rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
  60. }
  61. rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries)
  62. {
  63. struct rt_mmcsd_req req;
  64. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  65. rt_memset(cmd->resp, 0, sizeof(cmd->resp));
  66. req.cmd = cmd;
  67. cmd->data = RT_NULL;
  68. mmcsd_send_request(host, &req);
  69. return cmd->err;
  70. }
  71. rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host)
  72. {
  73. rt_int32_t err;
  74. struct rt_mmcsd_cmd cmd;
  75. if (!controller_is_spi(host)) {
  76. mmcsd_set_chip_select(host, MMCSD_CS_HIGH);
  77. mmcsd_delay_ms(1);
  78. }
  79. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  80. cmd.cmd_code = GO_IDLE_STATE;
  81. cmd.arg = 0;
  82. cmd.flags = RESP_SPI_R1 | RESP_NONE | CMD_BC;
  83. err = mmcsd_send_cmd(host, &cmd, 0);
  84. mmcsd_delay_ms(1);
  85. if (!controller_is_spi(host))
  86. {
  87. mmcsd_set_chip_select(host, MMCSD_CS_IGNORE);
  88. mmcsd_delay_ms(1);
  89. }
  90. return err;
  91. }
  92. rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr)
  93. {
  94. struct rt_mmcsd_cmd cmd;
  95. rt_int32_t err;
  96. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  97. cmd.cmd_code = SPI_READ_OCR;
  98. cmd.arg = high_capacity ? (1 << 30) : 0;
  99. cmd.flags = RESP_SPI_R3;
  100. err = mmcsd_send_cmd(host, &cmd, 0);
  101. *ocr = cmd.resp[1];
  102. return err;
  103. }
  104. rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  105. {
  106. rt_int32_t err;
  107. struct rt_mmcsd_cmd cmd;
  108. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  109. cmd.cmd_code = ALL_SEND_CID;
  110. cmd.arg = 0;
  111. cmd.flags = RESP_R2 | CMD_BCR;
  112. err = mmcsd_send_cmd(host, &cmd, 3);
  113. if (err)
  114. return err;
  115. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  116. return 0;
  117. }
  118. rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  119. {
  120. rt_int32_t err, i;
  121. struct rt_mmcsd_req req;
  122. struct rt_mmcsd_cmd cmd;
  123. struct rt_mmcsd_data data;
  124. rt_uint32_t *buf = RT_NULL;
  125. if (!controller_is_spi(host))
  126. {
  127. if (!host->card)
  128. return -RT_ERROR;
  129. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  130. cmd.cmd_code = SEND_CID;
  131. cmd.arg = host->card->rca << 16;
  132. cmd.flags = RESP_R2 | CMD_AC;
  133. err = mmcsd_send_cmd(host, &cmd, 3);
  134. if (err)
  135. return err;
  136. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  137. return 0;
  138. }
  139. buf = rt_malloc_align(16, 32);
  140. if (!buf)
  141. {
  142. rt_kprintf("malloc mem failed\n");
  143. return -RT_ENOMEM;
  144. }
  145. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  146. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  147. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  148. req.cmd = &cmd;
  149. req.data = &data;
  150. cmd.cmd_code = SEND_CID;
  151. cmd.arg = 0;
  152. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  153. * rely on callers to never use this with "native" calls for reading
  154. * CSD or CID. Native versions of those commands use the R2 type,
  155. * not R1 plus a data block.
  156. */
  157. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  158. data.blksize = 16;
  159. data.blks = 1;
  160. data.flags = DATA_DIR_READ;
  161. data.buf = buf;
  162. /*
  163. * The spec states that CSR and CID accesses have a timeout
  164. * of 64 clock cycles.
  165. */
  166. data.timeout_ns = 0;
  167. data.timeout_clks = 64;
  168. mmcsd_send_request(host, &req);
  169. if (cmd.err || data.err)
  170. {
  171. rt_free_align(buf);
  172. return -RT_ERROR;
  173. }
  174. for (i = 0;i < 4;i++)
  175. cid[i] = buf[i];
  176. rt_free_align(buf);
  177. return 0;
  178. }
  179. rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd)
  180. {
  181. rt_int32_t err, i;
  182. struct rt_mmcsd_req req;
  183. struct rt_mmcsd_cmd cmd;
  184. struct rt_mmcsd_data data;
  185. rt_uint32_t *buf = RT_NULL;
  186. if (!controller_is_spi(card->host))
  187. {
  188. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  189. cmd.cmd_code = SEND_CSD;
  190. cmd.arg = card->rca << 16;
  191. cmd.flags = RESP_R2 | CMD_AC;
  192. err = mmcsd_send_cmd(card->host, &cmd, 3);
  193. if (err)
  194. return err;
  195. rt_memcpy(csd, cmd.resp, sizeof(rt_uint32_t) * 4);
  196. return 0;
  197. }
  198. buf = rt_malloc_align(16, 32);
  199. if (!buf)
  200. {
  201. rt_kprintf("malloc mem failed\n");
  202. return -RT_ENOMEM;
  203. }
  204. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  205. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  206. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  207. req.cmd = &cmd;
  208. req.data = &data;
  209. cmd.cmd_code = SEND_CSD;
  210. cmd.arg = 0;
  211. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  212. * rely on callers to never use this with "native" calls for reading
  213. * CSD or CID. Native versions of those commands use the R2 type,
  214. * not R1 plus a data block.
  215. */
  216. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  217. data.blksize = 16;
  218. data.blks = 1;
  219. data.flags = DATA_DIR_READ;
  220. data.buf = buf;
  221. /*
  222. * The spec states that CSR and CID accesses have a timeout
  223. * of 64 clock cycles.
  224. */
  225. data.timeout_ns = 0;
  226. data.timeout_clks = 64;
  227. mmcsd_send_request(card->host, &req);
  228. if (cmd.err || data.err)
  229. {
  230. rt_free_align(buf);
  231. return -RT_ERROR;
  232. }
  233. for (i = 0;i < 4;i++)
  234. csd[i] = buf[i];
  235. rt_free_align(buf);
  236. return 0;
  237. }
  238. static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card)
  239. {
  240. rt_int32_t err;
  241. struct rt_mmcsd_cmd cmd;
  242. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  243. cmd.cmd_code = SELECT_CARD;
  244. if (card)
  245. {
  246. cmd.arg = card->rca << 16;
  247. cmd.flags = RESP_R1 | CMD_AC;
  248. }
  249. else
  250. {
  251. cmd.arg = 0;
  252. cmd.flags = RESP_NONE | CMD_AC;
  253. }
  254. err = mmcsd_send_cmd(host, &cmd, 3);
  255. if (err)
  256. return err;
  257. return 0;
  258. }
  259. rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card)
  260. {
  261. return _mmcsd_select_card(card->host, card);
  262. }
  263. rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *card)
  264. {
  265. return _mmcsd_select_card(card->host, RT_NULL);
  266. }
  267. rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc)
  268. {
  269. struct rt_mmcsd_cmd cmd;
  270. rt_int32_t err;
  271. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  272. cmd.cmd_code = SPI_CRC_ON_OFF;
  273. cmd.flags = RESP_SPI_R1;
  274. cmd.arg = use_crc;
  275. err = mmcsd_send_cmd(host, &cmd, 0);
  276. if (!err)
  277. host->spi_use_crc = use_crc;
  278. return err;
  279. }
  280. rt_inline void mmcsd_set_iocfg(struct rt_mmcsd_host *host)
  281. {
  282. struct rt_mmcsd_io_cfg *io_cfg = &host->io_cfg;
  283. mmcsd_dbg("clock %uHz busmode %u powermode %u cs %u Vdd %u "
  284. "width %u \n",
  285. io_cfg->clock, io_cfg->bus_mode,
  286. io_cfg->power_mode, io_cfg->chip_select, io_cfg->vdd,
  287. io_cfg->bus_width);
  288. host->ops->set_iocfg(host, io_cfg);
  289. }
  290. /*
  291. * Control chip select pin on a host.
  292. */
  293. void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode)
  294. {
  295. host->io_cfg.chip_select = mode;
  296. mmcsd_set_iocfg(host);
  297. }
  298. /*
  299. * Sets the host clock to the highest possible frequency that
  300. * is below "hz".
  301. */
  302. void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk)
  303. {
  304. if (clk < host->freq_min)
  305. {
  306. rt_kprintf("clock too low\n");
  307. }
  308. host->io_cfg.clock = clk;
  309. mmcsd_set_iocfg(host);
  310. }
  311. /*
  312. * Change the bus mode (open drain/push-pull) of a host.
  313. */
  314. void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode)
  315. {
  316. host->io_cfg.bus_mode = mode;
  317. mmcsd_set_iocfg(host);
  318. }
  319. /*
  320. * Change data bus width of a host.
  321. */
  322. void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width)
  323. {
  324. host->io_cfg.bus_width = width;
  325. mmcsd_set_iocfg(host);
  326. }
  327. void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card)
  328. {
  329. rt_uint32_t mult;
  330. if (card->card_type & CARD_TYPE_SDIO)
  331. {
  332. data->timeout_ns = 1000000000; /* SDIO card 1s */
  333. data->timeout_clks = 0;
  334. return;
  335. }
  336. /*
  337. * SD cards use a 100 multiplier rather than 10
  338. */
  339. mult = (card->card_type & CARD_TYPE_SD) ? 100 : 10;
  340. /*
  341. * Scale up the multiplier (and therefore the timeout) by
  342. * the r2w factor for writes.
  343. */
  344. if (data->flags & DATA_DIR_WRITE)
  345. mult <<= card->csd.r2w_factor;
  346. data->timeout_ns = card->tacc_ns * mult;
  347. data->timeout_clks = card->tacc_clks * mult;
  348. /*
  349. * SD cards also have an upper limit on the timeout.
  350. */
  351. if (card->card_type & CARD_TYPE_SD)
  352. {
  353. rt_uint32_t timeout_us, limit_us;
  354. timeout_us = data->timeout_ns / 1000;
  355. timeout_us += data->timeout_clks * 1000 /
  356. (card->host->io_cfg.clock / 1000);
  357. if (data->flags & DATA_DIR_WRITE)
  358. /*
  359. * The limit is really 250 ms, but that is
  360. * insufficient for some crappy cards.
  361. */
  362. limit_us = 300000;
  363. else
  364. limit_us = 100000;
  365. /*
  366. * SDHC cards always use these fixed values.
  367. */
  368. if (timeout_us > limit_us || card->card_type & CARD_TYPE_SDHC)
  369. {
  370. data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */
  371. data->timeout_clks = 0;
  372. }
  373. }
  374. if (controller_is_spi(card->host))
  375. {
  376. if (data->flags & DATA_DIR_WRITE)
  377. {
  378. if (data->timeout_ns < 1000000000)
  379. data->timeout_ns = 1000000000; /* 1s */
  380. }
  381. else
  382. {
  383. if (data->timeout_ns < 100000000)
  384. data->timeout_ns = 100000000; /* 100ms */
  385. }
  386. }
  387. }
  388. /*
  389. * Mask off any voltages we don't support and select
  390. * the lowest voltage
  391. */
  392. rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr)
  393. {
  394. int bit;
  395. ocr &= host->valid_ocr;
  396. bit = ffs(ocr);
  397. if (bit)
  398. {
  399. bit -= 1;
  400. ocr &= 3 << bit;
  401. host->io_cfg.vdd = bit;
  402. mmcsd_set_iocfg(host);
  403. }
  404. else
  405. {
  406. rt_kprintf("host doesn't support card's voltages\n");
  407. ocr = 0;
  408. }
  409. return ocr;
  410. }
  411. static void mmcsd_power_up(struct rt_mmcsd_host *host)
  412. {
  413. int bit = fls(host->valid_ocr) - 1;
  414. host->io_cfg.vdd = bit;
  415. if (controller_is_spi(host))
  416. {
  417. host->io_cfg.chip_select = MMCSD_CS_HIGH;
  418. host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL;
  419. }
  420. else
  421. {
  422. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  423. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  424. }
  425. host->io_cfg.power_mode = MMCSD_POWER_UP;
  426. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  427. mmcsd_set_iocfg(host);
  428. /*
  429. * This delay should be sufficient to allow the power supply
  430. * to reach the minimum voltage.
  431. */
  432. mmcsd_delay_ms(10);
  433. host->io_cfg.clock = host->freq_min;
  434. host->io_cfg.power_mode = MMCSD_POWER_ON;
  435. mmcsd_set_iocfg(host);
  436. /*
  437. * This delay must be at least 74 clock sizes, or 1 ms, or the
  438. * time required to reach a stable voltage.
  439. */
  440. mmcsd_delay_ms(10);
  441. }
  442. static void mmcsd_power_off(struct rt_mmcsd_host *host)
  443. {
  444. host->io_cfg.clock = 0;
  445. host->io_cfg.vdd = 0;
  446. if (!controller_is_spi(host))
  447. {
  448. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  449. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  450. }
  451. host->io_cfg.power_mode = MMCSD_POWER_OFF;
  452. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  453. mmcsd_set_iocfg(host);
  454. }
  455. void mmcsd_change(struct rt_mmcsd_host *host)
  456. {
  457. rt_mb_send(&mmcsd_detect_mb, (rt_uint32_t)host);
  458. }
  459. void mmcsd_detect(void *param)
  460. {
  461. struct rt_mmcsd_host *host;
  462. rt_uint32_t ocr;
  463. rt_int32_t err;
  464. while (1)
  465. {
  466. if (rt_mb_recv(&mmcsd_detect_mb, (rt_uint32_t*)&host, RT_WAITING_FOREVER) == RT_EOK)
  467. {
  468. mmcsd_host_lock(host);
  469. mmcsd_power_up(host);
  470. mmcsd_go_idle(host);
  471. mmcsd_send_if_cond(host, host->valid_ocr);
  472. /*
  473. * detect SD card
  474. */
  475. err = mmcsd_send_app_op_cond(host, 0, &ocr);
  476. if (!err)
  477. {
  478. if (init_sd(host, ocr))
  479. mmcsd_power_off(host);
  480. mmcsd_host_unlock(host);
  481. continue;
  482. }
  483. mmcsd_host_unlock(host);
  484. }
  485. }
  486. }
  487. struct rt_mmcsd_host *mmcsd_alloc_host(void)
  488. {
  489. struct rt_mmcsd_host *host;
  490. host = rt_malloc(sizeof(struct rt_mmcsd_host));
  491. if (!host)
  492. {
  493. rt_kprintf("alloc host failed\n");
  494. return RT_NULL;
  495. }
  496. rt_memset(host, 0, sizeof(struct rt_mmcsd_host));
  497. rt_sem_init(&host->bus_lock, "sd_bus_lock", 1, RT_IPC_FLAG_FIFO);
  498. rt_sem_init(&host->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
  499. return host;
  500. }
  501. void mmcsd_free_host(struct rt_mmcsd_host *host)
  502. {
  503. rt_sem_detach(&host->bus_lock);
  504. rt_sem_detach(&host->sem_ack);
  505. rt_free(host);
  506. }
  507. void rt_mmcsd_core_init(void)
  508. {
  509. rt_err_t ret;
  510. /* init detect sd cart thread */
  511. /* init mailbox and create detect sd card thread */
  512. ret = rt_mb_init(&mmcsd_detect_mb, "mmcsdmb",
  513. &mmcsd_detect_mb_pool[0], sizeof(mmcsd_detect_mb_pool),
  514. RT_IPC_FLAG_FIFO);
  515. RT_ASSERT(ret == RT_EOK);
  516. ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL,
  517. &mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20);
  518. if (ret == RT_EOK)
  519. {
  520. rt_thread_startup(&mmcsd_detect_thread);
  521. }
  522. }