fsl_hx8394.c 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187
  1. /*
  2. * Copyright 2021 NXP
  3. * All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. #include "fsl_display.h"
  8. #include "fsl_hx8394.h"
  9. /*******************************************************************************
  10. * Definitions
  11. ******************************************************************************/
  12. #define HX8394_DelayMs VIDEO_DelayMs
  13. typedef struct
  14. {
  15. const uint8_t *cmd;
  16. uint8_t cmdLen;
  17. } hx8394_cmd_t;
  18. /*******************************************************************************
  19. * Variables
  20. ******************************************************************************/
  21. const display_operations_t hx8394_ops = {
  22. .init = HX8394_Init,
  23. .deinit = HX8394_Deinit,
  24. .start = HX8394_Start,
  25. .stop = HX8394_Stop,
  26. };
  27. static const hx8394_cmd_t s_hx8394Cmds[] = {
  28. {(const uint8_t[]){0x36U, 0x02U}, 2U},
  29. {(const uint8_t[]){0xB1U, 0x48U, 0x12U, 0x72U, 0x09U, 0x32U, 0x54U, 0x71U, 0x71U, 0x57U, 0x47U}, 11U},
  30. {(const uint8_t[]){0xB2U, 0x00U, 0x80U, 0x64U, 0x0CU, 0x0DU, 0x2FU}, 7U},
  31. {(const uint8_t[]){0xB4U, 0x73U, 0x74U, 0x73U, 0x74U, 0x73U, 0x74U, 0x01U, 0x0CU, 0x86U, /* 10 */
  32. 0x75U, 0x00U, 0x3FU, 0x73U, 0x74U, 0x73U, 0x74U, 0x73U, 0x74U, 0x01U, /* 20 */
  33. 0x0CU, 0x86U},
  34. 22U},
  35. {(const uint8_t[]){0xD3U, 0x00U, 0x00U, 0x07U, 0x07U, 0x40U, 0x07U, 0x0CU, 0x00U, 0x08U, /* 10 */
  36. 0x10U, 0x08U, 0x00U, 0x08U, 0x54U, 0x15U, 0x0AU, 0x05U, 0x0AU, 0x02U, /* 20 */
  37. 0x15U, 0x06U, 0x05U, 0x06U, 0x47U, 0x44U, 0x0AU, 0x0AU, 0x4BU, 0x10U, /* 30 */
  38. 0x07U, 0x07U, 0x0CU, 0x40U},
  39. 34U},
  40. {(const uint8_t[]){0xD5U, 0x1CU, 0x1CU, 0x1DU, 0x1DU, 0x00U, 0x01U, 0x02U, 0x03U, 0x04U, /* 10 */
  41. 0x05U, 0x06U, 0x07U, 0x08U, 0x09U, 0x0AU, 0x0BU, 0x24U, 0x25U, 0x18U, /* 20 */
  42. 0x18U, 0x26U, 0x27U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, /* 30 */
  43. 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x20U, /* 40 */
  44. 0x21U, 0x18U, 0x18U, 0x18U, 0x18U},
  45. 45U},
  46. {(const uint8_t[]){0xD6U, 0x1CU, 0x1CU, 0x1DU, 0x1DU, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, /* 10 */
  47. 0x02U, 0x01U, 0x00U, 0x0BU, 0x0AU, 0x09U, 0x08U, 0x21U, 0x20U, 0x18U, /* 20 */
  48. 0x18U, 0x27U, 0x26U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, /* 30 */
  49. 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x18U, 0x25U, /* 40 */
  50. 0x24U, 0x18U, 0x18U, 0x18U, 0x18U},
  51. 45U},
  52. {(const uint8_t[]){0xB6U, 0x92U, 0x92U}, 3U},
  53. {(const uint8_t[]){0xE0U, 0x00U, 0x0AU, 0x15U, 0x1BU, 0x1EU, 0x21U, 0x24U, 0x22U, 0x47U, /* 10 */
  54. 0x56U, 0x65U, 0x66U, 0x6EU, 0x82U, 0x88U, 0x8BU, 0x9AU, 0x9DU, 0x98U, /* 20 */
  55. 0xA8U, 0xB9U, 0x5DU, 0x5CU, 0x61U, 0x66U, 0x6AU, 0x6FU, 0x7FU, 0x7FU, /* 30 */
  56. 0x00U, 0x0AU, 0x15U, 0x1BU, 0x1EU, 0x21U, 0x24U, 0x22U, 0x47U, 0x56U, /* 40 */
  57. 0x65U, 0x65U, 0x6EU, 0x81U, 0x87U, 0x8BU, 0x98U, 0x9DU, 0x99U, 0xA8U, /* 50 */
  58. 0xBAU, 0x5DU, 0x5DU, 0x62U, 0x67U, 0x6BU, 0x72U, 0x7FU, 0x7FU},
  59. 59U},
  60. {(const uint8_t[]){0xC0U, 0x1FU, 0x31U}, 3U},
  61. {(const uint8_t[]){0xCCU, 0x03U}, 2U},
  62. {(const uint8_t[]){0xD4U, 0x02U}, 2U},
  63. {(const uint8_t[]){0xBDU, 0x02U}, 2U},
  64. {(const uint8_t[]){0xD8U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, /* 10 */
  65. 0xFFU, 0xFFU, 0xFFU},
  66. 13U},
  67. {(const uint8_t[]){0xBDU, 0x00U}, 2U},
  68. {(const uint8_t[]){0xBDU, 0x01U}, 2U},
  69. {(const uint8_t[]){0xB1U, 0x00U}, 2U},
  70. {(const uint8_t[]){0xBDU, 0x00U}, 2U},
  71. {(const uint8_t[]){0xBFU, 0x40U, 0x81U, 0x50U, 0x00U, 0x1AU, 0xFCU, 0x01}, 8U},
  72. {(const uint8_t[]){0xC6U, 0xEDU}, 2U},
  73. {(const uint8_t[]){0x35U, 0x00U}, 2U},
  74. };
  75. /*******************************************************************************
  76. * Code
  77. ******************************************************************************/
  78. status_t HX8394_Init(display_handle_t *handle, const display_config_t *config)
  79. {
  80. uint8_t i;
  81. status_t status = kStatus_Success;
  82. const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource);
  83. mipi_dsi_device_t *dsiDevice = resource->dsiDevice;
  84. uint8_t setmipi[7] = {0xBAU, 0x60U, 0x03U, 0x68U, 0x6BU, 0xB2U, 0xC0U};
  85. /* Only support 720 * 1280 */
  86. if (config->resolution != FSL_VIDEO_RESOLUTION(720, 1280))
  87. {
  88. return kStatus_InvalidArgument;
  89. }
  90. /* Power on. */
  91. resource->pullPowerPin(true);
  92. HX8394_DelayMs(1);
  93. /* Perform reset. */
  94. resource->pullResetPin(false);
  95. HX8394_DelayMs(1);
  96. resource->pullResetPin(true);
  97. HX8394_DelayMs(50U);
  98. status = MIPI_DSI_GenericWrite(dsiDevice, (const uint8_t[]){0xB9U, 0xFFU, 0x83U, 0x94U}, 4);
  99. setmipi[1] |= (config->dsiLanes - 1U);
  100. if (kStatus_Success == status)
  101. {
  102. status = MIPI_DSI_GenericWrite(dsiDevice, setmipi, 7);
  103. }
  104. if (kStatus_Success == status)
  105. {
  106. for (i = 0; i < ARRAY_SIZE(s_hx8394Cmds); i++)
  107. {
  108. status = MIPI_DSI_GenericWrite(dsiDevice, s_hx8394Cmds[i].cmd, (int32_t)s_hx8394Cmds[i].cmdLen);
  109. if (kStatus_Success != status)
  110. {
  111. break;
  112. }
  113. }
  114. }
  115. if (kStatus_Success == status)
  116. {
  117. status = MIPI_DSI_DCS_EnterSleepMode(dsiDevice, false);
  118. }
  119. if (kStatus_Success == status)
  120. {
  121. HX8394_DelayMs(120U);
  122. status = MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true);
  123. }
  124. return status;
  125. }
  126. status_t HX8394_Deinit(display_handle_t *handle)
  127. {
  128. const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource);
  129. mipi_dsi_device_t *dsiDevice = resource->dsiDevice;
  130. (void)MIPI_DSI_DCS_EnterSleepMode(dsiDevice, true);
  131. resource->pullResetPin(false);
  132. resource->pullPowerPin(false);
  133. return kStatus_Success;
  134. }
  135. status_t HX8394_Start(display_handle_t *handle)
  136. {
  137. const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource);
  138. mipi_dsi_device_t *dsiDevice = resource->dsiDevice;
  139. return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, true);
  140. }
  141. status_t HX8394_Stop(display_handle_t *handle)
  142. {
  143. const hx8394_resource_t *resource = (const hx8394_resource_t *)(handle->resource);
  144. mipi_dsi_device_t *dsiDevice = resource->dsiDevice;
  145. return MIPI_DSI_DCS_SetDisplayOn(dsiDevice, false);
  146. }