lpc177x_8x_clkpwr.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301
  1. /**********************************************************************
  2. * $Id$ lpc177x_8x_clkpwr.c 2011-06-02
  3. *//**
  4. * @file lpc177x_8x_clkpwr.c
  5. * @brief Contains all functions support for Clock and Power Control
  6. * firmware library on LPC177x_8x
  7. * @version 1.0
  8. * @date 02. June. 2011
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2011, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. **********************************************************************/
  26. /* Peripheral group ----------------------------------------------------------- */
  27. /** @addtogroup CLKPWR
  28. * @{
  29. */
  30. /* Includes ------------------------------------------------------------------- */
  31. #include "lpc177x_8x_clkpwr.h"
  32. uint32_t USBFrequency = 0;
  33. uint32_t SPIFIFrequency = 0;
  34. /* Public Functions ----------------------------------------------------------- */
  35. /** @addtogroup CLKPWR_Public_Functions
  36. * @{
  37. */
  38. /*********************************************************************//**
  39. * @brief Set value of each Peripheral Clock Selection
  40. * @param[in] ClkType clock type that will be divided, should be:
  41. * - CLKPWR_CLKTYPE_CPU : CPU clock
  42. * - CLKPWR_CLKTYPE_PER : Peripheral clock
  43. * - CLKPWR_CLKTYPE_EMC : EMC clock
  44. * - CLKPWR_CLKTYPE_USB : USB clock
  45. * @param[in] DivVal Value of divider. This value should be set as follows:
  46. * - CPU clock: DivVal must be in range: 0..31
  47. * - Peripheral clock: DivVal must be in range: 0..31
  48. * - EMC clock: DivVal must be:
  49. * + 0: The EMC uses the same clock as the CPU
  50. * + 1: The EMC uses a clock at half the rate of the CPU
  51. * - USB clock: DivVal must be:
  52. * + 0: the divider is turned off, no clock will
  53. * be provided to the USB subsystem
  54. * + 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
  55. * + 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
  56. * @return none
  57. * Note: Pls assign right DivVal, this function will not check if it is illegal.
  58. **********************************************************************/
  59. void CLKPWR_SetCLKDiv (uint8_t ClkType, uint8_t DivVal)
  60. {
  61. switch(ClkType)
  62. {
  63. case CLKPWR_CLKTYPE_CPU:
  64. LPC_SC->CCLKSEL = DivVal;
  65. SystemCoreClockUpdate(); //Update clock
  66. break;
  67. case CLKPWR_CLKTYPE_PER:
  68. LPC_SC->PCLKSEL = DivVal;
  69. SystemCoreClockUpdate(); //Update clock
  70. break;
  71. case CLKPWR_CLKTYPE_EMC:
  72. LPC_SC->EMCCLKSEL = DivVal;
  73. SystemCoreClockUpdate(); //Update clock
  74. break;
  75. case CLKPWR_CLKTYPE_USB:
  76. LPC_SC->USBCLKSEL &= ~(0x0000001F);
  77. LPC_SC->USBCLKSEL |= DivVal;
  78. break;
  79. default:
  80. while(1);//Error Loop;
  81. }
  82. }
  83. /*********************************************************************//**
  84. * @brief Get current clock value
  85. * @param[in] ClkType clock type that will be divided, should be:
  86. * - CLKPWR_CLKTYPE_CPU : CPU clock
  87. * - CLKPWR_CLKTYPE_PER : Peripheral clock
  88. * - CLKPWR_CLKTYPE_EMC : EMC clock
  89. * - CLKPWR_CLKTYPE_USB : USB clock
  90. **********************************************************************/
  91. uint32_t CLKPWR_GetCLK (uint8_t ClkType)
  92. {
  93. switch(ClkType)
  94. {
  95. case CLKPWR_CLKTYPE_CPU:
  96. return SystemCoreClock;
  97. case CLKPWR_CLKTYPE_PER:
  98. return PeripheralClock;
  99. case CLKPWR_CLKTYPE_EMC:
  100. return EMCClock;
  101. case CLKPWR_CLKTYPE_USB:
  102. return USBClock;
  103. default:
  104. while(1);//error loop
  105. }
  106. }
  107. /*********************************************************************//**
  108. * @brief Configure power supply for each peripheral according to NewState
  109. * @param[in] PPType Type of peripheral used to enable power,
  110. * should be one of the following:
  111. * - CLKPWR_PCONP_PCLCD : LCD
  112. * - CLKPWR_PCONP_PCTIM0 : Timer 0
  113. - CLKPWR_PCONP_PCTIM1 : Timer 1
  114. - CLKPWR_PCONP_PCUART0 : UART 0
  115. - CLKPWR_PCONP_PCUART1 : UART 1
  116. - CLKPWR_PCONP_PCPWM0 : PWM 0
  117. - CLKPWR_PCONP_PCPWM1 : PWM 1
  118. - CLKPWR_PCONP_PCI2C0 : I2C 0
  119. - CLKPWR_PCONP_PCUART4 : UART4
  120. - CLKPWR_PCONP_PCRTC : RTC
  121. - CLKPWR_PCONP_PCSSP1 : SSP 1
  122. - CLKPWR_PCONP_PCEMC : EMC
  123. - CLKPWR_PCONP_PCADC : ADC
  124. - CLKPWR_PCONP_PCAN1 : CAN 1
  125. - CLKPWR_PCONP_PCAN2 : CAN 2
  126. - CLKPWR_PCONP_PCGPIO : GPIO
  127. - CLKPWR_PCONP_PCMC : MCPWM
  128. - CLKPWR_PCONP_PCQEI : QEI
  129. - CLKPWR_PCONP_PCI2C1 : I2C 1
  130. - CLKPWR_PCONP_PCSSP2 : SSP 2
  131. - CLKPWR_PCONP_PCSSP0 : SSP 0
  132. - CLKPWR_PCONP_PCTIM2 : Timer 2
  133. - CLKPWR_PCONP_PCTIM3 : Timer 3
  134. - CLKPWR_PCONP_PCUART2 : UART 2
  135. - CLKPWR_PCONP_PCUART3 : UART 3
  136. - CLKPWR_PCONP_PCI2C2 : I2C 2
  137. - CLKPWR_PCONP_PCI2S : I2S
  138. - CLKPWR_PCONP_PCSDC : SDC
  139. - CLKPWR_PCONP_PCGPDMA : GPDMA
  140. - CLKPWR_PCONP_PCENET : Ethernet
  141. - CLKPWR_PCONP_PCUSB : USB
  142. *
  143. * @param[in] NewState New state of Peripheral Power, should be:
  144. * - ENABLE : Enable power for this peripheral
  145. * - DISABLE : Disable power for this peripheral
  146. *
  147. * @return none
  148. **********************************************************************/
  149. void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
  150. {
  151. if (NewState == ENABLE)
  152. {
  153. LPC_SC->PCONP |= PPType;
  154. }
  155. else if (NewState == DISABLE)
  156. {
  157. LPC_SC->PCONP &= ~PPType;
  158. }
  159. }
  160. #if 0
  161. // nxp21346
  162. /*********************************************************************//**
  163. * @brief Configure hardware reset for each peripheral according to NewState
  164. * @param[in] PPType Type of peripheral used to enable power,
  165. * should be one of the following:
  166. * - CLKPWR_RSTCON0_LCD : LCD
  167. * - CLKPWR_RSTCON0_TIM0 : Timer 0
  168. - CLKPWR_RSTCON0_TIM1 : Timer 1
  169. - CLKPWR_RSTCON0_UART0 : UART 0
  170. - CLKPWR_RSTCON0_UART1 : UART 1
  171. - CLKPWR_RSTCON0_PWM0 : PWM 0
  172. - CLKPWR_RSTCON0_PWM1 : PWM 1
  173. - CLKPWR_RSTCON0_I2C0 : I2C 0
  174. - CLKPWR_RSTCON0_UART4 : UART 4
  175. - CLKPWR_RSTCON0_RTC : RTC
  176. - CLKPWR_RSTCON0_SSP1 : SSP 1
  177. - CLKPWR_RSTCON0_EMC : EMC
  178. - CLKPWR_RSTCON0_ADC : ADC
  179. - CLKPWR_RSTCON0_CAN1 : CAN 1
  180. - CLKPWR_RSTCON0_CAN2 : CAN 2
  181. - CLKPWR_RSTCON0_GPIO : GPIO
  182. - CLKPWR_RSTCON0_MCPWM : MCPWM
  183. - CLKPWR_RSTCON0_QEI : QEI
  184. - CLKPWR_RSTCON0_I2C1 : I2C 1
  185. - CLKPWR_RSTCON0_SSP2 : SSP 2
  186. - CLKPWR_RSTCON0_SSP0 : SSP 0
  187. - CLKPWR_RSTCON0_TIM2 : Timer 2
  188. - CLKPWR_RSTCON0_TIM3 : Timer 3
  189. - CLKPWR_RSTCON0_UART2 : UART 2
  190. - CLKPWR_RSTCON0_UART3 : UART 3
  191. - CLKPWR_RSTCON0_I2C2 : I2C 2
  192. - CLKPWR_RSTCON0_I2S : I2S
  193. - CLKPWR_RSTCON0_SDC : SDC
  194. - CLKPWR_RSTCON0_GPDMA : GPDMA
  195. - CLKPWR_RSTCON0_ENET : Ethernet
  196. - CLKPWR_RSTCON0_USB : USB
  197. *
  198. * @param[in] NewState New state of Peripheral Power, should be:
  199. * - ENABLE : Enable power for this peripheral
  200. * - DISABLE : Disable power for this peripheral
  201. *
  202. * @return none
  203. **********************************************************************/
  204. void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
  205. {
  206. if(PType < 32)
  207. {
  208. if(NewState == ENABLE)
  209. LPC_SC->RSTCON0 |=(1<<PType);
  210. else
  211. LPC_SC->RSTCON0 &=~(1<<PType);
  212. }
  213. else
  214. {
  215. if(NewState == ENABLE)
  216. LPC_SC->RSTCON1 |= (1<<(PType - 31));
  217. else
  218. LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
  219. }
  220. }
  221. // nxp21346
  222. #endif
  223. /*********************************************************************//**
  224. * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
  225. * @param[in] None
  226. * @return None
  227. **********************************************************************/
  228. void CLKPWR_Sleep(void)
  229. {
  230. LPC_SC->PCON = 0x00;
  231. /* Sleep Mode*/
  232. __WFI();
  233. }
  234. /*********************************************************************//**
  235. * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
  236. * @param[in] None
  237. * @return None
  238. **********************************************************************/
  239. void CLKPWR_DeepSleep(void)
  240. {
  241. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  242. SCB->SCR = 0x4;
  243. LPC_SC->PCON = 0x8;
  244. /* Deep Sleep Mode*/
  245. __WFI();
  246. }
  247. /*********************************************************************//**
  248. * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
  249. * @param[in] None
  250. * @return None
  251. **********************************************************************/
  252. void CLKPWR_PowerDown(void)
  253. {
  254. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  255. SCB->SCR = 0x4;
  256. LPC_SC->PCON = 0x09;
  257. /* Power Down Mode*/
  258. __WFI();
  259. }
  260. /*********************************************************************//**
  261. * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
  262. * @param[in] None
  263. * @return None
  264. **********************************************************************/
  265. void CLKPWR_DeepPowerDown(void)
  266. {
  267. /* Deep-Sleep Mode, set SLEEPDEEP bit */
  268. SCB->SCR = 0x4;
  269. LPC_SC->PCON = 0x03;
  270. /* Deep Power Down Mode*/
  271. __WFI();
  272. }
  273. /**
  274. * @}
  275. */
  276. /**
  277. * @}
  278. */
  279. /* --------------------------------- End Of File ------------------------------ */