drv_can.c 30 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-08-05 Xeon Xu the first version
  9. * 2019-01-22 YLZ port from stm324xx-HAL to bsp stm3210x-HAL
  10. * 2019-02-19 YLZ add support EXTID RTR Frame. modify send, recv functions.
  11. * fix bug.port to BSP [stm32]
  12. * 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode).
  13. * 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3.
  14. */
  15. #include "drv_can.h"
  16. #ifdef BSP_USING_CAN
  17. #define LOG_TAG "drv_can"
  18. #include <drv_log.h>
  19. /* attention !!! baud calculation example: Tclk / ((ss + bs1 + bs2) * brp) 36 / ((1 + 8 + 3) * 3) = 1MHz*/
  20. #if defined (SOC_SERIES_STM32F1)/* APB1 36MHz(max) */
  21. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  22. {
  23. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 3)},
  24. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_5TQ | CAN_BS2_3TQ | 5)},
  25. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 6)},
  26. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 12)},
  27. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 24)},
  28. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 30)},
  29. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 60)},
  30. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 150)},
  31. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 300)}
  32. };
  33. #elif defined (SOC_SERIES_STM32F4)/* APB1 45MHz(max) */
  34. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  35. {
  36. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 3)},
  37. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_5TQ | 4)},
  38. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 6)},
  39. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 12)},
  40. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 24)},
  41. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 30)},
  42. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 60)},
  43. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)},
  44. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)}
  45. };
  46. #elif defined (SOC_SERIES_STM32F7)/* APB1 54MHz(max) */
  47. static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
  48. {
  49. {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 3)},
  50. {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_7TQ | 4)},
  51. {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 6)},
  52. {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 12)},
  53. {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 24)},
  54. {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 30)},
  55. {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 60)},
  56. {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 150)},
  57. {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_10TQ | CAN_BS2_7TQ | 300)}
  58. };
  59. #endif
  60. #ifdef BSP_USING_CAN1
  61. static struct stm32_can drv_can1 =
  62. {
  63. .name = "can1",
  64. .CanHandle.Instance = CAN1,
  65. };
  66. #endif
  67. #ifdef BSP_USING_CAN2
  68. static struct stm32_can drv_can2 =
  69. {
  70. "can2",
  71. .CanHandle.Instance = CAN2,
  72. };
  73. #endif
  74. static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
  75. {
  76. rt_uint32_t len, index;
  77. len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
  78. for (index = 0; index < len; index++)
  79. {
  80. if (can_baud_rate_tab[index].baud_rate == baud)
  81. return index;
  82. }
  83. return 0; /* default baud is CAN1MBaud */
  84. }
  85. static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
  86. {
  87. struct stm32_can *drv_can;
  88. rt_uint32_t baud_index;
  89. RT_ASSERT(can);
  90. RT_ASSERT(cfg);
  91. drv_can = (struct stm32_can *)can->parent.user_data;
  92. RT_ASSERT(drv_can);
  93. drv_can->CanHandle.Init.TimeTriggeredMode = DISABLE;
  94. drv_can->CanHandle.Init.AutoBusOff = ENABLE;
  95. drv_can->CanHandle.Init.AutoWakeUp = DISABLE;
  96. drv_can->CanHandle.Init.AutoRetransmission = DISABLE;
  97. drv_can->CanHandle.Init.ReceiveFifoLocked = DISABLE;
  98. drv_can->CanHandle.Init.TransmitFifoPriority = ENABLE;
  99. switch (cfg->mode)
  100. {
  101. case RT_CAN_MODE_NORMAL:
  102. drv_can->CanHandle.Init.Mode = CAN_MODE_NORMAL;
  103. break;
  104. case RT_CAN_MODE_LISEN:
  105. drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT;
  106. break;
  107. case RT_CAN_MODE_LOOPBACK:
  108. drv_can->CanHandle.Init.Mode = CAN_MODE_LOOPBACK;
  109. break;
  110. case RT_CAN_MODE_LOOPBACKANLISEN:
  111. drv_can->CanHandle.Init.Mode = CAN_MODE_SILENT_LOOPBACK;
  112. break;
  113. }
  114. baud_index = get_can_baud_index(cfg->baud_rate);
  115. drv_can->CanHandle.Init.SyncJumpWidth = BAUD_DATA(SJW, baud_index);
  116. drv_can->CanHandle.Init.TimeSeg1 = BAUD_DATA(BS1, baud_index);
  117. drv_can->CanHandle.Init.TimeSeg2 = BAUD_DATA(BS2, baud_index);
  118. drv_can->CanHandle.Init.Prescaler = BAUD_DATA(RRESCL, baud_index);
  119. /* init can */
  120. if (HAL_CAN_Init(&drv_can->CanHandle) != HAL_OK)
  121. {
  122. return -RT_ERROR;
  123. }
  124. /* default filter config */
  125. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  126. /* can start */
  127. HAL_CAN_Start(&drv_can->CanHandle);
  128. return RT_EOK;
  129. }
  130. static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
  131. {
  132. rt_uint32_t argval;
  133. struct stm32_can *drv_can;
  134. struct rt_can_filter_config *filter_cfg;
  135. RT_ASSERT(can != RT_NULL);
  136. drv_can = (struct stm32_can *)can->parent.user_data;
  137. RT_ASSERT(drv_can != RT_NULL);
  138. switch (cmd)
  139. {
  140. case RT_DEVICE_CTRL_CLR_INT:
  141. argval = (rt_uint32_t) arg;
  142. if (argval == RT_DEVICE_FLAG_INT_RX)
  143. {
  144. if (CAN1 == drv_can->CanHandle.Instance)
  145. {
  146. HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
  147. HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);
  148. }
  149. #ifdef CAN2
  150. if (CAN2 == drv_can->CanHandle.Instance)
  151. {
  152. HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);
  153. HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);
  154. }
  155. #endif
  156. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
  157. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
  158. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
  159. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
  160. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
  161. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
  162. }
  163. else if (argval == RT_DEVICE_FLAG_INT_TX)
  164. {
  165. if (CAN1 == drv_can->CanHandle.Instance)
  166. {
  167. HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);
  168. }
  169. #ifdef CAN2
  170. if (CAN2 == drv_can->CanHandle.Instance)
  171. {
  172. HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);
  173. }
  174. #endif
  175. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
  176. }
  177. else if (argval == RT_DEVICE_CAN_INT_ERR)
  178. {
  179. if (CAN1 == drv_can->CanHandle.Instance)
  180. {
  181. NVIC_DisableIRQ(CAN1_SCE_IRQn);
  182. }
  183. #ifdef CAN2
  184. if (CAN2 == drv_can->CanHandle.Instance)
  185. {
  186. NVIC_DisableIRQ(CAN2_SCE_IRQn);
  187. }
  188. #endif
  189. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
  190. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
  191. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
  192. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
  193. __HAL_CAN_DISABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
  194. }
  195. break;
  196. case RT_DEVICE_CTRL_SET_INT:
  197. argval = (rt_uint32_t) arg;
  198. if (argval == RT_DEVICE_FLAG_INT_RX)
  199. {
  200. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_MSG_PENDING);
  201. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_FULL);
  202. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO0_OVERRUN);
  203. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_MSG_PENDING);
  204. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_FULL);
  205. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_RX_FIFO1_OVERRUN);
  206. if (CAN1 == drv_can->CanHandle.Instance)
  207. {
  208. HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 1, 0);
  209. HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
  210. HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 1, 0);
  211. HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);
  212. }
  213. #ifdef CAN2
  214. if (CAN2 == drv_can->CanHandle.Instance)
  215. {
  216. HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 1, 0);
  217. HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
  218. HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 1, 0);
  219. HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
  220. }
  221. #endif
  222. }
  223. else if (argval == RT_DEVICE_FLAG_INT_TX)
  224. {
  225. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_TX_MAILBOX_EMPTY);
  226. if (CAN1 == drv_can->CanHandle.Instance)
  227. {
  228. HAL_NVIC_SetPriority(CAN1_TX_IRQn, 1, 0);
  229. HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);
  230. }
  231. #ifdef CAN2
  232. if (CAN2 == drv_can->CanHandle.Instance)
  233. {
  234. HAL_NVIC_SetPriority(CAN2_TX_IRQn, 1, 0);
  235. HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);
  236. }
  237. #endif
  238. }
  239. else if (argval == RT_DEVICE_CAN_INT_ERR)
  240. {
  241. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_WARNING);
  242. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR_PASSIVE);
  243. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_BUSOFF);
  244. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_LAST_ERROR_CODE);
  245. __HAL_CAN_ENABLE_IT(&drv_can->CanHandle, CAN_IT_ERROR);
  246. if (CAN1 == drv_can->CanHandle.Instance)
  247. {
  248. HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 1, 0);
  249. HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);
  250. }
  251. #ifdef CAN2
  252. if (CAN2 == drv_can->CanHandle.Instance)
  253. {
  254. HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 1, 0);
  255. HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);
  256. }
  257. #endif
  258. }
  259. break;
  260. case RT_CAN_CMD_SET_FILTER:
  261. if (RT_NULL == arg)
  262. {
  263. /* default filter config */
  264. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  265. }
  266. else
  267. {
  268. filter_cfg = (struct rt_can_filter_config *)arg;
  269. /* get default filter */
  270. for (int i = 0; i < filter_cfg->count; i++)
  271. {
  272. drv_can->FilterConfig.FilterBank = filter_cfg->items[i].hdr;
  273. drv_can->FilterConfig.FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
  274. drv_can->FilterConfig.FilterIdLow = ((filter_cfg->items[i].id << 3) |
  275. (filter_cfg->items[i].ide << 2) |
  276. (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
  277. drv_can->FilterConfig.FilterMaskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
  278. drv_can->FilterConfig.FilterMaskIdLow = filter_cfg->items[i].mask & 0xFFFF;
  279. drv_can->FilterConfig.FilterMode = filter_cfg->items[i].mode;
  280. /* Filter conf */
  281. HAL_CAN_ConfigFilter(&drv_can->CanHandle, &drv_can->FilterConfig);
  282. }
  283. }
  284. break;
  285. case RT_CAN_CMD_SET_MODE:
  286. argval = (rt_uint32_t) arg;
  287. if (argval != RT_CAN_MODE_NORMAL &&
  288. argval != RT_CAN_MODE_LISEN &&
  289. argval != RT_CAN_MODE_LOOPBACK &&
  290. argval != RT_CAN_MODE_LOOPBACKANLISEN)
  291. {
  292. return -RT_ERROR;
  293. }
  294. if (argval != drv_can->device.config.mode)
  295. {
  296. drv_can->device.config.mode = argval;
  297. return _can_config(&drv_can->device, &drv_can->device.config);
  298. }
  299. break;
  300. case RT_CAN_CMD_SET_BAUD:
  301. argval = (rt_uint32_t) arg;
  302. if (argval != CAN1MBaud &&
  303. argval != CAN800kBaud &&
  304. argval != CAN500kBaud &&
  305. argval != CAN250kBaud &&
  306. argval != CAN125kBaud &&
  307. argval != CAN100kBaud &&
  308. argval != CAN50kBaud &&
  309. argval != CAN20kBaud &&
  310. argval != CAN10kBaud)
  311. {
  312. return -RT_ERROR;
  313. }
  314. if (argval != drv_can->device.config.baud_rate)
  315. {
  316. drv_can->device.config.baud_rate = argval;
  317. return _can_config(&drv_can->device, &drv_can->device.config);
  318. }
  319. break;
  320. case RT_CAN_CMD_SET_PRIV:
  321. argval = (rt_uint32_t) arg;
  322. if (argval != RT_CAN_MODE_PRIV &&
  323. argval != RT_CAN_MODE_NOPRIV)
  324. {
  325. return -RT_ERROR;
  326. }
  327. if (argval != drv_can->device.config.privmode)
  328. {
  329. drv_can->device.config.privmode = argval;
  330. return _can_config(&drv_can->device, &drv_can->device.config);
  331. }
  332. break;
  333. case RT_CAN_CMD_GET_STATUS:
  334. {
  335. rt_uint32_t errtype;
  336. errtype = drv_can->CanHandle.Instance->ESR;
  337. drv_can->device.status.rcverrcnt = errtype >> 24;
  338. drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
  339. drv_can->device.status.lasterrtype = errtype & 0x70;
  340. drv_can->device.status.errcode = errtype & 0x07;
  341. rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
  342. }
  343. break;
  344. }
  345. return RT_EOK;
  346. }
  347. static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
  348. {
  349. CAN_HandleTypeDef *hcan;
  350. hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
  351. struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
  352. CAN_TxHeaderTypeDef txheader = {0};
  353. HAL_CAN_StateTypeDef state = hcan->State;
  354. /* Check the parameters */
  355. RT_ASSERT(IS_CAN_IDTYPE(pmsg->ide));
  356. RT_ASSERT(IS_CAN_RTR(pmsg->rtr));
  357. RT_ASSERT(IS_CAN_DLC(pmsg->len));
  358. if ((state == HAL_CAN_STATE_READY) ||
  359. (state == HAL_CAN_STATE_LISTENING))
  360. {
  361. /*check select mailbox is empty */
  362. switch (1 << box_num)
  363. {
  364. case CAN_TX_MAILBOX0:
  365. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME0) != SET)
  366. {
  367. /* Change CAN state */
  368. hcan->State = HAL_CAN_STATE_ERROR;
  369. /* Return function status */
  370. return -RT_ERROR;
  371. }
  372. break;
  373. case CAN_TX_MAILBOX1:
  374. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME1) != SET)
  375. {
  376. /* Change CAN state */
  377. hcan->State = HAL_CAN_STATE_ERROR;
  378. /* Return function status */
  379. return -RT_ERROR;
  380. }
  381. break;
  382. case CAN_TX_MAILBOX2:
  383. if (HAL_IS_BIT_SET(hcan->Instance->TSR, CAN_TSR_TME2) != SET)
  384. {
  385. /* Change CAN state */
  386. hcan->State = HAL_CAN_STATE_ERROR;
  387. /* Return function status */
  388. return -RT_ERROR;
  389. }
  390. break;
  391. default:
  392. RT_ASSERT(0);
  393. break;
  394. }
  395. if (RT_CAN_STDID == pmsg->ide)
  396. {
  397. txheader.IDE = CAN_ID_STD;
  398. RT_ASSERT(IS_CAN_STDID(pmsg->id));
  399. txheader.StdId = pmsg->id;
  400. }
  401. else
  402. {
  403. txheader.IDE = CAN_ID_EXT;
  404. RT_ASSERT(IS_CAN_EXTID(pmsg->id));
  405. txheader.ExtId = pmsg->id;
  406. }
  407. if (RT_CAN_DTR == pmsg->rtr)
  408. {
  409. txheader.RTR = CAN_RTR_DATA;
  410. }
  411. else
  412. {
  413. txheader.RTR = CAN_RTR_REMOTE;
  414. }
  415. /* Set up the Id */
  416. if (RT_CAN_STDID == pmsg->ide)
  417. {
  418. hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.StdId << CAN_TI0R_STID_Pos) | txheader.RTR;
  419. }
  420. else
  421. {
  422. hcan->Instance->sTxMailBox[box_num].TIR |= (txheader.ExtId << CAN_TI0R_EXID_Pos) | txheader.IDE | txheader.RTR;
  423. }
  424. /* Set up the DLC */
  425. hcan->Instance->sTxMailBox[box_num].TDTR = pmsg->len & 0x0FU;
  426. /* Set up the data field */
  427. WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDHR,
  428. ((uint32_t)pmsg->data[7] << CAN_TDH0R_DATA7_Pos) |
  429. ((uint32_t)pmsg->data[6] << CAN_TDH0R_DATA6_Pos) |
  430. ((uint32_t)pmsg->data[5] << CAN_TDH0R_DATA5_Pos) |
  431. ((uint32_t)pmsg->data[4] << CAN_TDH0R_DATA4_Pos));
  432. WRITE_REG(hcan->Instance->sTxMailBox[box_num].TDLR,
  433. ((uint32_t)pmsg->data[3] << CAN_TDL0R_DATA3_Pos) |
  434. ((uint32_t)pmsg->data[2] << CAN_TDL0R_DATA2_Pos) |
  435. ((uint32_t)pmsg->data[1] << CAN_TDL0R_DATA1_Pos) |
  436. ((uint32_t)pmsg->data[0] << CAN_TDL0R_DATA0_Pos));
  437. /* Request transmission */
  438. SET_BIT(hcan->Instance->sTxMailBox[box_num].TIR, CAN_TI0R_TXRQ);
  439. return RT_EOK;
  440. }
  441. else
  442. {
  443. /* Update error code */
  444. hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
  445. return -RT_ERROR;
  446. }
  447. }
  448. static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
  449. {
  450. HAL_StatusTypeDef status;
  451. CAN_HandleTypeDef *hcan;
  452. struct rt_can_msg *pmsg;
  453. CAN_RxHeaderTypeDef rxheader = {0};
  454. RT_ASSERT(can);
  455. hcan = &((struct stm32_can *)can->parent.user_data)->CanHandle;
  456. pmsg = (struct rt_can_msg *) buf;
  457. /* get data */
  458. status = HAL_CAN_GetRxMessage(hcan, fifo, &rxheader, pmsg->data);
  459. if (HAL_OK != status)
  460. return -RT_ERROR;
  461. /* get id */
  462. if (CAN_ID_STD == rxheader.IDE)
  463. {
  464. pmsg->ide = RT_CAN_STDID;
  465. pmsg->id = rxheader.StdId;
  466. }
  467. else
  468. {
  469. pmsg->ide = RT_CAN_EXTID;
  470. pmsg->id = rxheader.ExtId;
  471. }
  472. /* get type */
  473. if (CAN_RTR_DATA == rxheader.RTR)
  474. {
  475. pmsg->rtr = RT_CAN_DTR;
  476. }
  477. else
  478. {
  479. pmsg->rtr = RT_CAN_RTR;
  480. }
  481. /* get len */
  482. pmsg->len = rxheader.DLC;
  483. /* get hdr */
  484. #ifdef BSP_USING_CAN2
  485. pmsg->hdr = rxheader.FilterMatchIndex;
  486. #else
  487. pmsg->hdr = (rxheader.FilterMatchIndex + 1) >> 1;
  488. #endif
  489. return RT_EOK;
  490. }
  491. static const struct rt_can_ops _can_ops =
  492. {
  493. _can_config,
  494. _can_control,
  495. _can_sendmsg,
  496. _can_recvmsg,
  497. };
  498. static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
  499. {
  500. CAN_HandleTypeDef *hcan;
  501. RT_ASSERT(can);
  502. hcan = &((struct stm32_can *) can->parent.user_data)->CanHandle;
  503. switch (fifo)
  504. {
  505. case CAN_RX_FIFO0:
  506. /* save to user list */
  507. if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_MSG_PENDING))
  508. {
  509. rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
  510. }
  511. /* Check FULL flag for FIFO0 */
  512. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_FULL))
  513. {
  514. /* Clear FIFO0 FULL Flag */
  515. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
  516. }
  517. /* Check Overrun flag for FIFO0 */
  518. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO0_OVERRUN))
  519. {
  520. /* Clear FIFO0 Overrun Flag */
  521. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
  522. rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
  523. }
  524. break;
  525. case CAN_RX_FIFO1:
  526. /* save to user list */
  527. if (HAL_CAN_GetRxFifoFillLevel(hcan, CAN_RX_FIFO1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_MSG_PENDING))
  528. {
  529. rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
  530. }
  531. /* Check FULL flag for FIFO1 */
  532. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FF1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_FULL))
  533. {
  534. /* Clear FIFO1 FULL Flag */
  535. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
  536. }
  537. /* Check Overrun flag for FIFO1 */
  538. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1) && __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_RX_FIFO1_OVERRUN))
  539. {
  540. /* Clear FIFO1 Overrun Flag */
  541. __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
  542. rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
  543. }
  544. break;
  545. }
  546. }
  547. #ifdef BSP_USING_CAN1
  548. /**
  549. * @brief This function handles CAN1 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
  550. */
  551. void CAN1_TX_IRQHandler(void)
  552. {
  553. rt_interrupt_enter();
  554. CAN_HandleTypeDef *hcan;
  555. hcan = &drv_can1.CanHandle;
  556. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
  557. {
  558. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
  559. {
  560. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
  561. }
  562. else
  563. {
  564. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  565. }
  566. /* Write 0 to Clear transmission status flag RQCPx */
  567. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
  568. }
  569. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
  570. {
  571. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
  572. {
  573. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
  574. }
  575. else
  576. {
  577. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  578. }
  579. /* Write 0 to Clear transmission status flag RQCPx */
  580. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
  581. }
  582. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
  583. {
  584. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
  585. {
  586. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
  587. }
  588. else
  589. {
  590. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  591. }
  592. /* Write 0 to Clear transmission status flag RQCPx */
  593. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
  594. }
  595. rt_interrupt_leave();
  596. }
  597. /**
  598. * @brief This function handles CAN1 RX0 interrupts.
  599. */
  600. void CAN1_RX0_IRQHandler(void)
  601. {
  602. rt_interrupt_enter();
  603. _can_rx_isr(&drv_can1.device, CAN_RX_FIFO0);
  604. rt_interrupt_leave();
  605. }
  606. /**
  607. * @brief This function handles CAN1 RX1 interrupts.
  608. */
  609. void CAN1_RX1_IRQHandler(void)
  610. {
  611. rt_interrupt_enter();
  612. _can_rx_isr(&drv_can1.device, CAN_RX_FIFO1);
  613. rt_interrupt_leave();
  614. }
  615. /**
  616. * @brief This function handles CAN1 SCE interrupts.
  617. */
  618. void CAN1_SCE_IRQHandler(void)
  619. {
  620. rt_uint32_t errtype;
  621. CAN_HandleTypeDef *hcan;
  622. hcan = &drv_can1.CanHandle;
  623. errtype = hcan->Instance->ESR;
  624. rt_interrupt_enter();
  625. HAL_CAN_IRQHandler(hcan);
  626. switch ((errtype & 0x70) >> 4)
  627. {
  628. case RT_CAN_BUS_BIT_PAD_ERR:
  629. drv_can1.device.status.bitpaderrcnt++;
  630. break;
  631. case RT_CAN_BUS_FORMAT_ERR:
  632. drv_can1.device.status.formaterrcnt++;
  633. break;
  634. case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
  635. drv_can1.device.status.ackerrcnt++;
  636. if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  637. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  638. else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  639. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  640. else if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  641. rt_hw_can_isr(&drv_can1.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  642. break;
  643. case RT_CAN_BUS_IMPLICIT_BIT_ERR:
  644. case RT_CAN_BUS_EXPLICIT_BIT_ERR:
  645. drv_can1.device.status.biterrcnt++;
  646. break;
  647. case RT_CAN_BUS_CRC_ERR:
  648. drv_can1.device.status.crcerrcnt++;
  649. break;
  650. }
  651. drv_can1.device.status.lasterrtype = errtype & 0x70;
  652. drv_can1.device.status.rcverrcnt = errtype >> 24;
  653. drv_can1.device.status.snderrcnt = (errtype >> 16 & 0xFF);
  654. drv_can1.device.status.errcode = errtype & 0x07;
  655. hcan->Instance->MSR |= CAN_MSR_ERRI;
  656. rt_interrupt_leave();
  657. }
  658. #endif /* BSP_USING_CAN1 */
  659. #ifdef BSP_USING_CAN2
  660. /**
  661. * @brief This function handles CAN2 TX interrupts.
  662. */
  663. void CAN2_TX_IRQHandler(void)
  664. {
  665. rt_interrupt_enter();
  666. CAN_HandleTypeDef *hcan;
  667. hcan = &drv_can2.CanHandle;
  668. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP0))
  669. {
  670. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0))
  671. {
  672. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
  673. }
  674. else
  675. {
  676. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  677. }
  678. /* Write 0 to Clear transmission status flag RQCPx */
  679. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0);
  680. }
  681. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP1))
  682. {
  683. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1))
  684. {
  685. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
  686. }
  687. else
  688. {
  689. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  690. }
  691. /* Write 0 to Clear transmission status flag RQCPx */
  692. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP1);
  693. }
  694. else if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_RQCP2))
  695. {
  696. if (__HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2))
  697. {
  698. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
  699. }
  700. else
  701. {
  702. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  703. }
  704. /* Write 0 to Clear transmission status flag RQCPx */
  705. SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP2);
  706. }
  707. rt_interrupt_leave();
  708. }
  709. /**
  710. * @brief This function handles CAN2 RX0 interrupts.
  711. */
  712. void CAN2_RX0_IRQHandler(void)
  713. {
  714. rt_interrupt_enter();
  715. _can_rx_isr(&drv_can2.device, CAN_RX_FIFO0);
  716. rt_interrupt_leave();
  717. }
  718. /**
  719. * @brief This function handles CAN2 RX1 interrupts.
  720. */
  721. void CAN2_RX1_IRQHandler(void)
  722. {
  723. rt_interrupt_enter();
  724. _can_rx_isr(&drv_can2.device, CAN_RX_FIFO1);
  725. rt_interrupt_leave();
  726. }
  727. /**
  728. * @brief This function handles CAN2 SCE interrupts.
  729. */
  730. void CAN2_SCE_IRQHandler(void)
  731. {
  732. rt_uint32_t errtype;
  733. CAN_HandleTypeDef *hcan;
  734. hcan = &drv_can2.CanHandle;
  735. errtype = hcan->Instance->ESR;
  736. rt_interrupt_enter();
  737. HAL_CAN_IRQHandler(hcan);
  738. switch ((errtype & 0x70) >> 4)
  739. {
  740. case RT_CAN_BUS_BIT_PAD_ERR:
  741. drv_can2.device.status.bitpaderrcnt++;
  742. break;
  743. case RT_CAN_BUS_FORMAT_ERR:
  744. drv_can2.device.status.formaterrcnt++;
  745. break;
  746. case RT_CAN_BUS_ACK_ERR:
  747. drv_can2.device.status.ackerrcnt++;
  748. if (!READ_BIT(drv_can1.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  749. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
  750. else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  751. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
  752. else if (!READ_BIT(drv_can2.CanHandle.Instance->TSR, CAN_FLAG_TXOK0))
  753. rt_hw_can_isr(&drv_can2.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
  754. break;
  755. case RT_CAN_BUS_IMPLICIT_BIT_ERR:
  756. case RT_CAN_BUS_EXPLICIT_BIT_ERR:
  757. drv_can2.device.status.biterrcnt++;
  758. break;
  759. case RT_CAN_BUS_CRC_ERR:
  760. drv_can2.device.status.crcerrcnt++;
  761. break;
  762. }
  763. drv_can2.device.status.lasterrtype = errtype & 0x70;
  764. drv_can2.device.status.rcverrcnt = errtype >> 24;
  765. drv_can2.device.status.snderrcnt = (errtype >> 16 & 0xFF);
  766. drv_can2.device.status.errcode = errtype & 0x07;
  767. hcan->Instance->MSR |= CAN_MSR_ERRI;
  768. rt_interrupt_leave();
  769. }
  770. #endif /* BSP_USING_CAN2 */
  771. /**
  772. * @brief Error CAN callback.
  773. * @param hcan pointer to a CAN_HandleTypeDef structure that contains
  774. * the configuration information for the specified CAN.
  775. * @retval None
  776. */
  777. void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
  778. {
  779. __HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERROR_WARNING |
  780. CAN_IT_ERROR_PASSIVE |
  781. CAN_IT_BUSOFF |
  782. CAN_IT_LAST_ERROR_CODE |
  783. CAN_IT_ERROR |
  784. CAN_IT_RX_FIFO0_MSG_PENDING |
  785. CAN_IT_RX_FIFO0_OVERRUN |
  786. CAN_IT_RX_FIFO0_FULL |
  787. CAN_IT_RX_FIFO1_MSG_PENDING |
  788. CAN_IT_RX_FIFO1_OVERRUN |
  789. CAN_IT_RX_FIFO1_FULL |
  790. CAN_IT_TX_MAILBOX_EMPTY);
  791. }
  792. int rt_hw_can_init(void)
  793. {
  794. struct can_configure config = CANDEFAULTCONFIG;
  795. config.privmode = RT_CAN_MODE_NOPRIV;
  796. config.ticks = 50;
  797. #ifdef RT_CAN_USING_HDR
  798. config.maxhdr = 14;
  799. #ifdef CAN2
  800. config.maxhdr = 28;
  801. #endif
  802. #endif
  803. /* config default filter */
  804. CAN_FilterTypeDef filterConf = {0};
  805. filterConf.FilterIdHigh = 0x0000;
  806. filterConf.FilterIdLow = 0x0000;
  807. filterConf.FilterMaskIdHigh = 0x0000;
  808. filterConf.FilterMaskIdLow = 0x0000;
  809. filterConf.FilterFIFOAssignment = CAN_FILTER_FIFO0;
  810. filterConf.FilterBank = 0;
  811. filterConf.FilterMode = CAN_FILTERMODE_IDMASK;
  812. filterConf.FilterScale = CAN_FILTERSCALE_32BIT;
  813. filterConf.FilterActivation = ENABLE;
  814. filterConf.SlaveStartFilterBank = 14;
  815. #ifdef BSP_USING_CAN1
  816. filterConf.FilterBank = 0;
  817. drv_can1.FilterConfig = filterConf;
  818. drv_can1.device.config = config;
  819. /* register CAN1 device */
  820. rt_hw_can_register(&drv_can1.device,
  821. drv_can1.name,
  822. &_can_ops,
  823. &drv_can1);
  824. #endif /* BSP_USING_CAN1 */
  825. #ifdef BSP_USING_CAN2
  826. filterConf.FilterBank = filterConf.SlaveStartFilterBank;
  827. drv_can2.FilterConfig = filterConf;
  828. drv_can2.device.config = config;
  829. /* register CAN2 device */
  830. rt_hw_can_register(&drv_can2.device,
  831. drv_can2.name,
  832. &_can_ops,
  833. &drv_can2);
  834. #endif /* BSP_USING_CAN2 */
  835. return 0;
  836. }
  837. INIT_BOARD_EXPORT(rt_hw_can_init);
  838. #endif /* BSP_USING_CAN */
  839. /************************** end of file ******************/