stm32f10x_pwr.c 8.5 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f10x_pwr.c
  4. * @author MCD Application Team
  5. * @version V3.4.0
  6. * @date 10/15/2010
  7. * @brief This file provides all the PWR firmware functions.
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * <h2><center>&copy; COPYRIGHT 2010 STMicroelectronics</center></h2>
  19. */
  20. /* Includes ------------------------------------------------------------------*/
  21. #include "stm32f10x_pwr.h"
  22. #include "stm32f10x_rcc.h"
  23. /** @addtogroup STM32F10x_StdPeriph_Driver
  24. * @{
  25. */
  26. /** @defgroup PWR
  27. * @brief PWR driver modules
  28. * @{
  29. */
  30. /** @defgroup PWR_Private_TypesDefinitions
  31. * @{
  32. */
  33. /**
  34. * @}
  35. */
  36. /** @defgroup PWR_Private_Defines
  37. * @{
  38. */
  39. /* --------- PWR registers bit address in the alias region ---------- */
  40. #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
  41. /* --- CR Register ---*/
  42. /* Alias word address of DBP bit */
  43. #define CR_OFFSET (PWR_OFFSET + 0x00)
  44. #define DBP_BitNumber 0x08
  45. #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
  46. /* Alias word address of PVDE bit */
  47. #define PVDE_BitNumber 0x04
  48. #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
  49. /* --- CSR Register ---*/
  50. /* Alias word address of EWUP bit */
  51. #define CSR_OFFSET (PWR_OFFSET + 0x04)
  52. #define EWUP_BitNumber 0x08
  53. #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
  54. /* ------------------ PWR registers bit mask ------------------------ */
  55. /* CR register bit mask */
  56. #define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
  57. #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
  58. /**
  59. * @}
  60. */
  61. /** @defgroup PWR_Private_Macros
  62. * @{
  63. */
  64. /**
  65. * @}
  66. */
  67. /** @defgroup PWR_Private_Variables
  68. * @{
  69. */
  70. /**
  71. * @}
  72. */
  73. /** @defgroup PWR_Private_FunctionPrototypes
  74. * @{
  75. */
  76. /**
  77. * @}
  78. */
  79. /** @defgroup PWR_Private_Functions
  80. * @{
  81. */
  82. /**
  83. * @brief Deinitializes the PWR peripheral registers to their default reset values.
  84. * @param None
  85. * @retval None
  86. */
  87. void PWR_DeInit(void)
  88. {
  89. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
  90. RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
  91. }
  92. /**
  93. * @brief Enables or disables access to the RTC and backup registers.
  94. * @param NewState: new state of the access to the RTC and backup registers.
  95. * This parameter can be: ENABLE or DISABLE.
  96. * @retval None
  97. */
  98. void PWR_BackupAccessCmd(FunctionalState NewState)
  99. {
  100. /* Check the parameters */
  101. assert_param(IS_FUNCTIONAL_STATE(NewState));
  102. *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
  103. }
  104. /**
  105. * @brief Enables or disables the Power Voltage Detector(PVD).
  106. * @param NewState: new state of the PVD.
  107. * This parameter can be: ENABLE or DISABLE.
  108. * @retval None
  109. */
  110. void PWR_PVDCmd(FunctionalState NewState)
  111. {
  112. /* Check the parameters */
  113. assert_param(IS_FUNCTIONAL_STATE(NewState));
  114. *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
  115. }
  116. /**
  117. * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
  118. * @param PWR_PVDLevel: specifies the PVD detection level
  119. * This parameter can be one of the following values:
  120. * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V
  121. * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V
  122. * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V
  123. * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V
  124. * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V
  125. * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V
  126. * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V
  127. * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V
  128. * @retval None
  129. */
  130. void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
  131. {
  132. uint32_t tmpreg = 0;
  133. /* Check the parameters */
  134. assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
  135. tmpreg = PWR->CR;
  136. /* Clear PLS[7:5] bits */
  137. tmpreg &= CR_PLS_MASK;
  138. /* Set PLS[7:5] bits according to PWR_PVDLevel value */
  139. tmpreg |= PWR_PVDLevel;
  140. /* Store the new value */
  141. PWR->CR = tmpreg;
  142. }
  143. /**
  144. * @brief Enables or disables the WakeUp Pin functionality.
  145. * @param NewState: new state of the WakeUp Pin functionality.
  146. * This parameter can be: ENABLE or DISABLE.
  147. * @retval None
  148. */
  149. void PWR_WakeUpPinCmd(FunctionalState NewState)
  150. {
  151. /* Check the parameters */
  152. assert_param(IS_FUNCTIONAL_STATE(NewState));
  153. *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
  154. }
  155. /**
  156. * @brief Enters STOP mode.
  157. * @param PWR_Regulator: specifies the regulator state in STOP mode.
  158. * This parameter can be one of the following values:
  159. * @arg PWR_Regulator_ON: STOP mode with regulator ON
  160. * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
  161. * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
  162. * This parameter can be one of the following values:
  163. * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
  164. * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
  165. * @retval None
  166. */
  167. void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
  168. {
  169. uint32_t tmpreg = 0;
  170. /* Check the parameters */
  171. assert_param(IS_PWR_REGULATOR(PWR_Regulator));
  172. assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
  173. /* Select the regulator state in STOP mode ---------------------------------*/
  174. tmpreg = PWR->CR;
  175. /* Clear PDDS and LPDS bits */
  176. tmpreg &= CR_DS_MASK;
  177. /* Set LPDS bit according to PWR_Regulator value */
  178. tmpreg |= PWR_Regulator;
  179. /* Store the new value */
  180. PWR->CR = tmpreg;
  181. /* Set SLEEPDEEP bit of Cortex System Control Register */
  182. SCB->SCR |= SCB_SCR_SLEEPDEEP;
  183. /* Select STOP mode entry --------------------------------------------------*/
  184. if(PWR_STOPEntry == PWR_STOPEntry_WFI)
  185. {
  186. /* Request Wait For Interrupt */
  187. __WFI();
  188. }
  189. else
  190. {
  191. /* Request Wait For Event */
  192. __WFE();
  193. }
  194. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  195. SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
  196. }
  197. /**
  198. * @brief Enters STANDBY mode.
  199. * @param None
  200. * @retval None
  201. */
  202. void PWR_EnterSTANDBYMode(void)
  203. {
  204. /* Clear Wake-up flag */
  205. PWR->CR |= PWR_CR_CWUF;
  206. /* Select STANDBY mode */
  207. PWR->CR |= PWR_CR_PDDS;
  208. /* Set SLEEPDEEP bit of Cortex System Control Register */
  209. SCB->SCR |= SCB_SCR_SLEEPDEEP;
  210. /* This option is used to ensure that store operations are completed */
  211. #if defined ( __CC_ARM )
  212. __force_stores();
  213. #endif
  214. /* Request Wait For Interrupt */
  215. __WFI();
  216. }
  217. /**
  218. * @brief Checks whether the specified PWR flag is set or not.
  219. * @param PWR_FLAG: specifies the flag to check.
  220. * This parameter can be one of the following values:
  221. * @arg PWR_FLAG_WU: Wake Up flag
  222. * @arg PWR_FLAG_SB: StandBy flag
  223. * @arg PWR_FLAG_PVDO: PVD Output
  224. * @retval The new state of PWR_FLAG (SET or RESET).
  225. */
  226. FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
  227. {
  228. FlagStatus bitstatus = RESET;
  229. /* Check the parameters */
  230. assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
  231. if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
  232. {
  233. bitstatus = SET;
  234. }
  235. else
  236. {
  237. bitstatus = RESET;
  238. }
  239. /* Return the flag status */
  240. return bitstatus;
  241. }
  242. /**
  243. * @brief Clears the PWR's pending flags.
  244. * @param PWR_FLAG: specifies the flag to clear.
  245. * This parameter can be one of the following values:
  246. * @arg PWR_FLAG_WU: Wake Up flag
  247. * @arg PWR_FLAG_SB: StandBy flag
  248. * @retval None
  249. */
  250. void PWR_ClearFlag(uint32_t PWR_FLAG)
  251. {
  252. /* Check the parameters */
  253. assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
  254. PWR->CR |= PWR_FLAG << 2;
  255. }
  256. /**
  257. * @}
  258. */
  259. /**
  260. * @}
  261. */
  262. /**
  263. * @}
  264. */
  265. /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/