drv_spi_bus.c 11 KB

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  1. /*
  2. * File : drv_spi_bus.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2018-03-27 Liuguang the first version.
  13. */
  14. #include "drv_spi_bus.h"
  15. #include "fsl_common.h"
  16. #include "fsl_iomuxc.h"
  17. #include "fsl_lpspi.h"
  18. #ifdef RT_USING_SPI
  19. #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
  20. #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
  21. #endif
  22. #if !defined(LPSPI_CLK_SOURCE)
  23. #define LPSPI_CLK_SOURCE (1U) /* PLL3 PFD0 */
  24. #endif
  25. #if !defined(LPSPI_CLK_SOURCE_DIVIDER)
  26. #define LPSPI_CLK_SOURCE_DIVIDER (7U) /* 8div */
  27. #endif
  28. /* LPSPI1 SCK SDO SDI IOMUX Config */
  29. #if defined(LPSPI1_SCK_GPIO_1)
  30. #define LPSPI1_SCK_GPIO IOMUXC_GPIO_EMC_27_LPSPI1_SCK
  31. #elif defined(LPSPI1_SCK_GPIO_2)
  32. #define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK
  33. #else
  34. #define LPSPI1_SCK_GPIO IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK
  35. #endif
  36. #if defined(LPSPI1_SDO_GPIO_1)
  37. #define LPSPI1_SDO_GPIO IOMUXC_GPIO_EMC_28_LPSPI1_SDO
  38. #elif defined(LPSPI1_SDO_GPIO_2)
  39. #define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO
  40. #else
  41. #define LPSPI1_SDO_GPIO IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO
  42. #endif
  43. #if defined(LPSPI1_SDI_GPIO_1)
  44. #define LPSPI1_SDI_GPIO IOMUXC_GPIO_EMC_29_LPSPI1_SDI
  45. #elif defined(LPSPI1_SDI_GPIO_2)
  46. #define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI
  47. #else
  48. #define LPSPI1_SDI_GPIO IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI
  49. #endif
  50. /* LPSPI2 SCK SDO SDI IOMUX Config */
  51. #if defined(LPSPI2_SCK_GPIO_1)
  52. #define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK
  53. #elif defined(LPSPI2_SCK_GPIO_2)
  54. #define LPSPI2_SCK_GPIO IOMUXC_GPIO_EMC_00_LPSPI2_SCK
  55. #else
  56. #define LPSPI2_SCK_GPIO IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK
  57. #endif
  58. #if defined(LPSPI2_SDO_GPIO_1)
  59. #define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0
  60. #elif defined(LPSPI2_SDO_GPIO_2)
  61. #define LPSPI2_SDO_GPIO IOMUXC_GPIO_EMC_02_LPSPI2_SDO
  62. #else
  63. #define LPSPI2_SDO_GPIO IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0
  64. #endif
  65. #if defined(LPSPI2_SDI_GPIO_1)
  66. #define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI
  67. #elif defined(LPSPI2_SDI_GPIO_2)
  68. #define LPSPI2_SDI_GPIO IOMUXC_GPIO_EMC_03_LPSPI2_SDI
  69. #else
  70. #define LPSPI2_SDI_GPIO IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI
  71. #endif
  72. /* LPSPI3 SCK SDO SDI IOMUX Config */
  73. #if defined(LPSPI3_SCK_GPIO_1)
  74. #define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK
  75. #elif defined(LPSPI3_SCK_GPIO_2)
  76. #define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK
  77. #else
  78. #define LPSPI3_SCK_GPIO IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK
  79. #endif
  80. #if defined(LPSPI3_SDO_GPIO_1)
  81. #define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO
  82. #elif defined(LPSPI3_SDO_GPIO_2)
  83. #define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO
  84. #else
  85. #define LPSPI3_SDO_GPIO IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO
  86. #endif
  87. #if defined(LPSPI3_SDI_GPIO_1)
  88. #define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI
  89. #elif defined(LPSPI3_SDI_GPIO_2)
  90. #define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI
  91. #else
  92. #define LPSPI3_SDI_GPIO IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI
  93. #endif
  94. /* LPSPI4 SCK SDO SDI IOMUX Config */
  95. #if defined(LPSPI4_SCK_GPIO_1)
  96. #define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK
  97. #elif defined(LPSPI4_SCK_GPIO_2)
  98. #define LPSPI4_SCK_GPIO IOMUXC_GPIO_B1_07_LPSPI4_SCK
  99. #else
  100. #define LPSPI4_SCK_GPIO IOMUXC_GPIO_B0_03_LPSPI4_SCK
  101. #endif
  102. #if defined(LPSPI4_SDO_GPIO_1)
  103. #define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO
  104. #elif defined(LPSPI4_SDO_GPIO_2)
  105. #define LPSPI4_SDO_GPIO IOMUXC_GPIO_B1_06_LPSPI4_SDO
  106. #else
  107. #define LPSPI4_SDO_GPIO IOMUXC_GPIO_B0_02_LPSPI4_SDO
  108. #endif
  109. #if defined(LPSPI4_SDI_GPIO_1)
  110. #define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI
  111. #elif defined(LPSPI4_SDI_GPIO_2)
  112. #define LPSPI4_SDI_GPIO IOMUXC_GPIO_B1_05_LPSPI4_SDI
  113. #else
  114. #define LPSPI4_SDI_GPIO IOMUXC_GPIO_B0_01_LPSPI4_SDI
  115. #endif
  116. struct rt1050_spi
  117. {
  118. LPSPI_Type *base;
  119. struct rt_spi_configuration *cfg;
  120. };
  121. struct rt1050_sw_spi_cs
  122. {
  123. rt_uint32_t pin;
  124. };
  125. static uint32_t rt1050_get_lpspi_freq(void)
  126. {
  127. uint32_t freq = 0;
  128. /* CLOCK_GetMux(kCLOCK_LpspiMux):
  129. 00b: derive clock from PLL3 PFD1 720M
  130. 01b: derive clock from PLL3 PFD0 720M
  131. 10b: derive clock from PLL2 528M
  132. 11b: derive clock from PLL2 PFD2 396M
  133. */
  134. switch(CLOCK_GetMux(kCLOCK_LpspiMux))
  135. {
  136. case 0:
  137. freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd1Clk);
  138. break;
  139. case 1:
  140. freq = CLOCK_GetFreq(kCLOCK_Usb1PllPfd0Clk);
  141. break;
  142. case 2:
  143. freq = CLOCK_GetFreq(kCLOCK_SysPllClk);
  144. break;
  145. case 3:
  146. freq = CLOCK_GetFreq(kCLOCK_SysPllPfd2Clk);
  147. break;
  148. }
  149. freq /= (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1U);
  150. return freq;
  151. }
  152. static rt_err_t rt1050_spi_init(LPSPI_Type *base, struct rt_spi_configuration *cfg)
  153. {
  154. lpspi_master_config_t masterConfig;
  155. RT_ASSERT(cfg != RT_NULL);
  156. if(cfg->data_width != 8 && cfg->data_width != 16 && cfg->data_width != 32)
  157. {
  158. return RT_EINVAL;
  159. }
  160. #if defined(RT_USING_SPIBUS1)
  161. if(base == LPSPI1)
  162. {
  163. IOMUXC_SetPinMux (LPSPI1_SCK_GPIO, 0U);
  164. IOMUXC_SetPinConfig(LPSPI1_SCK_GPIO, 0x10B0u);
  165. IOMUXC_SetPinMux (LPSPI1_SDO_GPIO, 0U);
  166. IOMUXC_SetPinConfig(LPSPI1_SDO_GPIO, 0x10B0u);
  167. IOMUXC_SetPinMux (LPSPI1_SDI_GPIO, 0U);
  168. IOMUXC_SetPinConfig(LPSPI1_SDI_GPIO, 0x10B0u);
  169. }
  170. #endif
  171. #if defined(RT_USING_SPIBUS2)
  172. if(base == LPSPI2)
  173. {
  174. IOMUXC_SetPinMux (LPSPI2_SCK_GPIO, 0U);
  175. IOMUXC_SetPinConfig(LPSPI2_SCK_GPIO, 0x10B0u);
  176. IOMUXC_SetPinMux (LPSPI2_SDO_GPIO, 0U);
  177. IOMUXC_SetPinConfig(LPSPI2_SDO_GPIO, 0x10B0u);
  178. IOMUXC_SetPinMux (LPSPI2_SDI_GPIO, 0U);
  179. IOMUXC_SetPinConfig(LPSPI2_SDI_GPIO, 0x10B0u);
  180. }
  181. #endif
  182. #if defined(RT_USING_SPIBUS3)
  183. if(base == LPSPI3)
  184. {
  185. IOMUXC_SetPinMux (LPSPI3_SCK_GPIO, 0U);
  186. IOMUXC_SetPinConfig(LPSPI3_SCK_GPIO, 0x10B0u);
  187. IOMUXC_SetPinMux (LPSPI3_SDO_GPIO, 0U);
  188. IOMUXC_SetPinConfig(LPSPI3_SDO_GPIO, 0x10B0u);
  189. IOMUXC_SetPinMux (LPSPI3_SDI_GPIO, 0U);
  190. IOMUXC_SetPinConfig(LPSPI3_SDI_GPIO, 0x10B0u);
  191. }
  192. #endif
  193. #if defined(RT_USING_SPIBUS4)
  194. if(base == LPSPI4)
  195. {
  196. IOMUXC_SetPinMux (LPSPI4_SCK_GPIO, 0U);
  197. IOMUXC_SetPinConfig(LPSPI4_SCK_GPIO, 0x10B0u);
  198. IOMUXC_SetPinMux (LPSPI4_SDO_GPIO, 0U);
  199. IOMUXC_SetPinConfig(LPSPI4_SDO_GPIO, 0x10B0u);
  200. IOMUXC_SetPinMux (LPSPI4_SDI_GPIO, 0U);
  201. IOMUXC_SetPinConfig(LPSPI4_SDI_GPIO, 0x10B0u);
  202. }
  203. #endif
  204. LPSPI_MasterGetDefaultConfig(&masterConfig);
  205. if(cfg->max_hz > 40*1000*1000)
  206. {
  207. cfg->max_hz = 40*1000*1000;
  208. }
  209. masterConfig.baudRate = cfg->max_hz;
  210. masterConfig.bitsPerFrame = cfg->data_width;
  211. if(cfg->mode & RT_SPI_MSB)
  212. {
  213. masterConfig.direction = kLPSPI_MsbFirst;
  214. }
  215. else
  216. {
  217. masterConfig.direction = kLPSPI_LsbFirst;
  218. }
  219. if(cfg->mode & RT_SPI_CPHA)
  220. {
  221. masterConfig.cpha = kLPSPI_ClockPhaseSecondEdge;
  222. }
  223. else
  224. {
  225. masterConfig.cpha = kLPSPI_ClockPhaseFirstEdge;
  226. }
  227. if(cfg->mode & RT_SPI_CPOL)
  228. {
  229. masterConfig.cpol = kLPSPI_ClockPolarityActiveLow;
  230. }
  231. else
  232. {
  233. masterConfig.cpol = kLPSPI_ClockPolarityActiveHigh;
  234. }
  235. masterConfig.pinCfg = kLPSPI_SdiInSdoOut;
  236. masterConfig.dataOutConfig = kLpspiDataOutTristate;
  237. masterConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.baudRate;
  238. masterConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.baudRate;
  239. masterConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.baudRate;
  240. LPSPI_MasterInit(base, &masterConfig, rt1050_get_lpspi_freq());
  241. base->CFGR1 |= LPSPI_CFGR1_PCSCFG_MASK;
  242. return RT_EOK;
  243. }
  244. rt_err_t rt1050_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin)
  245. {
  246. rt_err_t ret = RT_EOK;
  247. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  248. RT_ASSERT(spi_device != RT_NULL);
  249. struct rt1050_sw_spi_cs *cs_pin = (struct rt1050_sw_spi_cs *)rt_malloc(sizeof(struct rt1050_sw_spi_cs));
  250. RT_ASSERT(cs_pin != RT_NULL);
  251. cs_pin->pin = pin;
  252. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  253. rt_pin_write(pin, PIN_HIGH);
  254. ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  255. return ret;
  256. }
  257. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  258. {
  259. rt_err_t ret = RT_EOK;
  260. struct rt1050_spi *spi = RT_NULL;
  261. RT_ASSERT(cfg != RT_NULL);
  262. RT_ASSERT(device != RT_NULL);
  263. spi = (struct rt1050_spi *)(device->bus->parent.user_data);
  264. spi->cfg = cfg;
  265. ret = rt1050_spi_init(spi->base, cfg);
  266. return ret;
  267. }
  268. static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  269. {
  270. lpspi_transfer_t transfer;
  271. RT_ASSERT(device != RT_NULL);
  272. RT_ASSERT(device->bus != RT_NULL);
  273. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  274. struct rt1050_spi *spi = (struct rt1050_spi *)(device->bus->parent.user_data);
  275. struct rt1050_sw_spi_cs *cs = device->parent.user_data;
  276. if(message->cs_take)
  277. {
  278. rt_pin_write(cs->pin, PIN_LOW);
  279. }
  280. transfer.dataSize = message->length;
  281. transfer.rxData = (uint8_t *)(message->recv_buf);
  282. transfer.txData = (uint8_t *)(message->send_buf);
  283. LPSPI_MasterTransferBlocking(spi->base, &transfer);
  284. if(message->cs_release)
  285. {
  286. rt_pin_write(cs->pin, PIN_HIGH);
  287. }
  288. return message->length;
  289. }
  290. #if defined(RT_USING_SPIBUS1)
  291. static struct rt1050_spi spi1 =
  292. {
  293. .base = LPSPI1
  294. };
  295. static struct rt_spi_bus spi1_bus =
  296. {
  297. .parent.user_data = &spi1
  298. };
  299. #endif
  300. #if defined(RT_USING_SPIBUS2)
  301. static struct rt1050_spi spi2 =
  302. {
  303. .base = LPSPI2
  304. };
  305. static struct rt_spi_bus spi2_bus =
  306. {
  307. .parent.user_data = &spi2
  308. };
  309. #endif
  310. #if defined(RT_USING_SPIBUS3)
  311. static struct rt1050_spi spi3 =
  312. {
  313. .base = LPSPI3
  314. };
  315. static struct rt_spi_bus spi3_bus =
  316. {
  317. .parent.user_data = &spi3
  318. };
  319. #endif
  320. #if defined(RT_USING_SPIBUS4)
  321. static struct rt1050_spi spi4 =
  322. {
  323. .base = LPSPI4
  324. };
  325. static struct rt_spi_bus spi4_bus =
  326. {
  327. .parent.user_data = &spi4
  328. };
  329. #endif
  330. static struct rt_spi_ops rt1050_spi_ops =
  331. {
  332. .configure = spi_configure,
  333. .xfer = spixfer
  334. };
  335. int rt_hw_spi_bus_init(void)
  336. {
  337. #if defined(RT_USING_SPIBUS1) || defined(RT_USING_SPIBUS2) || \
  338. defined(RT_USING_SPIBUS3) || defined(RT_USING_SPIBUS4)
  339. CLOCK_SetMux(kCLOCK_LpspiMux, LPSPI_CLK_SOURCE);
  340. CLOCK_SetDiv(kCLOCK_LpspiDiv, LPSPI_CLK_SOURCE_DIVIDER);
  341. CLOCK_EnableClock(kCLOCK_Iomuxc);
  342. #endif
  343. #if defined(RT_USING_SPIBUS1)
  344. rt_spi_bus_register(&spi1_bus, "spi1", &rt1050_spi_ops);
  345. #endif
  346. #if defined(RT_USING_SPIBUS2)
  347. rt_spi_bus_register(&spi2_bus, "spi2", &rt1050_spi_ops);
  348. #endif
  349. #if defined(RT_USING_SPIBUS3)
  350. rt_spi_bus_register(&spi3_bus, "spi3", &rt1050_spi_ops);
  351. #endif
  352. #if defined(RT_USING_SPIBUS4)
  353. rt_spi_bus_register(&spi4_bus, "spi4", &rt1050_spi_ops);
  354. #endif
  355. return RT_EOK;
  356. }
  357. INIT_BOARD_EXPORT(rt_hw_spi_bus_init);
  358. #endif