drv_rtc.c 6.5 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-01-28 greedyhao first version
  9. * 2021-03-19 iysheng modify just set time first power up
  10. * 2021-03-26 iysheng add alarm and 1s interrupt support
  11. */
  12. #include "board.h"
  13. #include <time.h>
  14. #include <sys/time.h>
  15. #ifdef BSP_USING_ONCHIP_RTC
  16. //#define DRV_DEBUG
  17. #define LOG_TAG "drv.rtc"
  18. #include <drv_log.h>
  19. static struct rt_device rtc;
  20. /************** HAL Start *******************/
  21. #define IRTC_ENTER_CRITICAL() uint32_t cpu_ie = PICCON & BIT(0); PICCONCLR = BIT(0);
  22. #define IRTC_EXIT_CRITICAL() PICCON |= cpu_ie
  23. uint8_t get_weekday(struct tm *const _tm)
  24. {
  25. uint8_t weekday;
  26. time_t secs = timegm(_tm);
  27. weekday = (secs / 86400 + 4) % 7;
  28. return weekday;
  29. }
  30. void irtc_write(uint32_t cmd)
  31. {
  32. RTCDAT = cmd;
  33. while (RTCCON & RTC_CON_TRANS_DONE);
  34. }
  35. uint8_t irtc_read(void)
  36. {
  37. RTCDAT = 0x00;
  38. while (RTCCON & RTC_CON_TRANS_DONE);
  39. return (uint8_t)RTCDAT;
  40. }
  41. void irtc_time_write(uint32_t cmd, uint32_t dat)
  42. {
  43. IRTC_ENTER_CRITICAL();
  44. RTCCON |= RTC_CON_CHIP_SELECT;
  45. irtc_write(cmd | RTC_WR);
  46. irtc_write((uint8_t)(dat >> 24));
  47. irtc_write((uint8_t)(dat >> 16));
  48. irtc_write((uint8_t)(dat >> 8));
  49. irtc_write((uint8_t)(dat >> 0));
  50. RTCCON &= ~RTC_CON_CHIP_SELECT;
  51. IRTC_EXIT_CRITICAL();
  52. }
  53. uint32_t irtc_time_read(uint32_t cmd)
  54. {
  55. uint32_t rd_val;
  56. IRTC_ENTER_CRITICAL();
  57. RTCCON |= RTC_CON_CHIP_SELECT;
  58. irtc_write(cmd | RTC_RD);
  59. *((uint8_t *)&rd_val + 3) = irtc_read();
  60. *((uint8_t *)&rd_val + 2) = irtc_read();
  61. *((uint8_t *)&rd_val + 1) = irtc_read();
  62. *((uint8_t *)&rd_val + 0) = irtc_read();
  63. RTCCON &= ~RTC_CON_CHIP_SELECT;
  64. IRTC_EXIT_CRITICAL();
  65. return rd_val;
  66. }
  67. void irtc_sfr_write(uint32_t cmd, uint8_t dat)
  68. {
  69. IRTC_ENTER_CRITICAL();
  70. RTCCON |= RTC_CON_CHIP_SELECT;
  71. irtc_write(cmd | RTC_WR);
  72. irtc_write(dat);
  73. RTCCON &= ~RTC_CON_CHIP_SELECT;
  74. IRTC_EXIT_CRITICAL();
  75. }
  76. uint8_t irtc_sfr_read(uint32_t cmd)
  77. {
  78. uint8_t rd_val;
  79. IRTC_ENTER_CRITICAL();
  80. RTCCON |= RTC_CON_CHIP_SELECT;
  81. irtc_write(cmd | RTC_RD);
  82. rd_val = irtc_read();
  83. RTCCON &= ~RTC_CON_CHIP_SELECT;
  84. IRTC_EXIT_CRITICAL();
  85. }
  86. static void _init_rtc_clock(void)
  87. {
  88. uint8_t rtccon0;
  89. uint8_t rtccon2;
  90. rtccon0 = irtc_sfr_read(RTCCON0_CMD);
  91. rtccon2 = irtc_sfr_read(RTCCON2_CMD);
  92. #ifdef RTC_USING_INTERNAL_CLK
  93. rtccon0 &= ~RTC_CON0_XOSC32K_ENABLE;
  94. rtccon0 |= RTC_CON0_INTERNAL_32K;
  95. rtccon2 | RTC_CON2_32K_SELECT;
  96. #else
  97. rtccon0 |= RTC_CON0_XOSC32K_ENABLE;
  98. rtccon0 &= ~RTC_CON0_INTERNAL_32K;
  99. rtccon2 & ~RTC_CON2_32K_SELECT;
  100. #endif
  101. irtc_sfr_write(RTCCON0_CMD, rtccon0);
  102. irtc_sfr_write(RTCCON2_CMD, rtccon2);
  103. }
  104. void hal_rtc_init(void)
  105. {
  106. time_t sec = 0;
  107. struct tm tm_new = {0};
  108. uint8_t temp;
  109. _init_rtc_clock();
  110. temp = irtc_sfr_read(RTCCON0_CMD);
  111. if (temp & RTC_CON0_PWRUP_FIRST) {
  112. temp &= ~RTC_CON0_PWRUP_FIRST;
  113. irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
  114. tm_new.tm_mday = 29;
  115. tm_new.tm_mon = 1 - 1;
  116. tm_new.tm_year = 2021 - 1900;
  117. sec = timegm(&tm_new);
  118. irtc_time_write(RTCCNT_CMD, sec);
  119. }
  120. #ifdef RT_USING_ALARM
  121. RTCCON |= RTC_CON_ALM_INTERRUPT;
  122. #ifdef RTC_USING_1S_INT
  123. RTCCON |= RTC_CON_1S_INTERRUPT;
  124. #endif
  125. #endif
  126. }
  127. /************** HAL End *******************/
  128. static time_t get_rtc_time_stamp(void)
  129. {
  130. time_t sec = 0;
  131. sec = irtc_time_read(RTCCNT_CMD);
  132. LOG_D("get rtc time.");
  133. return sec;
  134. }
  135. static rt_err_t set_rtc_time_stamp(time_t time_stamp)
  136. {
  137. irtc_time_write(RTCCNT_CMD, time_stamp);
  138. return RT_EOK;
  139. }
  140. static rt_err_t set_rtc_alarm_stamp(time_t alarm_stamp)
  141. {
  142. irtc_time_write(RTCALM_CMD, alarm_stamp);
  143. return RT_EOK;
  144. }
  145. static time_t get_rtc_alarm_stamp(void)
  146. {
  147. time_t sec = 0;
  148. sec = irtc_time_read(RTCALM_CMD);
  149. return sec;
  150. }
  151. static void rt_rtc_init(void)
  152. {
  153. hal_rtc_init();
  154. }
  155. static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args)
  156. {
  157. rt_err_t result = RT_EOK;
  158. RT_ASSERT(dev != RT_NULL);
  159. switch (cmd)
  160. {
  161. case RT_DEVICE_CTRL_RTC_GET_TIME:
  162. *(time_t *)args = get_rtc_time_stamp();
  163. LOG_D("RTC: get rtc_time %x", *(time_t *)args);
  164. break;
  165. case RT_DEVICE_CTRL_RTC_SET_TIME:
  166. if (set_rtc_time_stamp(*(time_t *)args))
  167. {
  168. result = -RT_ERROR;
  169. }
  170. LOG_D("RTC: set rtc_time %x", *(time_t *)args);
  171. break;
  172. case RT_DEVICE_CTRL_RTC_SET_ALARM:
  173. if (set_rtc_alarm_stamp(*(time_t *)args))
  174. {
  175. result = -RT_ERROR;
  176. }
  177. LOG_D("RTC: set alarm_stamp %x", *(time_t *)args);
  178. break;
  179. case RT_DEVICE_CTRL_RTC_GET_ALARM:
  180. *(time_t *)args = get_rtc_alarm_stamp();
  181. LOG_D("RTC: get alarm_stamp %x", *(time_t *)args);
  182. break;
  183. }
  184. return result;
  185. }
  186. #ifdef RT_USING_DEVICE_OPS
  187. const static struct rt_device_ops rtc_ops =
  188. {
  189. RT_NULL,
  190. RT_NULL,
  191. RT_NULL,
  192. RT_NULL,
  193. RT_NULL,
  194. ab32_rtc_control
  195. };
  196. #endif
  197. static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
  198. {
  199. RT_ASSERT(device != RT_NULL);
  200. rt_rtc_init();
  201. #ifdef RT_USING_DEVICE_OPS
  202. device->ops = &rtc_ops;
  203. #else
  204. device->init = RT_NULL;
  205. device->open = RT_NULL;
  206. device->close = RT_NULL;
  207. device->read = RT_NULL;
  208. device->write = RT_NULL;
  209. device->control = ab32_rtc_control;
  210. #endif
  211. device->type = RT_Device_Class_RTC;
  212. device->rx_indicate = RT_NULL;
  213. device->tx_complete = RT_NULL;
  214. device->user_data = RT_NULL;
  215. /* register a character device */
  216. return rt_device_register(device, name, flag);
  217. }
  218. #ifdef RT_USING_ALARM
  219. RT_SECTION(".irq.rtc")
  220. static void rtc_isr(int vector, void *param)
  221. {
  222. rt_interrupt_enter();
  223. if (RTCCON & RTC_CON_ALM_PEND)
  224. {
  225. RTCCPND |= RTC_CPND_ALM;
  226. }
  227. #ifdef RTC_USING_1S_INT
  228. if (RTCCON & RTC_CON_1S_PEND)
  229. {
  230. RTCCPND |= RTC_CPND_1S;
  231. }
  232. #endif
  233. rt_interrupt_leave();
  234. }
  235. #endif
  236. int rt_hw_rtc_init(void)
  237. {
  238. rt_err_t result;
  239. result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
  240. if (result != RT_EOK)
  241. {
  242. LOG_E("rtc register err code: %d", result);
  243. return result;
  244. }
  245. #ifdef RT_USING_ALARM
  246. rt_hw_interrupt_install(IRQ_RTC_VECTOR, rtc_isr, RT_NULL, "rtc_isr");
  247. #endif
  248. LOG_D("rtc init success");
  249. return RT_EOK;
  250. }
  251. INIT_DEVICE_EXPORT(rt_hw_rtc_init);
  252. #endif /* BSP_USING_ONCHIP_RTC */