drv_uart.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569
  1. /*
  2. * File : drv_uart.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2017-10-10 Tanek the first version
  13. * 2018-03-17 laiyiketang Add other uart.
  14. */
  15. #include <rtthread.h>
  16. #include "drv_uart.h"
  17. #include "fsl_common.h"
  18. #include "fsl_lpuart.h"
  19. #include "fsl_iomuxc.h"
  20. #ifdef RT_USING_SERIAL
  21. /* GPIO外设时钟会在LPUART_Init中自动配置, 如果定义了以下宏则不会自动配置 */
  22. #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
  23. #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
  24. #endif
  25. #if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \
  26. !defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \
  27. !defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \
  28. !defined(RT_USING_UART7) && !defined(RT_USING_UART8)
  29. #error "Please define at least one UARTx"
  30. #endif
  31. #include <rtdevice.h>
  32. /* imxrt uart driver */
  33. struct imxrt_uart
  34. {
  35. LPUART_Type * uart_base;
  36. IRQn_Type irqn;
  37. struct rt_serial_device * serial;
  38. char *device_name;
  39. };
  40. static void uart_isr(struct rt_serial_device *serial);
  41. #if defined(RT_USING_UART1)
  42. struct rt_serial_device serial1;
  43. void LPUART1_IRQHandler(void)
  44. {
  45. uart_isr(&serial1);
  46. }
  47. #endif /* RT_USING_UART1 */
  48. #if defined(RT_USING_UART2)
  49. struct rt_serial_device serial2;
  50. void LPUART2_IRQHandler(void)
  51. {
  52. uart_isr(&serial2);
  53. }
  54. #endif /* RT_USING_UART2 */
  55. #if defined(RT_USING_UART3)
  56. struct rt_serial_device serial3;
  57. void LPUART3_IRQHandler(void)
  58. {
  59. uart_isr(&serial3);
  60. }
  61. #endif /* RT_USING_UART3 */
  62. #if defined(RT_USING_UART4)
  63. struct rt_serial_device serial4;
  64. void LPUART4_IRQHandler(void)
  65. {
  66. uart_isr(&serial4);
  67. }
  68. #endif /* RT_USING_UART4 */
  69. #if defined(RT_USING_UART5)
  70. struct rt_serial_device serial5;
  71. void LPUART5_IRQHandler(void)
  72. {
  73. uart_isr(&serial5);
  74. }
  75. #endif /* RT_USING_UART5 */
  76. #if defined(RT_USING_UART6)
  77. struct rt_serial_device serial6;
  78. void LPUART6_IRQHandler(void)
  79. {
  80. uart_isr(&serial6);
  81. }
  82. #endif /* RT_USING_UART6 */
  83. #if defined(RT_USING_UART7)
  84. struct rt_serial_device serial7;
  85. void LPUART7_IRQHandler(void)
  86. {
  87. uart_isr(&serial7);
  88. }
  89. #endif /* RT_USING_UART7 */
  90. #if defined(RT_USING_UART8)
  91. struct rt_serial_device serial8;
  92. void LPUART8_IRQHandler(void)
  93. {
  94. uart_isr(&serial8);
  95. }
  96. #endif /* RT_USING_UART8 */
  97. static const struct imxrt_uart uarts[] = {
  98. #ifdef RT_USING_UART1
  99. {
  100. LPUART1,
  101. LPUART1_IRQn,
  102. &serial1,
  103. "uart1",
  104. },
  105. #endif
  106. #ifdef RT_USING_UART2
  107. {
  108. LPUART2,
  109. LPUART2_IRQn,
  110. &serial2,
  111. "uart2",
  112. },
  113. #endif
  114. #ifdef RT_USING_UART3
  115. {
  116. LPUART3,
  117. LPUART3_IRQn,
  118. &serial3,
  119. "uart3",
  120. },
  121. #endif
  122. #ifdef RT_USING_UART4
  123. {
  124. LPUART4,
  125. LPUART4_IRQn,
  126. &serial4,
  127. "uart4",
  128. },
  129. #endif
  130. #ifdef RT_USING_UART5
  131. {
  132. LPUART5,
  133. LPUART5_IRQn,
  134. &serial5,
  135. "uart5",
  136. },
  137. #endif
  138. #ifdef RT_USING_UART6
  139. {
  140. LPUART6,
  141. LPUART6_IRQn,
  142. &serial6,
  143. "uart6",
  144. },
  145. #endif
  146. #ifdef RT_USING_UART7
  147. {
  148. LPUART7,
  149. LPUART7_IRQn,
  150. &serial7,
  151. "uart7",
  152. },
  153. #endif
  154. #ifdef RT_USING_UART8
  155. {
  156. LPUART8,
  157. LPUART8_IRQn,
  158. &serial8,
  159. "uart8",
  160. },
  161. #endif
  162. };
  163. /* Get debug console frequency. */
  164. uint32_t BOARD_DebugConsoleSrcFreq(void)
  165. {
  166. uint32_t freq;
  167. /* To make it simple, we assume default PLL and divider settings, and the only variable
  168. from application is use PLL3 source or OSC source */
  169. if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
  170. {
  171. freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  172. }
  173. else
  174. {
  175. freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
  176. }
  177. return freq;
  178. }
  179. /**
  180. * @brief UART MSP Initialization
  181. * This function configures the hardware resources used in this example:
  182. * - Peripheral's clock enable
  183. * - Peripheral's GPIO Configuration
  184. * - NVIC configuration for UART interrupt request enable
  185. * @param huart: UART handle pointer
  186. * @retval None
  187. */
  188. void imxrt_uart_gpio_init(struct imxrt_uart *uart)
  189. {
  190. if (uart->uart_base != RT_NULL)
  191. {
  192. #ifdef RT_USING_UART1
  193. CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
  194. IOMUXC_SetPinMux(
  195. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
  196. 0U); /* Software Input On Field: Input Path is determined by functionality */
  197. IOMUXC_SetPinMux(
  198. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
  199. 0U); /* Software Input On Field: Input Path is determined by functionality */
  200. IOMUXC_SetPinConfig(
  201. IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
  202. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  203. Drive Strength Field: R0/6
  204. Speed Field: medium(100MHz)
  205. Open Drain Enable Field: Open Drain Disabled
  206. Pull / Keep Enable Field: Pull/Keeper Enabled
  207. Pull / Keep Select Field: Keeper
  208. Pull Up / Down Config. Field: 100K Ohm Pull Down
  209. Hyst. Enable Field: Hysteresis Disabled */
  210. IOMUXC_SetPinConfig(
  211. IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
  212. 0x10B0u); /* Slew Rate Field: Slow Slew Rate
  213. Drive Strength Field: R0/6
  214. Speed Field: medium(100MHz)
  215. Open Drain Enable Field: Open Drain Disabled
  216. Pull / Keep Enable Field: Pull/Keeper Enabled
  217. Pull / Keep Select Field: Keeper
  218. Pull Up / Down Config. Field: 100K Ohm Pull Down
  219. Hyst. Enable Field: Hysteresis Disabled */
  220. #endif
  221. #ifdef RT_USING_UART2
  222. CLOCK_EnableClock(kCLOCK_Iomuxc);
  223. IOMUXC_SetPinMux(
  224. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  225. 0U);
  226. IOMUXC_SetPinMux(
  227. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  228. 0U);
  229. IOMUXC_SetPinConfig(
  230. IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
  231. 0x10B0u);
  232. IOMUXC_SetPinConfig(
  233. IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
  234. 0x10B0u);
  235. #endif
  236. #ifdef RT_USING_UART3
  237. CLOCK_EnableClock(kCLOCK_Iomuxc);
  238. IOMUXC_SetPinMux(
  239. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  240. 0U);
  241. IOMUXC_SetPinMux(
  242. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  243. 0U);
  244. IOMUXC_SetPinConfig(
  245. IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
  246. 0x10B0u);
  247. IOMUXC_SetPinConfig(
  248. IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
  249. 0x10B0u);
  250. #endif
  251. #ifdef RT_USING_UART4
  252. CLOCK_EnableClock(kCLOCK_Iomuxc);
  253. IOMUXC_SetPinMux(
  254. IOMUXC_GPIO_B1_00_LPUART4_TX,
  255. 0U);
  256. IOMUXC_SetPinMux(
  257. IOMUXC_GPIO_B1_01_LPUART4_RX,
  258. 0U);
  259. IOMUXC_SetPinConfig(
  260. IOMUXC_GPIO_B1_00_LPUART4_TX,
  261. 0x10B0u);
  262. IOMUXC_SetPinConfig(
  263. IOMUXC_GPIO_B1_01_LPUART4_RX,
  264. 0x10B0u);
  265. #endif
  266. #ifdef RT_USING_UART5
  267. CLOCK_EnableClock(kCLOCK_Iomuxc);
  268. IOMUXC_SetPinMux(
  269. IOMUXC_GPIO_B1_12_LPUART5_TX,
  270. 0U);
  271. IOMUXC_SetPinMux(
  272. IOMUXC_GPIO_B1_13_LPUART5_RX,
  273. 0U);
  274. IOMUXC_SetPinConfig(
  275. IOMUXC_GPIO_B1_12_LPUART5_TX,
  276. 0x10B0u);
  277. IOMUXC_SetPinConfig(
  278. IOMUXC_GPIO_B1_13_LPUART5_RX,
  279. 0x10B0u);
  280. #endif
  281. #ifdef RT_USING_UART6
  282. CLOCK_EnableClock(kCLOCK_Iomuxc);
  283. IOMUXC_SetPinMux(
  284. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  285. 0U);
  286. IOMUXC_SetPinMux(
  287. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  288. 0U);
  289. IOMUXC_SetPinConfig(
  290. IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
  291. 0x10B0u);
  292. IOMUXC_SetPinConfig(
  293. IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
  294. 0x10B0u);
  295. #endif
  296. #ifdef RT_USING_UART7
  297. CLOCK_EnableClock(kCLOCK_Iomuxc);
  298. IOMUXC_SetPinMux(
  299. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  300. 0U);
  301. IOMUXC_SetPinMux(
  302. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  303. 0U);
  304. IOMUXC_SetPinConfig(
  305. IOMUXC_GPIO_EMC_31_LPUART7_TX,
  306. 0x10B0u);
  307. IOMUXC_SetPinConfig(
  308. IOMUXC_GPIO_EMC_32_LPUART7_RX,
  309. 0x10B0u);
  310. #endif
  311. #ifdef RT_USING_UART8
  312. CLOCK_EnableClock(kCLOCK_Iomuxc);
  313. IOMUXC_SetPinMux(
  314. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  315. 0U);
  316. IOMUXC_SetPinMux(
  317. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  318. 0U);
  319. IOMUXC_SetPinConfig(
  320. IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
  321. 0x10B0u);
  322. IOMUXC_SetPinConfig(
  323. IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
  324. 0x10B0u);
  325. #endif
  326. }
  327. else
  328. {
  329. RT_ASSERT(RT_NULL);
  330. }
  331. }
  332. static rt_err_t imxrt_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  333. {
  334. struct imxrt_uart *uart;
  335. lpuart_config_t config;
  336. RT_ASSERT(serial != RT_NULL);
  337. RT_ASSERT(cfg != RT_NULL);
  338. uart = (struct imxrt_uart *)serial->parent.user_data;
  339. imxrt_uart_gpio_init(uart);
  340. LPUART_GetDefaultConfig(&config);
  341. config.baudRate_Bps = cfg->baud_rate;
  342. switch (cfg->data_bits)
  343. {
  344. case DATA_BITS_7:
  345. config.dataBitsCount = kLPUART_SevenDataBits;
  346. break;
  347. default:
  348. config.dataBitsCount = kLPUART_EightDataBits;
  349. break;
  350. }
  351. switch (cfg->stop_bits)
  352. {
  353. case STOP_BITS_2:
  354. config.stopBitCount = kLPUART_TwoStopBit;
  355. break;
  356. default:
  357. config.stopBitCount = kLPUART_OneStopBit;
  358. break;
  359. }
  360. switch (cfg->parity)
  361. {
  362. case PARITY_ODD:
  363. config.parityMode = kLPUART_ParityOdd;
  364. break;
  365. case PARITY_EVEN:
  366. config.parityMode = kLPUART_ParityEven;
  367. break;
  368. default:
  369. config.parityMode = kLPUART_ParityDisabled;
  370. break;
  371. }
  372. config.enableTx = true;
  373. config.enableRx = true;
  374. LPUART_Init(uart->uart_base, &config, BOARD_DebugConsoleSrcFreq());
  375. return RT_EOK;
  376. }
  377. static rt_err_t imxrt_control(struct rt_serial_device *serial, int cmd, void *arg)
  378. {
  379. struct imxrt_uart *uart;
  380. RT_ASSERT(serial != RT_NULL);
  381. uart = (struct imxrt_uart *)serial->parent.user_data;
  382. switch (cmd)
  383. {
  384. case RT_DEVICE_CTRL_CLR_INT:
  385. /* disable interrupt */
  386. LPUART_DisableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
  387. /* disable rx irq */
  388. DisableIRQ(uart->irqn);
  389. break;
  390. case RT_DEVICE_CTRL_SET_INT:
  391. /* enable interrupt */
  392. LPUART_EnableInterrupts(uart->uart_base, kLPUART_RxDataRegFullInterruptEnable);
  393. /* enable rx irq */
  394. EnableIRQ(uart->irqn);
  395. break;
  396. }
  397. return RT_EOK;
  398. }
  399. static int imxrt_putc(struct rt_serial_device *serial, char ch)
  400. {
  401. struct imxrt_uart *uart;
  402. RT_ASSERT(serial != RT_NULL);
  403. uart = (struct imxrt_uart *)serial->parent.user_data;
  404. LPUART_WriteByte(uart->uart_base, ch);
  405. while(!(LPUART_GetStatusFlags(uart->uart_base) & kLPUART_TxDataRegEmptyFlag));
  406. return 1;
  407. }
  408. static int imxrt_getc(struct rt_serial_device *serial)
  409. {
  410. int ch;
  411. struct imxrt_uart *uart;
  412. RT_ASSERT(serial != RT_NULL);
  413. uart = (struct imxrt_uart *)serial->parent.user_data;
  414. ch = -1;
  415. if (LPUART_GetStatusFlags(uart->uart_base) & kLPUART_RxDataRegFullFlag)
  416. ch = LPUART_ReadByte(uart->uart_base);
  417. return ch;
  418. }
  419. /**
  420. * Uart common interrupt process. This need add to uart ISR.
  421. *
  422. * @param serial serial device
  423. */
  424. static void uart_isr(struct rt_serial_device *serial)
  425. {
  426. struct imxrt_uart *uart;
  427. LPUART_Type *base;
  428. RT_ASSERT(serial != RT_NULL);
  429. uart = (struct imxrt_uart *) serial->parent.user_data;
  430. RT_ASSERT(uart != RT_NULL);
  431. base = uart->uart_base;
  432. RT_ASSERT(base != RT_NULL);
  433. /* enter interrupt */
  434. rt_interrupt_enter();
  435. /* UART in mode Receiver -------------------------------------------------*/
  436. if (LPUART_GetStatusFlags(base) & kLPUART_RxDataRegFullFlag)
  437. {
  438. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  439. }
  440. /* If RX overrun. */
  441. if (LPUART_STAT_OR_MASK & base->STAT)
  442. {
  443. /* Clear overrun flag, otherwise the RX does not work. */
  444. base->STAT = ((base->STAT & 0x3FE00000U) | LPUART_STAT_OR_MASK);
  445. }
  446. /* leave interrupt */
  447. rt_interrupt_leave();
  448. }
  449. static const struct rt_uart_ops imxrt_uart_ops =
  450. {
  451. imxrt_configure,
  452. imxrt_control,
  453. imxrt_putc,
  454. imxrt_getc,
  455. };
  456. int imxrt_hw_usart_init(void)
  457. {
  458. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  459. int i;
  460. for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
  461. {
  462. uarts[i].serial->ops = &imxrt_uart_ops;
  463. uarts[i].serial->config = config;
  464. /* register UART1 device */
  465. rt_hw_serial_register(uarts[i].serial,
  466. uarts[i].device_name,
  467. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  468. (void *)&uarts[i]);
  469. }
  470. return 0;
  471. }
  472. INIT_BOARD_EXPORT(imxrt_hw_usart_init);
  473. #endif /*RT_USING_SERIAL */