mmcsd_core.c 13 KB

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  1. /*
  2. * File : mmcsd_core.c
  3. * This file is part of RT-Thread RTOS
  4. * COPYRIGHT (C) 2006, RT-Thread Development Team
  5. *
  6. * The license and distribution terms for this file may be
  7. * found in the file LICENSE in this distribution or at
  8. * http://www.rt-thread.org/license/LICENSE
  9. *
  10. * Change Logs:
  11. * Date Author Notes
  12. * 2011-07-25 weety first version
  13. */
  14. #include <rtthread.h>
  15. #include <drivers/mmcsd_core.h>
  16. #include <drivers/sd.h>
  17. #ifndef RT_MMCSD_STACK_SIZE
  18. #define RT_MMCSD_STACK_SIZE 1024
  19. #endif
  20. #ifndef RT_MMCSD_THREAD_PREORITY
  21. #define RT_MMCSD_THREAD_PREORITY 0x40
  22. #endif
  23. //static struct rt_semaphore mmcsd_sem;
  24. static struct rt_thread mmcsd_detect_thread;
  25. static rt_uint8_t mmcsd_stack[RT_MMCSD_STACK_SIZE];
  26. static struct rt_mailbox mmcsd_detect_mb;
  27. static rt_uint32_t mmcsd_detect_mb_pool[4];
  28. void mmcsd_host_lock(struct rt_mmcsd_host *host)
  29. {
  30. rt_sem_take(&host->bus_lock, RT_WAITING_FOREVER);
  31. }
  32. void mmcsd_host_unlock(struct rt_mmcsd_host *host)
  33. {
  34. rt_sem_release(&host->bus_lock);
  35. }
  36. void mmcsd_req_complete(struct rt_mmcsd_host *host)
  37. {
  38. rt_sem_release(&host->sem_ack);
  39. }
  40. void mmcsd_send_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
  41. {
  42. req->cmd->err = 0;
  43. req->cmd->mrq = req;
  44. if (req->data)
  45. {
  46. req->cmd->data = req->data;
  47. req->data->err = 0;
  48. req->data->mrq = req;
  49. if (req->stop)
  50. {
  51. req->data->stop = req->stop;
  52. req->stop->err = 0;
  53. req->stop->mrq = req;
  54. }
  55. }
  56. host->ops->request(host, req);
  57. rt_sem_take(&host->sem_ack, RT_WAITING_FOREVER);
  58. }
  59. rt_int32_t mmcsd_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd, int retries)
  60. {
  61. struct rt_mmcsd_req req;
  62. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  63. rt_memset(cmd->resp, 0, sizeof(cmd->resp));
  64. req.cmd = cmd;
  65. cmd->data = RT_NULL;
  66. mmcsd_send_request(host, &req);
  67. return cmd->err;
  68. }
  69. rt_int32_t mmcsd_go_idle(struct rt_mmcsd_host *host)
  70. {
  71. rt_int32_t err;
  72. struct rt_mmcsd_cmd cmd;
  73. if (!controller_is_spi(host)) {
  74. mmcsd_set_chip_select(host, MMCSD_CS_HIGH);
  75. mmcsd_delay_ms(1);
  76. }
  77. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  78. cmd.cmd_code = GO_IDLE_STATE;
  79. cmd.arg = 0;
  80. cmd.flags = RESP_SPI_R1 | RESP_NONE | CMD_BC;
  81. err = mmcsd_send_cmd(host, &cmd, 0);
  82. mmcsd_delay_ms(1);
  83. if (!controller_is_spi(host))
  84. {
  85. mmcsd_set_chip_select(host, MMCSD_CS_IGNORE);
  86. mmcsd_delay_ms(1);
  87. }
  88. return err;
  89. }
  90. rt_int32_t mmcsd_spi_read_ocr(struct rt_mmcsd_host *host, rt_int32_t high_capacity, rt_uint32_t *ocr)
  91. {
  92. struct rt_mmcsd_cmd cmd;
  93. rt_int32_t err;
  94. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  95. cmd.cmd_code = SPI_READ_OCR;
  96. cmd.arg = high_capacity ? (1 << 30) : 0;
  97. cmd.flags = RESP_SPI_R3;
  98. err = mmcsd_send_cmd(host, &cmd, 0);
  99. *ocr = cmd.resp[1];
  100. return err;
  101. }
  102. rt_int32_t mmcsd_all_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  103. {
  104. rt_int32_t err;
  105. struct rt_mmcsd_cmd cmd;
  106. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  107. cmd.cmd_code = ALL_SEND_CID;
  108. cmd.arg = 0;
  109. cmd.flags = RESP_R2 | CMD_BCR;
  110. err = mmcsd_send_cmd(host, &cmd, 3);
  111. if (err)
  112. return err;
  113. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  114. return 0;
  115. }
  116. rt_int32_t mmcsd_get_cid(struct rt_mmcsd_host *host, rt_uint32_t *cid)
  117. {
  118. rt_int32_t err, i;
  119. struct rt_mmcsd_req req;
  120. struct rt_mmcsd_cmd cmd;
  121. struct rt_mmcsd_data data;
  122. rt_uint32_t *buf = RT_NULL;
  123. if (!controller_is_spi(host))
  124. {
  125. if (!host->card)
  126. return -RT_ERROR;
  127. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  128. cmd.cmd_code = SEND_CID;
  129. cmd.arg = host->card->rca << 16;
  130. cmd.flags = RESP_R2 | CMD_AC;
  131. err = mmcsd_send_cmd(host, &cmd, 3);
  132. if (err)
  133. return err;
  134. rt_memcpy(cid, cmd.resp, sizeof(rt_uint32_t) * 4);
  135. return 0;
  136. }
  137. buf = (rt_uint32_t *)rt_malloc(16);
  138. if (!buf)
  139. {
  140. rt_kprintf("allocate memory failed\n");
  141. return -RT_ENOMEM;
  142. }
  143. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  144. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  145. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  146. req.cmd = &cmd;
  147. req.data = &data;
  148. cmd.cmd_code = SEND_CID;
  149. cmd.arg = 0;
  150. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  151. * rely on callers to never use this with "native" calls for reading
  152. * CSD or CID. Native versions of those commands use the R2 type,
  153. * not R1 plus a data block.
  154. */
  155. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  156. data.blksize = 16;
  157. data.blks = 1;
  158. data.flags = DATA_DIR_READ;
  159. data.buf = buf;
  160. /*
  161. * The spec states that CSR and CID accesses have a timeout
  162. * of 64 clock cycles.
  163. */
  164. data.timeout_ns = 0;
  165. data.timeout_clks = 64;
  166. mmcsd_send_request(host, &req);
  167. if (cmd.err || data.err)
  168. {
  169. rt_free(buf);
  170. return -RT_ERROR;
  171. }
  172. for (i = 0;i < 4;i++)
  173. cid[i] = buf[i];
  174. rt_free(buf);
  175. return 0;
  176. }
  177. rt_int32_t mmcsd_get_csd(struct rt_mmcsd_card *card, rt_uint32_t *csd)
  178. {
  179. rt_int32_t err, i;
  180. struct rt_mmcsd_req req;
  181. struct rt_mmcsd_cmd cmd;
  182. struct rt_mmcsd_data data;
  183. rt_uint32_t *buf = RT_NULL;
  184. if (!controller_is_spi(card->host))
  185. {
  186. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  187. cmd.cmd_code = SEND_CSD;
  188. cmd.arg = card->rca << 16;
  189. cmd.flags = RESP_R2 | CMD_AC;
  190. err = mmcsd_send_cmd(card->host, &cmd, 3);
  191. if (err)
  192. return err;
  193. rt_memcpy(csd, cmd.resp, sizeof(rt_uint32_t) * 4);
  194. return 0;
  195. }
  196. buf = (rt_uint32_t*)rt_malloc(16);
  197. if (!buf)
  198. {
  199. rt_kprintf("allocate memory failed\n");
  200. return -RT_ENOMEM;
  201. }
  202. rt_memset(&req, 0, sizeof(struct rt_mmcsd_req));
  203. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  204. rt_memset(&data, 0, sizeof(struct rt_mmcsd_data));
  205. req.cmd = &cmd;
  206. req.data = &data;
  207. cmd.cmd_code = SEND_CSD;
  208. cmd.arg = 0;
  209. /* NOTE HACK: the RESP_SPI_R1 is always correct here, but we
  210. * rely on callers to never use this with "native" calls for reading
  211. * CSD or CID. Native versions of those commands use the R2 type,
  212. * not R1 plus a data block.
  213. */
  214. cmd.flags = RESP_SPI_R1 | RESP_R1 | CMD_ADTC;
  215. data.blksize = 16;
  216. data.blks = 1;
  217. data.flags = DATA_DIR_READ;
  218. data.buf = buf;
  219. /*
  220. * The spec states that CSR and CID accesses have a timeout
  221. * of 64 clock cycles.
  222. */
  223. data.timeout_ns = 0;
  224. data.timeout_clks = 64;
  225. mmcsd_send_request(card->host, &req);
  226. if (cmd.err || data.err)
  227. {
  228. rt_free(buf);
  229. return -RT_ERROR;
  230. }
  231. for (i = 0;i < 4;i++)
  232. csd[i] = buf[i];
  233. rt_free(buf);
  234. return 0;
  235. }
  236. static rt_int32_t _mmcsd_select_card(struct rt_mmcsd_host *host, struct rt_mmcsd_card *card)
  237. {
  238. rt_int32_t err;
  239. struct rt_mmcsd_cmd cmd;
  240. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  241. cmd.cmd_code = SELECT_CARD;
  242. if (card)
  243. {
  244. cmd.arg = card->rca << 16;
  245. cmd.flags = RESP_R1 | CMD_AC;
  246. }
  247. else
  248. {
  249. cmd.arg = 0;
  250. cmd.flags = RESP_NONE | CMD_AC;
  251. }
  252. err = mmcsd_send_cmd(host, &cmd, 3);
  253. if (err)
  254. return err;
  255. return 0;
  256. }
  257. rt_int32_t mmcsd_select_card(struct rt_mmcsd_card *card)
  258. {
  259. return _mmcsd_select_card(card->host, card);
  260. }
  261. rt_int32_t mmcsd_deselect_cards(struct rt_mmcsd_card *card)
  262. {
  263. return _mmcsd_select_card(card->host, RT_NULL);
  264. }
  265. rt_int32_t mmcsd_spi_use_crc(struct rt_mmcsd_host *host, rt_int32_t use_crc)
  266. {
  267. struct rt_mmcsd_cmd cmd;
  268. rt_int32_t err;
  269. rt_memset(&cmd, 0, sizeof(struct rt_mmcsd_cmd));
  270. cmd.cmd_code = SPI_CRC_ON_OFF;
  271. cmd.flags = RESP_SPI_R1;
  272. cmd.arg = use_crc;
  273. err = mmcsd_send_cmd(host, &cmd, 0);
  274. if (!err)
  275. host->spi_use_crc = use_crc;
  276. return err;
  277. }
  278. rt_inline void mmcsd_set_iocfg(struct rt_mmcsd_host *host)
  279. {
  280. struct rt_mmcsd_io_cfg *io_cfg = &host->io_cfg;
  281. mmcsd_dbg("clock %uHz busmode %u powermode %u cs %u Vdd %u "
  282. "width %u \n",
  283. io_cfg->clock, io_cfg->bus_mode,
  284. io_cfg->power_mode, io_cfg->chip_select, io_cfg->vdd,
  285. io_cfg->bus_width);
  286. host->ops->set_iocfg(host, io_cfg);
  287. }
  288. /*
  289. * Control chip select pin on a host.
  290. */
  291. void mmcsd_set_chip_select(struct rt_mmcsd_host *host, rt_int32_t mode)
  292. {
  293. host->io_cfg.chip_select = mode;
  294. mmcsd_set_iocfg(host);
  295. }
  296. /*
  297. * Sets the host clock to the highest possible frequency that
  298. * is below "hz".
  299. */
  300. void mmcsd_set_clock(struct rt_mmcsd_host *host, rt_uint32_t clk)
  301. {
  302. if (clk < host->freq_min)
  303. {
  304. rt_kprintf("clock too low\n");
  305. }
  306. host->io_cfg.clock = clk;
  307. mmcsd_set_iocfg(host);
  308. }
  309. /*
  310. * Change the bus mode (open drain/push-pull) of a host.
  311. */
  312. void mmcsd_set_bus_mode(struct rt_mmcsd_host *host, rt_uint32_t mode)
  313. {
  314. host->io_cfg.bus_mode = mode;
  315. mmcsd_set_iocfg(host);
  316. }
  317. /*
  318. * Change data bus width of a host.
  319. */
  320. void mmcsd_set_bus_width(struct rt_mmcsd_host *host, rt_uint32_t width)
  321. {
  322. host->io_cfg.bus_width = width;
  323. mmcsd_set_iocfg(host);
  324. }
  325. void mmcsd_set_data_timeout(struct rt_mmcsd_data *data, const struct rt_mmcsd_card *card)
  326. {
  327. rt_uint32_t mult;
  328. if (card->card_type == CARD_TYPE_SDIO)
  329. {
  330. data->timeout_ns = 1000000000; /* SDIO card 1s */
  331. data->timeout_clks = 0;
  332. return;
  333. }
  334. /*
  335. * SD cards use a 100 multiplier rather than 10
  336. */
  337. mult = (card->card_type == CARD_TYPE_SD) ? 100 : 10;
  338. /*
  339. * Scale up the multiplier (and therefore the timeout) by
  340. * the r2w factor for writes.
  341. */
  342. if (data->flags & DATA_DIR_WRITE)
  343. mult <<= card->csd.r2w_factor;
  344. data->timeout_ns = card->tacc_ns * mult;
  345. data->timeout_clks = card->tacc_clks * mult;
  346. /*
  347. * SD cards also have an upper limit on the timeout.
  348. */
  349. if (card->card_type == CARD_TYPE_SD)
  350. {
  351. rt_uint32_t timeout_us, limit_us;
  352. timeout_us = data->timeout_ns / 1000;
  353. timeout_us += data->timeout_clks * 1000 /
  354. (card->host->io_cfg.clock / 1000);
  355. if (data->flags & DATA_DIR_WRITE)
  356. /*
  357. * The limit is really 250 ms, but that is
  358. * insufficient for some crappy cards.
  359. */
  360. limit_us = 300000;
  361. else
  362. limit_us = 100000;
  363. /*
  364. * SDHC cards always use these fixed values.
  365. */
  366. if (timeout_us > limit_us || card->flags & CARD_FLAG_SDHC)
  367. {
  368. data->timeout_ns = limit_us * 1000; /* SDHC card fixed 250ms */
  369. data->timeout_clks = 0;
  370. }
  371. }
  372. if (controller_is_spi(card->host))
  373. {
  374. if (data->flags & DATA_DIR_WRITE)
  375. {
  376. if (data->timeout_ns < 1000000000)
  377. data->timeout_ns = 1000000000; /* 1s */
  378. }
  379. else
  380. {
  381. if (data->timeout_ns < 100000000)
  382. data->timeout_ns = 100000000; /* 100ms */
  383. }
  384. }
  385. }
  386. /*
  387. * Mask off any voltages we don't support and select
  388. * the lowest voltage
  389. */
  390. rt_uint32_t mmcsd_select_voltage(struct rt_mmcsd_host *host, rt_uint32_t ocr)
  391. {
  392. int bit;
  393. ocr &= host->valid_ocr;
  394. bit = ffs(ocr);
  395. if (bit)
  396. {
  397. bit -= 1;
  398. ocr &= 3 << bit;
  399. host->io_cfg.vdd = bit;
  400. mmcsd_set_iocfg(host);
  401. }
  402. else
  403. {
  404. rt_kprintf("host doesn't support card's voltages\n");
  405. ocr = 0;
  406. }
  407. return ocr;
  408. }
  409. static void mmcsd_power_up(struct rt_mmcsd_host *host)
  410. {
  411. int bit = fls(host->valid_ocr) - 1;
  412. host->io_cfg.vdd = bit;
  413. if (controller_is_spi(host))
  414. {
  415. host->io_cfg.chip_select = MMCSD_CS_HIGH;
  416. host->io_cfg.bus_mode = MMCSD_BUSMODE_PUSHPULL;
  417. }
  418. else
  419. {
  420. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  421. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  422. }
  423. host->io_cfg.power_mode = MMCSD_POWER_UP;
  424. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  425. mmcsd_set_iocfg(host);
  426. /*
  427. * This delay should be sufficient to allow the power supply
  428. * to reach the minimum voltage.
  429. */
  430. mmcsd_delay_ms(10);
  431. host->io_cfg.clock = host->freq_min;
  432. host->io_cfg.power_mode = MMCSD_POWER_ON;
  433. mmcsd_set_iocfg(host);
  434. /*
  435. * This delay must be at least 74 clock sizes, or 1 ms, or the
  436. * time required to reach a stable voltage.
  437. */
  438. mmcsd_delay_ms(10);
  439. }
  440. static void mmcsd_power_off(struct rt_mmcsd_host *host)
  441. {
  442. host->io_cfg.clock = 0;
  443. host->io_cfg.vdd = 0;
  444. if (!controller_is_spi(host))
  445. {
  446. host->io_cfg.bus_mode = MMCSD_BUSMODE_OPENDRAIN;
  447. host->io_cfg.chip_select = MMCSD_CS_IGNORE;
  448. }
  449. host->io_cfg.power_mode = MMCSD_POWER_OFF;
  450. host->io_cfg.bus_width = MMCSD_BUS_WIDTH_1;
  451. mmcsd_set_iocfg(host);
  452. }
  453. void mmcsd_change(struct rt_mmcsd_host *host)
  454. {
  455. rt_mb_send(&mmcsd_detect_mb, (rt_uint32_t)host);
  456. }
  457. void mmcsd_detect(void *param)
  458. {
  459. struct rt_mmcsd_host *host;
  460. rt_uint32_t ocr;
  461. rt_int32_t err;
  462. while (1)
  463. {
  464. if (rt_mb_recv(&mmcsd_detect_mb, (rt_uint32_t*)&host, RT_WAITING_FOREVER) == RT_EOK)
  465. {
  466. if (host->card == RT_NULL)
  467. {
  468. mmcsd_host_lock(host);
  469. mmcsd_power_up(host);
  470. mmcsd_go_idle(host);
  471. mmcsd_send_if_cond(host, host->valid_ocr);
  472. err = sdio_io_send_op_cond(host, 0, &ocr);
  473. if (!err) {
  474. if (init_sdio(host, ocr))
  475. mmcsd_power_off(host);
  476. mmcsd_host_unlock(host);
  477. continue;
  478. }
  479. /*
  480. * detect SD card
  481. */
  482. err = mmcsd_send_app_op_cond(host, 0, &ocr);
  483. if (!err)
  484. {
  485. if (init_sd(host, ocr))
  486. mmcsd_power_off(host);
  487. mmcsd_host_unlock(host);
  488. continue;
  489. }
  490. mmcsd_host_unlock(host);
  491. }
  492. }
  493. }
  494. }
  495. struct rt_mmcsd_host *mmcsd_alloc_host(void)
  496. {
  497. struct rt_mmcsd_host *host;
  498. host = rt_malloc(sizeof(struct rt_mmcsd_host));
  499. if (!host)
  500. {
  501. rt_kprintf("alloc host failed\n");
  502. return RT_NULL;
  503. }
  504. rt_memset(host, 0, sizeof(struct rt_mmcsd_host));
  505. host->max_seg_size = 65535;
  506. host->max_dma_segs = 1;
  507. host->max_blk_size = 512;
  508. host->max_blk_count = 4096;
  509. rt_sem_init(&host->bus_lock, "sd_bus_lock", 1, RT_IPC_FLAG_FIFO);
  510. rt_sem_init(&host->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO);
  511. return host;
  512. }
  513. void mmcsd_free_host(struct rt_mmcsd_host *host)
  514. {
  515. rt_sem_detach(&host->bus_lock);
  516. rt_sem_detach(&host->sem_ack);
  517. rt_free(host);
  518. }
  519. void rt_mmcsd_core_init(void)
  520. {
  521. rt_err_t ret;
  522. /* init detect sd cart thread */
  523. /* init mailbox and create detect sd card thread */
  524. ret = rt_mb_init(&mmcsd_detect_mb, "mmcsdmb",
  525. &mmcsd_detect_mb_pool[0], sizeof(mmcsd_detect_mb_pool),
  526. RT_IPC_FLAG_FIFO);
  527. RT_ASSERT(ret == RT_EOK);
  528. ret = rt_thread_init(&mmcsd_detect_thread, "mmcsd_detect", mmcsd_detect, RT_NULL,
  529. &mmcsd_stack[0], RT_MMCSD_STACK_SIZE, RT_MMCSD_THREAD_PREORITY, 20);
  530. if (ret == RT_EOK)
  531. {
  532. rt_thread_startup(&mmcsd_detect_thread);
  533. }
  534. rt_sdio_init();
  535. }