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drv_rtc.c 4.9 KB

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  1. /*
  2. * Copyright (c) 2020-2021, Bluetrum Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-01-28 greedyhao first version
  9. */
  10. #include "board.h"
  11. #include <time.h>
  12. #include <sys/time.h>
  13. #ifdef BSP_USING_ONCHIP_RTC
  14. //#define DRV_DEBUG
  15. #define LOG_TAG "drv.rtc"
  16. #include <drv_log.h>
  17. static struct rt_device rtc;
  18. /************** HAL Start *******************/
  19. #define IRTC_ENTER_CRITICAL() uint32_t cpu_ie = PICCON & BIT(0); PICCONCLR = BIT(0);
  20. #define IRTC_EXIT_CRITICAL() PICCON |= cpu_ie
  21. uint8_t get_weekday(struct tm *const _tm)
  22. {
  23. uint8_t weekday;
  24. time_t secs = timegm(_tm);
  25. weekday = (secs / 86400 + 4) % 7;
  26. return weekday;
  27. }
  28. void irtc_write(uint32_t cmd)
  29. {
  30. RTCDAT = cmd;
  31. while (RTCCON & RTC_CON_TRANS_DONE);
  32. }
  33. uint8_t irtc_read(void)
  34. {
  35. RTCDAT = 0x00;
  36. while (RTCCON & RTC_CON_TRANS_DONE);
  37. return (uint8_t)RTCDAT;
  38. }
  39. void irtc_time_write(uint32_t cmd, uint32_t dat)
  40. {
  41. IRTC_ENTER_CRITICAL();
  42. RTCCON |= RTC_CON_CHIP_SELECT;
  43. irtc_write(cmd | RTC_WR);
  44. irtc_write((uint8_t)(dat >> 24));
  45. irtc_write((uint8_t)(dat >> 16));
  46. irtc_write((uint8_t)(dat >> 8));
  47. irtc_write((uint8_t)(dat >> 0));
  48. RTCCON &= ~RTC_CON_CHIP_SELECT;
  49. IRTC_EXIT_CRITICAL();
  50. }
  51. uint32_t irtc_time_read(uint32_t cmd)
  52. {
  53. uint32_t rd_val;
  54. IRTC_ENTER_CRITICAL();
  55. RTCCON |= RTC_CON_CHIP_SELECT;
  56. irtc_write(cmd | RTC_RD);
  57. *((uint8_t *)&rd_val + 3) = irtc_read();
  58. *((uint8_t *)&rd_val + 2) = irtc_read();
  59. *((uint8_t *)&rd_val + 1) = irtc_read();
  60. *((uint8_t *)&rd_val + 0) = irtc_read();
  61. RTCCON &= ~RTC_CON_CHIP_SELECT;
  62. IRTC_EXIT_CRITICAL();
  63. return rd_val;
  64. }
  65. void irtc_sfr_write(uint32_t cmd, uint8_t dat)
  66. {
  67. IRTC_ENTER_CRITICAL();
  68. RTCCON |= RTC_CON_CHIP_SELECT;
  69. irtc_write(cmd | RTC_WR);
  70. irtc_write(dat);
  71. RTCCON &= ~RTC_CON_CHIP_SELECT;
  72. IRTC_EXIT_CRITICAL();
  73. }
  74. uint8_t irtc_sfr_read(uint32_t cmd)
  75. {
  76. uint8_t rd_val;
  77. IRTC_ENTER_CRITICAL();
  78. RTCCON |= RTC_CON_CHIP_SELECT;
  79. irtc_write(cmd | RTC_RD);
  80. rd_val = irtc_read();
  81. RTCCON &= ~RTC_CON_CHIP_SELECT;
  82. IRTC_EXIT_CRITICAL();
  83. }
  84. void hal_rtc_init(void)
  85. {
  86. time_t sec = 0;
  87. struct tm tm_new = {0};
  88. uint8_t temp = irtc_sfr_read(RTCCON0_CMD);
  89. temp &= ~RTC_CON0_XOSC32K_ENABLE;
  90. temp |= RTC_CON0_EXTERNAL_32K;
  91. irtc_sfr_write(RTCCON0_CMD, temp);
  92. temp = irtc_sfr_read(RTCCON2_CMD);
  93. irtc_sfr_write(RTCCON2_CMD, temp | RTC_CON2_32K_SELECT);
  94. temp = irtc_sfr_read(RTCCON0_CMD);
  95. if (temp & BIT(7)) {
  96. temp &= ~BIT(7);
  97. irtc_sfr_write(RTCCON0_CMD, temp); /* First power on */
  98. }
  99. tm_new.tm_mday = 29;
  100. tm_new.tm_mon = 1 - 1;
  101. tm_new.tm_year = 2021 - 1900;
  102. sec = timegm(&tm_new);
  103. irtc_time_write(RTCCNT_CMD, sec);
  104. }
  105. /************** HAL End *******************/
  106. static time_t get_rtc_timestamp(void)
  107. {
  108. time_t sec = 0;
  109. sec = irtc_time_read(RTCCNT_CMD);
  110. LOG_D("get rtc time.");
  111. return sec;
  112. }
  113. static rt_err_t set_rtc_time_stamp(time_t time_stamp)
  114. {
  115. irtc_time_write(RTCCNT_CMD, time_stamp);
  116. return RT_EOK;
  117. }
  118. static void rt_rtc_init(void)
  119. {
  120. hal_rtc_init();
  121. }
  122. static rt_err_t rt_rtc_control(rt_device_t dev, int cmd, void *args)
  123. {
  124. rt_err_t result = RT_EOK;
  125. RT_ASSERT(dev != RT_NULL);
  126. switch (cmd)
  127. {
  128. case RT_DEVICE_CTRL_RTC_GET_TIME:
  129. *(rt_uint32_t *)args = get_rtc_timestamp();
  130. LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args);
  131. break;
  132. case RT_DEVICE_CTRL_RTC_SET_TIME:
  133. if (set_rtc_time_stamp(*(rt_uint32_t *)args))
  134. {
  135. result = -RT_ERROR;
  136. }
  137. LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args);
  138. break;
  139. }
  140. return result;
  141. }
  142. #ifdef RT_USING_DEVICE_OPS
  143. const static struct rt_device_ops rtc_ops =
  144. {
  145. RT_NULL,
  146. RT_NULL,
  147. RT_NULL,
  148. RT_NULL,
  149. RT_NULL,
  150. rt_rtc_control
  151. };
  152. #endif
  153. static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag)
  154. {
  155. RT_ASSERT(device != RT_NULL);
  156. rt_rtc_init();
  157. #ifdef RT_USING_DEVICE_OPS
  158. device->ops = &rtc_ops;
  159. #else
  160. device->init = RT_NULL;
  161. device->open = RT_NULL;
  162. device->close = RT_NULL;
  163. device->read = RT_NULL;
  164. device->write = RT_NULL;
  165. device->control = rt_rtc_control;
  166. #endif
  167. device->type = RT_Device_Class_RTC;
  168. device->rx_indicate = RT_NULL;
  169. device->tx_complete = RT_NULL;
  170. device->user_data = RT_NULL;
  171. /* register a character device */
  172. return rt_device_register(device, name, flag);
  173. }
  174. int rt_hw_rtc_init(void)
  175. {
  176. rt_err_t result;
  177. result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR);
  178. if (result != RT_EOK)
  179. {
  180. LOG_E("rtc register err code: %d", result);
  181. return result;
  182. }
  183. LOG_D("rtc init success");
  184. return RT_EOK;
  185. }
  186. INIT_DEVICE_EXPORT(rt_hw_rtc_init);
  187. #endif /* BSP_USING_ONCHIP_RTC */