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GD32F4xx_standard_peripheral
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Include
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gd32f4xx_sdio.h

gd32f4xx_sdio.h 25 KB
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  1. /*!
    2. 

  2.     \file  gd32f4xx_sdio.h
    3. 

  3.     \brief definitions for the SDIO
    4. 

  4. */
    5. 

  5. 

  6. /*
    7. 

  7.     Copyright (C) 2016 GigaDevice
    8. 

  8. 

  9.     2016-08-15, V1.0.0, firmware for GD32F4xx
    10. 

  10. */
    11. 

  11. 

  12. #ifndef GD32F4XX_SDIO_H
    13. 

  13. #define GD32F4XX_SDIO_H
    14. 

  14. 

  15. #include "gd32f4xx.h"
    16. 

  16. 

  17. /* SDIO definitions */
    18. 

  18. #define SDIO                            SDIO_BASE
    19. 

  19. 

  20. /* registers definitions */
    21. 

  21. #define SDIO_PWRCTL                     REG32(SDIO + 0x00U)    /*!< SDIO power control register */
    22. 

  22. #define SDIO_CLKCTL                     REG32(SDIO + 0x04U)    /*!< SDIO clock control register */
    23. 

  23. #define SDIO_CMDAGMT                    REG32(SDIO + 0x08U)    /*!< SDIO command argument register */
    24. 

  24. #define SDIO_CMDCTL                     REG32(SDIO + 0x0CU)    /*!< SDIO command control register */
    25. 

  25. #define SDIO_RSPCMDIDX                  REG32(SDIO + 0x10U)    /*!< SDIO command index response register */
    26. 

  26. #define SDIO_RESP0                      REG32(SDIO + 0x14U)    /*!< SDIO response register 0 */
    27. 

  27. #define SDIO_RESP1                      REG32(SDIO + 0x18U)    /*!< SDIO response register 1 */
    28. 

  28. #define SDIO_RESP2                      REG32(SDIO + 0x1CU)    /*!< SDIO response register 2 */
    29. 

  29. #define SDIO_RESP3                      REG32(SDIO + 0x20U)    /*!< SDIO response register 3 */
    30. 

  30. #define SDIO_DATATO                     REG32(SDIO + 0x24U)    /*!< SDIO data timeout register */
    31. 

  31. #define SDIO_DATALEN                    REG32(SDIO + 0x28U)    /*!< SDIO data length register */
    32. 

  32. #define SDIO_DATACTL                    REG32(SDIO + 0x2CU)    /*!< SDIO data control register */
    33. 

  33. #define SDIO_DATACNT                    REG32(SDIO + 0x30U)    /*!< SDIO data counter register */
    34. 

  34. #define SDIO_STAT                       REG32(SDIO + 0x34U)    /*!< SDIO status register */
    35. 

  35. #define SDIO_INTC                       REG32(SDIO + 0x38U)    /*!< SDIO interrupt clear register */
    36. 

  36. #define SDIO_INTEN                      REG32(SDIO + 0x3CU)    /*!< SDIO interrupt enable register */
    37. 

  37. #define SDIO_FIFOCNT                    REG32(SDIO + 0x48U)    /*!< SDIO FIFO counter register */
    38. 

  38. #define SDIO_FIFO                       REG32(SDIO + 0x80U)    /*!< SDIO FIFO data register */
    39. 

  39. 

  40. /* bits definitions */
    41. 

  41. /* SDIO_PWRCTL */
    42. 

  42. #define SDIO_PWRCTL_PWRCTL              BITS(0,1)              /*!< SDIO power control bits */
    43. 

  43. 

  44. /* SDIO_CLKCTL */
    45. 

  45. #define SDIO_CLKCTL_DIV                 BITS(0,7)              /*!< clock division */
    46. 

  46. #define SDIO_CLKCTL_CLKEN               BIT(8)                 /*!< SDIO_CLK clock output enable bit */
    47. 

  47. #define SDIO_CLKCTL_CLKPWRSAV           BIT(9)                 /*!< SDIO_CLK clock dynamic switch on/off for power saving */
    48. 

  48. #define SDIO_CLKCTL_CLKBYP              BIT(10)                /*!< clock bypass enable bit */
    49. 

  49. #define SDIO_CLKCTL_BUSMODE             BITS(11,12)            /*!< SDIO card bus mode control bit */
    50. 

  50. #define SDIO_CLKCTL_CLKEDGE             BIT(13)                /*!< SDIO_CLK clock edge selection bit */
    51. 

  51. #define SDIO_CLKCTL_HWCLKEN             BIT(14)                /*!< hardware clock control enable bit */
    52. 

  52. #define SDIO_CLKCTL_DIV8                BIT(31)                /*!< MSB of clock division */
    53. 

  53. 

  54. /* SDIO_CMDAGMT */
    55. 

  55. #define SDIO_CMDAGMT_CMDAGMT            BITS(0,31)             /*!< SDIO card command argument */
    56. 

  56. 

  57. /* SDIO_CMDCTL */
    58. 

  58. #define SDIO_CMDCTL_CMDIDX              BITS(0,5)              /*!< command index */
    59. 

  59. #define SDIO_CMDCTL_CMDRESP             BITS(6,7)              /*!< command response type bits */
    60. 

  60. #define SDIO_CMDCTL_INTWAIT             BIT(8)                 /*!< interrupt wait instead of timeout */
    61. 

  61. #define SDIO_CMDCTL_WAITDEND            BIT(9)                 /*!< wait for ends of data transfer */
    62. 

  62. #define SDIO_CMDCTL_CSMEN               BIT(10)                /*!< command state machine(CSM) enable bit */
    63. 

  63. #define SDIO_CMDCTL_SUSPEND             BIT(11)                /*!< SD I/O suspend command(SD I/O only) */
    64. 

  64. #define SDIO_CMDCTL_ENCMDC              BIT(12)                /*!< CMD completion signal enabled (CE-ATA only) */
    65. 

  65. #define SDIO_CMDCTL_NINTEN              BIT(13)                /*!< no CE-ATA interrupt (CE-ATA only) */
    66. 

  66. #define SDIO_CMDCTL_ATAEN               BIT(14)                /*!< CE-ATA command enable(CE-ATA only) */
    67. 

  67. 

  68. /* SDIO_DATATO */
    69. 

  69. #define SDIO_DATATO_DATATO              BITS(0,31)             /*!< data timeout period */
    70. 

  70. 

  71. /* SDIO_DATALEN */
    72. 

  72. #define SDIO_DATALEN_DATALEN            BITS(0,24)             /*!< data transfer length */
    73. 

  73. 

  74. /* SDIO_DATACTL */
    75. 

  75. #define SDIO_DATACTL_DATAEN             BIT(0)                 /*!< data transfer enabled bit */
    76. 

  76. #define SDIO_DATACTL_DATADIR            BIT(1)                 /*!< data transfer direction */
    77. 

  77. #define SDIO_DATACTL_TRANSMOD           BIT(2)                 /*!< data transfer mode */
    78. 

  78. #define SDIO_DATACTL_DMAEN              BIT(3)                 /*!< DMA enable bit */
    79. 

  79. #define SDIO_DATACTL_BLKSZ              BITS(4,7)              /*!< data block size */
    80. 

  80. #define SDIO_DATACTL_RWEN               BIT(8)                 /*!< read wait mode enabled(SD I/O only) */
    81. 

  81. #define SDIO_DATACTL_RWSTOP             BIT(9)                 /*!< read wait stop(SD I/O only) */
    82. 

  82. #define SDIO_DATACTL_RWTYPE             BIT(10)                /*!< read wait type(SD I/O only) */
    83. 

  83. #define SDIO_DATACTL_IOEN               BIT(11)                /*!< SD I/O specific function enable(SD I/O only) */
    84. 

  84. 

  85. /* SDIO_STAT */
    86. 

  86. #define SDIO_STAT_CCRCERR               BIT(0)                 /*!< command response received (CRC check failed) */
    87. 

  87. #define SDIO_STAT_DTCRCERR              BIT(1)                 /*!< data block sent/received (CRC check failed) */
    88. 

  88. #define SDIO_STAT_CMDTMOUT              BIT(2)                 /*!< command response timeout */
    89. 

  89. #define SDIO_STAT_DTTMOUT               BIT(3)                 /*!< data timeout */
    90. 

  90. #define SDIO_STAT_TXURE                 BIT(4)                 /*!< transmit FIFO underrun error occurs */
    91. 

  91. #define SDIO_STAT_RXORE                 BIT(5)                 /*!< received FIFO overrun error occurs */
    92. 

  92. #define SDIO_STAT_CMDRECV               BIT(6)                 /*!< command response received (CRC check passed) */
    93. 

  93. #define SDIO_STAT_CMDSEND               BIT(7)                 /*!< command sent (no response required) */
    94. 

  94. #define SDIO_STAT_DTEND                 BIT(8)                 /*!< data end (data counter, SDIO_DATACNT, is zero) */
    95. 

  95. #define SDIO_STAT_STBITE                BIT(9)                 /*!< start bit error in the bus */
    96. 

  96. #define SDIO_STAT_DTBLKEND              BIT(10)                /*!< data block sent/received (CRC check passed) */
    97. 

  97. #define SDIO_STAT_CMDRUN                BIT(11)                /*!< command transmission in progress */
    98. 

  98. #define SDIO_STAT_TXRUN                 BIT(12)                /*!< data transmission in progress */
    99. 

  99. #define SDIO_STAT_RXRUN                 BIT(13)                /*!< data reception in progress */
    100. 

  100. #define SDIO_STAT_TFH                   BIT(14)                /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
    101. 

  101. #define SDIO_STAT_RFH                   BIT(15)                /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
    102. 

  102. #define SDIO_STAT_TFF                   BIT(16)                /*!< transmit FIFO is full */
    103. 

  103. #define SDIO_STAT_RFF                   BIT(17)                /*!< receive FIFO is full */
    104. 

  104. #define SDIO_STAT_TFE                   BIT(18)                /*!< transmit FIFO is empty */
    105. 

  105. #define SDIO_STAT_RFE                   BIT(19)                /*!< receive FIFO is empty */
    106. 

  106. #define SDIO_STAT_TXDTVAL               BIT(20)                /*!< data is valid in transmit FIFO */
    107. 

  107. #define SDIO_STAT_RXDTVAL               BIT(21)                /*!< data is valid in receive FIFO */
    108. 

  108. #define SDIO_STAT_SDIOINT               BIT(22)                /*!< SD I/O interrupt received */
    109. 

  109. #define SDIO_STAT_ATAEND                BIT(23)                /*!< CE-ATA command completion signal received (only for CMD61) */
    110. 

  110. 

  111. /* SDIO_INTC */
    112. 

  112. #define SDIO_INTC_CCRCERRC              BIT(0)                 /*!< CCRCERR flag clear bit */
    113. 

  113. #define SDIO_INTC_DTCRCERRC             BIT(1)                 /*!< DTCRCERR flag clear bit */
    114. 

  114. #define SDIO_INTC_CMDTMOUTC             BIT(2)                 /*!< CMDTMOUT flag clear bit */
    115. 

  115. #define SDIO_INTC_DTTMOUTC              BIT(3)                 /*!< DTTMOUT flag clear bit */
    116. 

  116. #define SDIO_INTC_TXUREC                BIT(4)                 /*!< TXURE flag clear bit */
    117. 

  117. #define SDIO_INTC_RXOREC                BIT(5)                 /*!< RXORE flag clear bit */
    118. 

  118. #define SDIO_INTC_CMDRECVC              BIT(6)                 /*!< CMDRECV flag clear bit */
    119. 

  119. #define SDIO_INTC_CMDSENDC              BIT(7)                 /*!< CMDSEND flag clear bit */
    120. 

  120. #define SDIO_INTC_DTENDC                BIT(8)                 /*!< DTEND flag clear bit */
    121. 

  121. #define SDIO_INTC_STBITEC               BIT(9)                 /*!< STBITE flag clear bit */
    122. 

  122. #define SDIO_INTC_DTBLKENDC             BIT(10)                /*!< DTBLKEND flag clear bit */
    123. 

  123. #define SDIO_INTC_SDIOINTC              BIT(22)                /*!< SDIOINT flag clear bit */
    124. 

  124. #define SDIO_INTC_ATAENDC               BIT(23)                /*!< ATAEND flag clear bit */
    125. 

  125. 

  126. /* SDIO_INTEN */
    127. 

  127. #define SDIO_INTEN_CCRCERRIE            BIT(0)                 /*!< command response CRC fail interrupt enable */
    128. 

  128. #define SDIO_INTEN_DTCRCERRIE           BIT(1)                 /*!< data CRC fail interrupt enable */
    129. 

  129. #define SDIO_INTEN_CMDTMOUTIE           BIT(2)                 /*!< command response timeout interrupt enable */
    130. 

  130. #define SDIO_INTEN_DTTMOUTIE            BIT(3)                 /*!< data timeout interrupt enable */
    131. 

  131. #define SDIO_INTEN_TXUREIE              BIT(4)                 /*!< transmit FIFO underrun error interrupt enable */
    132. 

  132. #define SDIO_INTEN_RXOREIE              BIT(5)                 /*!< received FIFO overrun error interrupt enable */
    133. 

  133. #define SDIO_INTEN_CMDRECVIE            BIT(6)                 /*!< command response received interrupt enable */
    134. 

  134. #define SDIO_INTEN_CMDSENDIE            BIT(7)                 /*!< command sent interrupt enable */
    135. 

  135. #define SDIO_INTEN_DTENDIE              BIT(8)                 /*!< data end interrupt enable */
    136. 

  136. #define SDIO_INTEN_STBITEIE             BIT(9)                 /*!< start bit error interrupt enable */
    137. 

  137. #define SDIO_INTEN_DTBLKENDIE           BIT(10)                /*!< data block end interrupt enable */
    138. 

  138. #define SDIO_INTEN_CMDRUNIE             BIT(11)                /*!< command transmission interrupt enable */
    139. 

  139. #define SDIO_INTEN_TXRUNIE              BIT(12)                /*!< data transmission interrupt enable */
    140. 

  140. #define SDIO_INTEN_RXRUNIE              BIT(13)                /*!< data reception interrupt enable */
    141. 

  141. #define SDIO_INTEN_TFHIE                BIT(14)                /*!< transmit FIFO half empty interrupt enable */
    142. 

  142. #define SDIO_INTEN_RFHIE                BIT(15)                /*!< receive FIFO half full interrupt enable */
    143. 

  143. #define SDIO_INTEN_TFFIE                BIT(16)                /*!< transmit FIFO full interrupt enable */
    144. 

  144. #define SDIO_INTEN_RFFIE                BIT(17)                /*!< receive FIFO full interrupt enable */
    145. 

  145. #define SDIO_INTEN_TFEIE                BIT(18)                /*!< transmit FIFO empty interrupt enable */
    146. 

  146. #define SDIO_INTEN_RFEIE                BIT(19)                /*!< receive FIFO empty interrupt enable */
    147. 

  147. #define SDIO_INTEN_TXDTVALIE            BIT(20)                /*!< data valid in transmit FIFO interrupt enable */
    148. 

  148. #define SDIO_INTEN_RXDTVALIE            BIT(21)                /*!< data valid in receive FIFO interrupt enable */
    149. 

  149. #define SDIO_INTEN_SDIOINTIE            BIT(22)                /*!< SD I/O interrupt received interrupt enable */
    150. 

  150. #define SDIO_INTEN_ATAENDIE             BIT(23)                /*!< CE-ATA command completion signal received interrupt enable */
    151. 

  151. 

  152. /* SDIO_FIFO */
    153. 

  153. #define SDIO_FIFO_FIFODT                BITS(0,31)             /*!< receive FIFO data or transmit FIFO data */
    154. 

  154. 

  155. /* constants definitions */
    156. 

  156. /* SDIO flags */
    157. 

  157. #define SDIO_FLAG_CCRCERR               BIT(0)                 /*!< command response received (CRC check failed) flag */
    158. 

  158. #define SDIO_FLAG_DTCRCERR              BIT(1)                 /*!< data block sent/received (CRC check failed) flag */
    159. 

  159. #define SDIO_FLAG_CMDTMOUT              BIT(2)                 /*!< command response timeout flag */
    160. 

  160. #define SDIO_FLAG_DTTMOUT               BIT(3)                 /*!< data timeout flag */
    161. 

  161. #define SDIO_FLAG_TXURE                 BIT(4)                 /*!< transmit FIFO underrun error occurs flag */
    162. 

  162. #define SDIO_FLAG_RXORE                 BIT(5)                 /*!< received FIFO overrun error occurs flag */
    163. 

  163. #define SDIO_FLAG_CMDRECV               BIT(6)                 /*!< command response received (CRC check passed) flag */
    164. 

  164. #define SDIO_FLAG_CMDSEND               BIT(7)                 /*!< command sent (no response required) flag */
    165. 

  165. #define SDIO_FLAG_DTEND                 BIT(8)                 /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
    166. 

  166. #define SDIO_FLAG_STBITE                BIT(9)                 /*!< start bit error in the bus flag */
    167. 

  167. #define SDIO_FLAG_DTBLKEND              BIT(10)                /*!< data block sent/received (CRC check passed) flag */
    168. 

  168. #define SDIO_FLAG_CMDRUN                BIT(11)                /*!< command transmission in progress flag */
    169. 

  169. #define SDIO_FLAG_TXRUN                 BIT(12)                /*!< data transmission in progress flag */
    170. 

  170. #define SDIO_FLAG_RXRUN                 BIT(13)                /*!< data reception in progress flag */
    171. 

  171. #define SDIO_FLAG_TFH                   BIT(14)                /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
    172. 

  172. #define SDIO_FLAG_RFH                   BIT(15)                /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
    173. 

  173. #define SDIO_FLAG_TFF                   BIT(16)                /*!< transmit FIFO is full flag */
    174. 

  174. #define SDIO_FLAG_RFF                   BIT(17)                /*!< receive FIFO is full flag */
    175. 

  175. #define SDIO_FLAG_TFE                   BIT(18)                /*!< transmit FIFO is empty flag */
    176. 

  176. #define SDIO_FLAG_RFE                   BIT(19)                /*!< receive FIFO is empty flag */
    177. 

  177. #define SDIO_FLAG_TXDTVAL               BIT(20)                /*!< data is valid in transmit FIFO flag */
    178. 

  178. #define SDIO_FLAG_RXDTVAL               BIT(21)                /*!< data is valid in receive FIFO flag */
    179. 

  179. #define SDIO_FLAG_SDIOINT               BIT(22)                /*!< SD I/O interrupt received flag */
    180. 

  180. #define SDIO_FLAG_ATAEND                BIT(23)                /*!< CE-ATA command completion signal received (only for CMD61) flag */
    181. 

  181. 

  182. /* SDIO interrupt flags */
    183. 

  183. #define SDIO_INT_CCRCERR                BIT(0)                 /*!< SDIO CCRCERR interrupt */
    184. 

  184. #define SDIO_INT_DTCRCERR               BIT(1)                 /*!< SDIO DTCRCERR interrupt */
    185. 

  185. #define SDIO_INT_CMDTMOUT               BIT(2)                 /*!< SDIO CMDTMOUT interrupt */
    186. 

  186. #define SDIO_INT_DTTMOUT                BIT(3)                 /*!< SDIO DTTMOUT interrupt */
    187. 

  187. #define SDIO_INT_TXURE                  BIT(4)                 /*!< SDIO TXURE interrupt */
    188. 

  188. #define SDIO_INT_RXORE                  BIT(5)                 /*!< SDIO RXORE interrupt */
    189. 

  189. #define SDIO_INT_CMDRECV                BIT(6)                 /*!< SDIO CMDRECV interrupt */
    190. 

  190. #define SDIO_INT_CMDSEND                BIT(7)                 /*!< SDIO CMDSEND interrupt */
    191. 

  191. #define SDIO_INT_DTEND                  BIT(8)                 /*!< SDIO DTEND interrupt */
    192. 

  192. #define SDIO_INT_STBITE                 BIT(9)                 /*!< SDIO STBITE interrupt */
    193. 

  193. #define SDIO_INT_DTBLKEND               BIT(10)                /*!< SDIO DTBLKEND interrupt */
    194. 

  194. #define SDIO_INT_CMDRUN                 BIT(11)                /*!< SDIO CMDRUN interrupt */
    195. 

  195. #define SDIO_INT_TXRUN                  BIT(12)                /*!< SDIO TXRUN interrupt */
    196. 

  196. #define SDIO_INT_RXRUN                  BIT(13)                /*!< SDIO RXRUN interrupt */
    197. 

  197. #define SDIO_INT_TFH                    BIT(14)                /*!< SDIO TFH interrupt */
    198. 

  198. #define SDIO_INT_RFH                    BIT(15)                /*!< SDIO RFH interrupt */
    199. 

  199. #define SDIO_INT_TFF                    BIT(16)                /*!< SDIO TFF interrupt */
    200. 

  200. #define SDIO_INT_RFF                    BIT(17)                /*!< SDIO RFF interrupt */
    201. 

  201. #define SDIO_INT_TFE                    BIT(18)                /*!< SDIO TFE interrupt */
    202. 

  202. #define SDIO_INT_RFE                    BIT(19)                /*!< SDIO RFE interrupt */
    203. 

  203. #define SDIO_INT_TXDTVAL                BIT(20)                /*!< SDIO TXDTVAL interrupt */
    204. 

  204. #define SDIO_INT_RXDTVAL                BIT(21)                /*!< SDIO RXDTVAL interrupt */
    205. 

  205. #define SDIO_INT_SDIOINT                BIT(22)                /*!< SDIO SDIOINT interrupt */
    206. 

  206. #define SDIO_INT_ATAEND                 BIT(23)                /*!< SDIO ATAEND interrupt */
    207. 

  207. 

  208. /* SDIO power control */
    209. 

  209. #define PWRCTL_PWRCTL(regval)           (BITS(0,1) & ((uint32_t)(regval) << 0))
    210. 

  210. #define SDIO_POWER_OFF                  PWRCTL_PWRCTL(0)       /*!< SDIO power off */
    211. 

  211. #define SDIO_POWER_ON                   PWRCTL_PWRCTL(3)       /*!< SDIO power on */
    212. 

  212. 

  213. /* SDIO card bus mode control */
    214. 

  214. #define CLKCTL_BUSMODE(regval)          (BITS(11,12) & ((uint32_t)(regval) << 11))
    215. 

  215. #define SDIO_BUSMODE_1BIT               CLKCTL_BUSMODE(0)      /*!< 1-bit SDIO card bus mode */
    216. 

  216. #define SDIO_BUSMODE_4BIT               CLKCTL_BUSMODE(1)      /*!< 4-bit SDIO card bus mode */
    217. 

  217. #define SDIO_BUSMODE_8BIT               CLKCTL_BUSMODE(2)      /*!< 8-bit SDIO card bus mode */
    218. 

  218. 

  219. /* SDIO_CLK clock edge selection */
    220. 

  220. #define SDIO_SDIOCLKEDGE_RISING         (uint32_t)0x00000000U  /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
    221. 

  221. #define SDIO_SDIOCLKEDGE_FALLING        SDIO_CLKCTL_CLKEDGE    /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
    222. 

  222. 

  223. /* clock bypass enable or disable */
    224. 

  224. #define SDIO_CLOCKBYPASS_DISABLE        (uint32_t)0x00000000U  /*!< no bypass */
    225. 

  225. #define SDIO_CLOCKBYPASS_ENABLE         SDIO_CLKCTL_CLKBYP     /*!< clock bypass */
    226. 

  226. 

  227. /* SDIO_CLK clock dynamic switch on/off for power saving */
    228. 

  228. #define SDIO_CLOCKPWRSAVE_DISABLE       (uint32_t)0x00000000U  /*!< SDIO_CLK clock is always on */
    229. 

  229. #define SDIO_CLOCKPWRSAVE_ENABLE        SDIO_CLKCTL_CLKPWRSAV  /*!< SDIO_CLK closed when bus is idle */
    230. 

  230. 

  231. /* SDIO command response type */
    232. 

  232. #define CMDCTL_CMDRESP(regval)          (BITS(6,7) & ((uint32_t)(regval) << 6))
    233. 

  233. #define SDIO_RESPONSETYPE_NO            CMDCTL_CMDRESP(0)      /*!< no response */
    234. 

  234. #define SDIO_RESPONSETYPE_SHORT         CMDCTL_CMDRESP(1)      /*!< short response */
    235. 

  235. #define SDIO_RESPONSETYPE_LONG          CMDCTL_CMDRESP(3)      /*!< long response */
    236. 

  236. 

  237. /* command state machine wait type */
    238. 

  238. #define SDIO_WAITTYPE_NO                (uint32_t)0x00000000U  /*!< not wait interrupt */
    239. 

  239. #define SDIO_WAITTYPE_INTERRUPT         SDIO_CMDCTL_INTWAIT    /*!< wait interrupt */
    240. 

  240. #define SDIO_WAITTYPE_DATAEND           SDIO_CMDCTL_WAITDEND   /*!< wait the end of data transfer */
    241. 

  241. 

  242. #define SDIO_RESPONSE0                  (uint32_t)0x00000000U  /*!< card response[31:0]/card response[127:96] */
    243. 

  243. #define SDIO_RESPONSE1                  (uint32_t)0x00000001U  /*!< card response[95:64] */
    244. 

  244. #define SDIO_RESPONSE2                  (uint32_t)0x00000002U  /*!< card response[63:32] */
    245. 

  245. #define SDIO_RESPONSE3                  (uint32_t)0x00000003U  /*!< card response[31:1], plus bit 0 */
    246. 

  246. 

  247. /* SDIO data block size */
    248. 

  248. #define DATACTL_BLKSZ(regval)           (BITS(4,7) & ((uint32_t)(regval) << 4))
    249. 

  249. #define SDIO_DATABLOCKSIZE_1BYTE        DATACTL_BLKSZ(0)       /*!< block size = 1 byte */
    250. 

  250. #define SDIO_DATABLOCKSIZE_2BYTES       DATACTL_BLKSZ(1)       /*!< block size = 2 bytes */
    251. 

  251. #define SDIO_DATABLOCKSIZE_4BYTES       DATACTL_BLKSZ(2)       /*!< block size = 4 bytes */
    252. 

  252. #define SDIO_DATABLOCKSIZE_8BYTES       DATACTL_BLKSZ(3)       /*!< block size = 8 bytes */
    253. 

  253. #define SDIO_DATABLOCKSIZE_16BYTES      DATACTL_BLKSZ(4)       /*!< block size = 16 bytes */
    254. 

  254. #define SDIO_DATABLOCKSIZE_32BYTES      DATACTL_BLKSZ(5)       /*!< block size = 32 bytes */
    255. 

  255. #define SDIO_DATABLOCKSIZE_64BYTES      DATACTL_BLKSZ(6)       /*!< block size = 64 bytes */
    256. 

  256. #define SDIO_DATABLOCKSIZE_128BYTES     DATACTL_BLKSZ(7)       /*!< block size = 128 bytes */
    257. 

  257. #define SDIO_DATABLOCKSIZE_256BYTES     DATACTL_BLKSZ(8)       /*!< block size = 256 bytes */
    258. 

  258. #define SDIO_DATABLOCKSIZE_512BYTES     DATACTL_BLKSZ(9)       /*!< block size = 512 bytes */
    259. 

  259. #define SDIO_DATABLOCKSIZE_1024BYTES    DATACTL_BLKSZ(10)      /*!< block size = 1024 bytes */
    260. 

  260. #define SDIO_DATABLOCKSIZE_2048BYTES    DATACTL_BLKSZ(11)      /*!< block size = 2048 bytes */
    261. 

  261. #define SDIO_DATABLOCKSIZE_4096BYTES    DATACTL_BLKSZ(12)      /*!< block size = 4096 bytes */
    262. 

  262. #define SDIO_DATABLOCKSIZE_8192BYTES    DATACTL_BLKSZ(13)      /*!< block size = 8192 bytes */
    263. 

  263. #define SDIO_DATABLOCKSIZE_16384BYTES   DATACTL_BLKSZ(14)      /*!< block size = 16384 bytes */
    264. 

  264. 

  265. /* SDIO data transfer mode */
    266. 

  266. #define SDIO_TRANSMODE_BLOCK            (uint32_t)0x00000000U  /*!< block transfer */
    267. 

  267. #define SDIO_TRANSMODE_STREAM           SDIO_DATACTL_TRANSMOD  /*!< stream transfer or SDIO multibyte transfer */
    268. 

  268. 

  269. /* SDIO data transfer direction */
    270. 

  270. #define SDIO_TRANSDIRECTION_TOCARD      (uint32_t)0x00000000U  /*!< write data to card */
    271. 

  271. #define SDIO_TRANSDIRECTION_TOSDIO      SDIO_DATACTL_DATADIR   /*!< read data from card */
    272. 

  272. 

  273. /* SDIO read wait type */
    274. 

  274. #define SDIO_READWAITTYPE_DAT2          (uint32_t)0x00000000U  /*!< read wait control using SDIO_DAT[2] */
    275. 

  275. #define SDIO_READWAITTYPE_CLK           SDIO_DATACTL_RWTYPE    /*!< read wait control by stopping SDIO_CLK */
    276. 

  276. 

  277. /* function declarations */
    278. 

  278. /* deinitialize the SDIO */
    279. 

  279. void sdio_deinit(void);
    280. 

  280. /* configure the SDIO clock */
    281. 

  281. void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
    282. 

  282. /* enable hardware clock control */
    283. 

  283. void sdio_hardware_clock_enable(void);
    284. 

  284. /* disable hardware clock control */
    285. 

  285. void sdio_hardware_clock_disable(void);
    286. 

  286. /* set different SDIO card bus mode */
    287. 

  287. void sdio_bus_mode_set(uint32_t bus_mode);
    288. 

  288. /* set the SDIO power state */
    289. 

  289. void sdio_power_state_set(uint32_t power_state);
    290. 

  290. /* get the SDIO power state */
    291. 

  291. uint32_t sdio_power_state_get(void);
    292. 

  292. /* enable SDIO_CLK clock output */
    293. 

  293. void sdio_clock_enable(void);
    294. 

  294. /* disable SDIO_CLK clock output */
    295. 

  295. void sdio_clock_disable(void);
    296. 

  296. 

  297. /* configure the command index, argument, response type, wait type and CSM to send command */
    298. 

  298. /* configure the command and response */
    299. 

  299. void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
    300. 

  300. /* set the command state machine wait type */
    301. 

  301. void sdio_wait_type_set(uint32_t wait_type);
    302. 

  302. /* enable the CSM(command state machine) */
    303. 

  303. void sdio_csm_enable(void);
    304. 

  304. /* disable the CSM(command state machine) */
    305. 

  305. void sdio_csm_disable(void);
    306. 

  306. /* get the last response command index */
    307. 

  307. uint8_t sdio_command_index_get(void);
    308. 

  308. /* get the response for the last received command */
    309. 

  309. uint32_t sdio_response_get(uint32_t sdio_responsex);
    310. 

  310. 

  311. /* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer */
    312. 

  312. /* configure the data timeout, data length and data block size */
    313. 

  313. void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
    314. 

  314. /* configure the data transfer mode and direction */
    315. 

  315. void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
    316. 

  316. /* enable the DSM(data state machine) for data transfer */
    317. 

  317. void sdio_dsm_enable(void);
    318. 

  318. /* disable the DSM(data state machine) */
    319. 

  319. void sdio_dsm_disable(void);
    320. 

  320. /* write data(one word) to the transmit FIFO */
    321. 

  321. void sdio_data_write(uint32_t data);
    322. 

  322. /* read data(one word) from the receive FIFO */
    323. 

  323. uint32_t sdio_data_read(void);
    324. 

  324. /* get the number of remaining data bytes to be transferred to card */
    325. 

  325. uint32_t sdio_data_counter_get(void);
    326. 

  326. /* get the number of words remaining to be written or read from FIFO */
    327. 

  327. uint32_t sdio_fifo_counter_get(void);
    328. 

  328. /* enable the DMA request for SDIO */
    329. 

  329. void sdio_dma_enable(void);
    330. 

  330. /* disable the DMA request for SDIO */
    331. 

  331. void sdio_dma_disable(void);
    332. 

  332. 

  333. /* get the flags state of SDIO */
    334. 

  334. FlagStatus sdio_flag_get(uint32_t flag);
    335. 

  335. /* clear the pending flags of SDIO */
    336. 

  336. void sdio_flag_clear(uint32_t flag);
    337. 

  337. /* enable the SDIO interrupt */
    338. 

  338. void sdio_interrupt_enable(uint32_t int_flag);
    339. 

  339. /* disable the SDIO interrupt */
    340. 

  340. void sdio_interrupt_disable(uint32_t int_flag);
    341. 

  341. /* get the interrupt flags state of SDIO */
    342. 

  342. FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
    343. 

  343. /* clear the interrupt pending flags of SDIO */
    344. 

  344. void sdio_interrupt_flag_clear(uint32_t int_flag);
    345. 

  345. 

  346. /* enable the read wait mode(SD I/O only) */
    347. 

  347. void sdio_readwait_enable(void);
    348. 

  348. /* disable the read wait mode(SD I/O only) */
    349. 

  349. void sdio_readwait_disable(void);
    350. 

  350. /* enable the function that stop the read wait process(SD I/O only) */
    351. 

  351. void sdio_stop_readwait_enable(void);
    352. 

  352. /* disable the function that stop the read wait process(SD I/O only) */
    353. 

  353. void sdio_stop_readwait_disable(void);
    354. 

  354. /* set the read wait type(SD I/O only) */
    355. 

  355. void sdio_readwait_type_set(uint32_t readwait_type);
    356. 

  356. /* enable the SD I/O mode specific operation(SD I/O only) */
    357. 

  357. void sdio_operation_enable(void);
    358. 

  358. /* disable the SD I/O mode specific operation(SD I/O only) */
    359. 

  359. void sdio_operation_disable(void);
    360. 

  360. /* enable the SD I/O suspend operation(SD I/O only) */
    361. 

  361. void sdio_suspend_enable(void);
    362. 

  362. /* disable the SD I/O suspend operation(SD I/O only) */
    363. 

  363. void sdio_suspend_disable(void);
    364. 

  364. 

  365. /* enable the CE-ATA command(CE-ATA only) */
    366. 

  366. void sdio_ceata_command_enable(void);
    367. 

  367. /* disable the CE-ATA command(CE-ATA only) */
    368. 

  368. void sdio_ceata_command_disable(void);
    369. 

  369. /* enable the CE-ATA interrupt(CE-ATA only) */
    370. 

  370. void sdio_ceata_interrupt_enable(void);
    371. 

  371. /* disable the CE-ATA interrupt(CE-ATA only) */
    372. 

  372. void sdio_ceata_interrupt_disable(void);
    373. 

  373. /* enable the CE-ATA command completion signal(CE-ATA only) */
    374. 

  374. void sdio_ceata_command_completion_enable(void);
    375. 

  375. /* disable the CE-ATA command completion signal(CE-ATA only) */
    376. 

  376. void sdio_ceata_command_completion_disable(void);
    377. 

  377. 

  378. #endif /* GD32F4XX_SDIO_H */
    379.