drv_spi.c 7.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2019-07-15 Magicoe The first version for LPC55S6x
  9. */
  10. #include "rtdevice.h"
  11. #include "fsl_common.h"
  12. #include "fsl_iocon.h"
  13. #include "fsl_spi.h"
  14. #include "fsl_spi_dma.h"
  15. enum
  16. {
  17. #ifdef BSP_USING_SPI3
  18. SPI3_INDEX,
  19. #endif
  20. #ifdef BSP_USING_SPI8
  21. SPI8_INDEX,
  22. #endif
  23. };
  24. struct lpc_spi
  25. {
  26. struct rt_spi_bus parent;
  27. SPI_Type *SPIx;
  28. clock_attach_id_t clock_attach_id;
  29. clock_ip_name_t clock_name;
  30. DMA_Type *DMAx;
  31. uint8_t tx_dma_chl;
  32. uint8_t rx_dma_chl;
  33. dma_handle_t dma_tx_handle;
  34. dma_handle_t dma_rx_handle;
  35. spi_dma_handle_t spi_dma_handle;
  36. rt_sem_t sem;
  37. char *device_name;
  38. };
  39. static struct lpc_spi lpc_obj[] =
  40. {
  41. #ifdef BSP_USING_SPI3
  42. {
  43. .SPIx = SPI3,
  44. .clock_attach_id = kMAIN_CLK_to_FLEXCOMM3,
  45. .clock_name = kCLOCK_FlexComm3,
  46. .device_name = "spi3",
  47. .DMAx = DMA0,
  48. .tx_dma_chl = 9,
  49. .rx_dma_chl = 8,
  50. },
  51. #endif
  52. #ifdef BSP_USING_SPI8
  53. {
  54. .SPIx = SPI8,
  55. .clock_attach_id = kMAIN_CLK_to_HSLSPI,
  56. .clock_name = kCLOCK_Hs_Lspi,
  57. .device_name = "spi8",
  58. .DMAx = DMA0,
  59. .tx_dma_chl = 3,
  60. .rx_dma_chl = 2,
  61. },
  62. #endif
  63. };
  64. struct lpc_sw_spi_cs
  65. {
  66. rt_uint32_t pin;
  67. };
  68. static uint32_t lpc_get_spi_freq(SPI_Type *base)
  69. {
  70. uint32_t freq = 0;
  71. if(base == SPI3)
  72. {
  73. freq = CLOCK_GetFlexCommClkFreq(kCLOCK_FlexComm3);
  74. }
  75. if(base == SPI8)
  76. {
  77. freq = CLOCK_GetFlexCommClkFreq(kCLOCK_Hs_Lspi);
  78. }
  79. return freq;
  80. }
  81. static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
  82. {
  83. spi_master_config_t masterConfig = {0};
  84. SPI_MasterGetDefaultConfig(&masterConfig);
  85. if(cfg->data_width != 8 && cfg->data_width != 16)
  86. {
  87. cfg->data_width = 8;
  88. }
  89. masterConfig.baudRate_Bps = cfg->max_hz;
  90. if(cfg->data_width == 8)
  91. {
  92. masterConfig.dataWidth = kSPI_Data8Bits;
  93. }
  94. else if(cfg->data_width == 16)
  95. {
  96. masterConfig.dataWidth = kSPI_Data16Bits;
  97. }
  98. if(cfg->mode & RT_SPI_MSB)
  99. {
  100. masterConfig.direction = kSPI_MsbFirst;
  101. }
  102. else
  103. {
  104. masterConfig.direction = kSPI_LsbFirst;
  105. }
  106. if(cfg->mode & RT_SPI_CPHA)
  107. {
  108. masterConfig.phase = kSPI_ClockPhaseSecondEdge;
  109. }
  110. else
  111. {
  112. masterConfig.phase = kSPI_ClockPhaseFirstEdge;
  113. }
  114. if(cfg->mode & RT_SPI_CPOL)
  115. {
  116. masterConfig.polarity = kSPI_ClockPolarityActiveLow;
  117. }
  118. else
  119. {
  120. masterConfig.polarity = kSPI_ClockPolarityActiveHigh;
  121. }
  122. SPI_MasterInit(base, &masterConfig, lpc_get_spi_freq(base));
  123. return RT_EOK;
  124. }
  125. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
  126. {
  127. rt_err_t ret = RT_EOK;
  128. struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
  129. struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
  130. cs_pin->pin = pin;
  131. rt_pin_mode(pin, PIN_MODE_OUTPUT);
  132. rt_pin_write(pin, PIN_HIGH);
  133. ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
  134. return ret;
  135. }
  136. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  137. {
  138. rt_err_t ret = RT_EOK;
  139. struct lpc_spi *spi = RT_NULL;
  140. spi = (struct lpc_spi *)(device->bus->parent.user_data);
  141. ret = lpc_spi_init(spi->SPIx, cfg);
  142. return ret;
  143. }
  144. static void SPI_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
  145. {
  146. struct lpc_spi *spi = (struct lpc_spi*)userData;
  147. rt_sem_release(spi->sem);
  148. }
  149. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  150. {
  151. int i;
  152. spi_transfer_t transfer = {0};
  153. RT_ASSERT(device != RT_NULL);
  154. RT_ASSERT(device->bus != RT_NULL);
  155. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  156. struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
  157. struct lpc_sw_spi_cs *cs = device->parent.user_data;
  158. if(message->cs_take)
  159. {
  160. rt_pin_write(cs->pin, PIN_LOW);
  161. }
  162. transfer.dataSize = message->length;
  163. transfer.rxData = (uint8_t *)(message->recv_buf);
  164. transfer.txData = (uint8_t *)(message->send_buf);
  165. transfer.configFlags = kSPI_FrameAssert;
  166. // if(message->length < MAX_DMA_TRANSFER_SIZE)
  167. if(0)
  168. {
  169. SPI_MasterTransferBlocking(spi->SPIx, &transfer);
  170. }
  171. else
  172. {
  173. uint32_t block, remain;
  174. block = message->length / DMA_MAX_TRANSFER_COUNT;
  175. remain = message->length % DMA_MAX_TRANSFER_COUNT;
  176. for(i=0; i<block; i++)
  177. {
  178. transfer.dataSize = DMA_MAX_TRANSFER_COUNT;
  179. if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
  180. if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
  181. SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
  182. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  183. }
  184. if(remain)
  185. {
  186. transfer.dataSize = remain;
  187. if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
  188. if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
  189. SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
  190. rt_sem_take(spi->sem, RT_WAITING_FOREVER);
  191. }
  192. }
  193. if(message->cs_release)
  194. {
  195. rt_pin_write(cs->pin, PIN_HIGH);
  196. }
  197. return message->length;
  198. }
  199. static struct rt_spi_ops lpc_spi_ops =
  200. {
  201. .configure = spi_configure,
  202. .xfer = spixfer
  203. };
  204. int rt_hw_spi_init(void)
  205. {
  206. int i;
  207. for(i=0; i<ARRAY_SIZE(lpc_obj); i++)
  208. {
  209. CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
  210. lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
  211. lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
  212. DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  213. DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  214. DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, kDMA_ChannelPriority3);
  215. DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, kDMA_ChannelPriority2);
  216. DMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
  217. DMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
  218. SPI_MasterTransferCreateHandleDMA(lpc_obj[i].SPIx, &lpc_obj[i].spi_dma_handle, SPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_tx_handle, &lpc_obj[i].dma_rx_handle);
  219. rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].device_name, &lpc_spi_ops);
  220. }
  221. return RT_EOK;
  222. }
  223. INIT_DEVICE_EXPORT(rt_hw_spi_init);