stm32g031xx.h 583 KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32g031xx.h
  4. * @author MCD Application Team
  5. * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
  6. * This file contains all the peripheral register's definitions, bits
  7. * definitions and memory mapping for stm32g031xx devices.
  8. *
  9. * This file contains:
  10. * - Data structures and the address mapping for all peripherals
  11. * - Peripheral's registers declarations and bits definition
  12. * - Macros to access peripheral's registers hardware
  13. *
  14. ******************************************************************************
  15. * @attention
  16. *
  17. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
  18. * All rights reserved.</center></h2>
  19. *
  20. * This software component is licensed by ST under BSD 3-Clause license,
  21. * the "License"; You may not use this file except in compliance with the
  22. * License. You may obtain a copy of the License at:
  23. * opensource.org/licenses/BSD-3-Clause
  24. *
  25. ******************************************************************************
  26. */
  27. /** @addtogroup CMSIS_Device
  28. * @{
  29. */
  30. /** @addtogroup stm32g031xx
  31. * @{
  32. */
  33. #ifndef STM32G031xx_H
  34. #define STM32G031xx_H
  35. #ifdef __cplusplus
  36. extern "C" {
  37. #endif /* __cplusplus */
  38. /** @addtogroup Configuration_section_for_CMSIS
  39. * @{
  40. */
  41. /**
  42. * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
  43. */
  44. #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
  45. #define __MPU_PRESENT 1 /*!< STM32G0xx provides an MPU */
  46. #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
  47. #define __NVIC_PRIO_BITS 2 /*!< STM32G0xx uses 2 Bits for the Priority Levels */
  48. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  49. /**
  50. * @}
  51. */
  52. /** @addtogroup Peripheral_interrupt_number_definition
  53. * @{
  54. */
  55. /**
  56. * @brief stm32g031xx Interrupt Number Definition, according to the selected device
  57. * in @ref Library_configuration_section
  58. */
  59. /*!< Interrupt Number Definition */
  60. typedef enum
  61. {
  62. /****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/
  63. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  64. HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */
  65. SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
  66. PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
  67. SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
  68. /****** STM32G0xxxx specific Interrupt Numbers ****************************************************************/
  69. WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
  70. PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */
  71. RTC_TAMP_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 & 21 */
  72. FLASH_IRQn = 3, /*!< FLASH global Interrupt */
  73. RCC_IRQn = 4, /*!< RCC global Interrupt */
  74. EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */
  75. EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
  76. EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
  77. DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
  78. DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
  79. DMA1_Ch4_5_DMAMUX1_OVR_IRQn = 11, /*!< DMA1 Channel 4 to Channel 5 and DMAMUX1 Overrun Interrupts */
  80. ADC1_IRQn = 12, /*!< ADC1 Interrupts */
  81. TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
  82. TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
  83. TIM2_IRQn = 15, /*!< TIM2 Interrupt */
  84. TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
  85. LPTIM1_IRQn = 17, /*!< LPTIM1 global Interrupts */
  86. LPTIM2_IRQn = 18, /*!< LPTIM2 global Interrupt */
  87. TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
  88. TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
  89. TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
  90. I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */
  91. I2C2_IRQn = 24, /*!< I2C2 Interrupt */
  92. SPI1_IRQn = 25, /*!< SPI1/I2S1 Interrupt */
  93. SPI2_IRQn = 26, /*!< SPI2 Interrupt */
  94. USART1_IRQn = 27, /*!< USART1 Interrupt */
  95. USART2_IRQn = 28, /*!< USART2 Interrupt */
  96. LPUART1_IRQn = 29, /*!< LPUART1 globlal Interrupts (combined with EXTI 28) */
  97. } IRQn_Type;
  98. /**
  99. * @}
  100. */
  101. #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
  102. #include "system_stm32g0xx.h"
  103. #include <stdint.h>
  104. /** @addtogroup Peripheral_registers_structures
  105. * @{
  106. */
  107. /**
  108. * @brief Analog to Digital Converter
  109. */
  110. typedef struct
  111. {
  112. __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
  113. __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
  114. __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
  115. __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
  116. __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
  117. __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
  118. uint32_t RESERVED1; /*!< Reserved, 0x18 */
  119. uint32_t RESERVED2; /*!< Reserved, 0x1C */
  120. __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
  121. __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
  122. __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
  123. __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x2C */
  124. uint32_t RESERVED3[4]; /*!< Reserved, 0x30 - 0x3C */
  125. __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
  126. uint32_t RESERVED4[23];/*!< Reserved, 0x44 - 0x9C */
  127. __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
  128. __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 configuration register, Address offset: 0xA4 */
  129. uint32_t RESERVED5[3]; /*!< Reserved, 0xA8 - 0xB0 */
  130. __IO uint32_t CALFACT; /*!< ADC Calibration factor register, Address offset: 0xB4 */
  131. } ADC_TypeDef;
  132. typedef struct
  133. {
  134. __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
  135. } ADC_Common_TypeDef;
  136. /**
  137. * @brief CRC calculation unit
  138. */
  139. typedef struct
  140. {
  141. __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
  142. __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
  143. __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
  144. uint32_t RESERVED1; /*!< Reserved, 0x0C */
  145. __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
  146. __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
  147. } CRC_TypeDef;
  148. /**
  149. * @brief Debug MCU
  150. */
  151. typedef struct
  152. {
  153. __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
  154. __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */
  155. __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */
  156. __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */
  157. } DBG_TypeDef;
  158. /**
  159. * @brief DMA Controller
  160. */
  161. typedef struct
  162. {
  163. __IO uint32_t CCR; /*!< DMA channel x configuration register */
  164. __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
  165. __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
  166. __IO uint32_t CMAR; /*!< DMA channel x memory address register */
  167. } DMA_Channel_TypeDef;
  168. typedef struct
  169. {
  170. __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
  171. __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
  172. } DMA_TypeDef;
  173. /**
  174. * @brief DMA Multiplexer
  175. */
  176. typedef struct
  177. {
  178. __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
  179. }DMAMUX_Channel_TypeDef;
  180. typedef struct
  181. {
  182. __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
  183. __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
  184. }DMAMUX_ChannelStatus_TypeDef;
  185. typedef struct
  186. {
  187. __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
  188. }DMAMUX_RequestGen_TypeDef;
  189. typedef struct
  190. {
  191. __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
  192. __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
  193. }DMAMUX_RequestGenStatus_TypeDef;
  194. /**
  195. * @brief Asynch Interrupt/Event Controller (EXTI)
  196. */
  197. typedef struct
  198. {
  199. __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */
  200. __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */
  201. __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */
  202. __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */
  203. __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */
  204. uint32_t RESERVED1[3]; /*!< Reserved 1, 0x14 -- 0x1C */
  205. uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */
  206. uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */
  207. __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x6C */
  208. uint32_t RESERVED4[4]; /*!< Reserved 4, 0x70 -- 0x7C */
  209. __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */
  210. __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */
  211. } EXTI_TypeDef;
  212. /**
  213. * @brief FLASH Registers
  214. */
  215. typedef struct
  216. {
  217. __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
  218. uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */
  219. __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
  220. __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
  221. __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
  222. __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */
  223. __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
  224. uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
  225. __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */
  226. __IO uint32_t PCROP1ASR; /*!< FLASH Bank PCROP area A Start address register, Address offset: 0x24 */
  227. __IO uint32_t PCROP1AER; /*!< FLASH Bank PCROP area A End address register, Address offset: 0x28 */
  228. __IO uint32_t WRP1AR; /*!< FLASH Bank WRP area A address register, Address offset: 0x2C */
  229. __IO uint32_t WRP1BR; /*!< FLASH Bank WRP area B address register, Address offset: 0x30 */
  230. __IO uint32_t PCROP1BSR; /*!< FLASH Bank PCROP area B Start address register, Address offset: 0x34 */
  231. __IO uint32_t PCROP1BER; /*!< FLASH Bank PCROP area B End address register, Address offset: 0x38 */
  232. uint32_t RESERVED3[17];/*!< Reserved3, Address offset: 0x3C */
  233. __IO uint32_t SECR; /*!< FLASH security register , Address offset: 0x80 */
  234. } FLASH_TypeDef;
  235. /**
  236. * @brief General Purpose I/O
  237. */
  238. typedef struct
  239. {
  240. __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
  241. __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
  242. __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
  243. __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
  244. __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
  245. __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
  246. __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
  247. __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
  248. __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
  249. __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
  250. } GPIO_TypeDef;
  251. /**
  252. * @brief Inter-integrated Circuit Interface
  253. */
  254. typedef struct
  255. {
  256. __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
  257. __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
  258. __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
  259. __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
  260. __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
  261. __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
  262. __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
  263. __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
  264. __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
  265. __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
  266. __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
  267. } I2C_TypeDef;
  268. /**
  269. * @brief Independent WATCHDOG
  270. */
  271. typedef struct
  272. {
  273. __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
  274. __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
  275. __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
  276. __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
  277. __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
  278. } IWDG_TypeDef;
  279. /**
  280. * @brief LPTIMER
  281. */
  282. typedef struct
  283. {
  284. __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
  285. __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
  286. __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
  287. __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
  288. __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
  289. __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
  290. __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
  291. __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
  292. __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x20 */
  293. __IO uint32_t CFGR2; /*!< LPTIM Option register, Address offset: 0x24 */
  294. } LPTIM_TypeDef;
  295. /**
  296. * @brief Power Control
  297. */
  298. typedef struct
  299. {
  300. __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */
  301. __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */
  302. __IO uint32_t CR3; /*!< PWR Power Control Register 3, Address offset: 0x08 */
  303. __IO uint32_t CR4; /*!< PWR Power Control Register 4, Address offset: 0x0C */
  304. __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
  305. __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
  306. __IO uint32_t SCR; /*!< PWR Power Status Clear Register, Address offset: 0x18 */
  307. uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
  308. __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
  309. __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
  310. __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
  311. __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
  312. __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
  313. __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
  314. __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
  315. __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
  316. uint32_t RESERVED2; /*!< Reserved, Address offset: 0x40 */
  317. uint32_t RESERVED3; /*!< Reserved, Address offset: 0x44 */
  318. __IO uint32_t PUCRF; /*!< PWR Pull-Up Control Register of port F, Address offset: 0x48 */
  319. __IO uint32_t PDCRF; /*!< PWR Pull-Down Control Register of port F, Address offset: 0x4C */
  320. } PWR_TypeDef;
  321. /**
  322. * @brief Reset and Clock Control
  323. */
  324. typedef struct
  325. {
  326. __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
  327. __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
  328. __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */
  329. __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */
  330. __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
  331. __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
  332. __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
  333. __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
  334. __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
  335. __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */
  336. __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */
  337. __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */
  338. __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */
  339. __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */
  340. __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */
  341. __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */
  342. __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */
  343. __IO uint32_t IOPSMENR; /*!< RCC IO port clocks enable in sleep mode register, Address offset: 0x44 */
  344. __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clocks enable in sleep mode register, Address offset: 0x48 */
  345. __IO uint32_t APBSMENR1; /*!< RCC APB peripheral clocks enable in sleep mode register1, Address offset: 0x4C */
  346. __IO uint32_t APBSMENR2; /*!< RCC APB peripheral clocks enable in sleep mode register2, Address offset: 0x50 */
  347. __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */
  348. __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */
  349. __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */
  350. __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */
  351. } RCC_TypeDef;
  352. /**
  353. * @brief Real-Time Clock
  354. */
  355. typedef struct
  356. {
  357. __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
  358. __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
  359. __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
  360. __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
  361. __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
  362. __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
  363. __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
  364. uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
  365. uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
  366. __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
  367. __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
  368. __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
  369. __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
  370. __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
  371. __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
  372. uint32_t RESERVED2; /*!< Reserved Address offset: 0x1C */
  373. __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
  374. __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
  375. __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
  376. __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
  377. __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
  378. __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
  379. uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
  380. __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
  381. __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */
  382. } RTC_TypeDef;
  383. /**
  384. * @brief Tamper and backup registers
  385. */
  386. typedef struct
  387. {
  388. __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
  389. __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
  390. uint32_t RESERVED0; /*!< Reserved Address offset: 0x08 */
  391. __IO uint32_t FLTCR; /*!< Reserved Address offset: 0x0C */
  392. uint32_t RESERVED1[7]; /*!< Reserved Address offset: 0x10 -- 0x28 */
  393. __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
  394. __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
  395. __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register, Address offset: 0x34 */
  396. uint32_t RESERVED2; /*!< Reserved Address offset: 0x38 */
  397. __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
  398. uint32_t RESERVED3[48]; /*!< Reserved Address offset: 0x54 -- 0xFC */
  399. __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
  400. __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
  401. __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
  402. __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
  403. __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
  404. } TAMP_TypeDef;
  405. /**
  406. * @brief Serial Peripheral Interface
  407. */
  408. typedef struct
  409. {
  410. __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
  411. __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
  412. __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
  413. __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
  414. __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  415. __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
  416. __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
  417. __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
  418. __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
  419. } SPI_TypeDef;
  420. /**
  421. * @brief System configuration controller
  422. */
  423. typedef struct
  424. {
  425. __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
  426. uint32_t RESERVED0[5]; /*!< Reserved, 0x04 --0x14 */
  427. __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
  428. uint32_t RESERVED1[25]; /*!< Reserved 0x1C */
  429. __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
  430. } SYSCFG_TypeDef;
  431. /**
  432. * @brief TIM
  433. */
  434. typedef struct
  435. {
  436. __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
  437. __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
  438. __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
  439. __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
  440. __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
  441. __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
  442. __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
  443. __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
  444. __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
  445. __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
  446. __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
  447. __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
  448. __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
  449. __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
  450. __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
  451. __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
  452. __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
  453. __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
  454. __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
  455. __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
  456. __IO uint32_t OR1; /*!< TIM option register, Address offset: 0x50 */
  457. __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
  458. __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
  459. __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
  460. __IO uint32_t AF1; /*!< TIM alternate function register 1, Address offset: 0x60 */
  461. __IO uint32_t AF2; /*!< TIM alternate function register 2, Address offset: 0x64 */
  462. __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
  463. } TIM_TypeDef;
  464. /**
  465. * @brief Universal Synchronous Asynchronous Receiver Transmitter
  466. */
  467. typedef struct
  468. {
  469. __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
  470. __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
  471. __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
  472. __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
  473. __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
  474. __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
  475. __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
  476. __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
  477. __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
  478. __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
  479. __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
  480. __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
  481. } USART_TypeDef;
  482. /**
  483. * @brief VREFBUF
  484. */
  485. typedef struct
  486. {
  487. __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
  488. __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
  489. } VREFBUF_TypeDef;
  490. /**
  491. * @brief Window WATCHDOG
  492. */
  493. typedef struct
  494. {
  495. __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
  496. __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
  497. __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
  498. } WWDG_TypeDef;
  499. /** @addtogroup Peripheral_memory_map
  500. * @{
  501. */
  502. #define FLASH_BASE (0x08000000UL) /*!< FLASH base address */
  503. #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */
  504. #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
  505. #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */
  506. #define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8 KBytes) */
  507. /*!< Peripheral memory map */
  508. #define APBPERIPH_BASE (PERIPH_BASE)
  509. #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
  510. /*!< APB peripherals */
  511. #define TIM2_BASE (APBPERIPH_BASE + 0UL)
  512. #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL)
  513. #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL)
  514. #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL)
  515. #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL)
  516. #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL)
  517. #define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL)
  518. #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL)
  519. #define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL)
  520. #define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL)
  521. #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL)
  522. #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL)
  523. #define LPUART1_BASE (APBPERIPH_BASE + 0x00008000UL)
  524. #define LPTIM2_BASE (APBPERIPH_BASE + 0x00009400UL)
  525. #define TAMP_BASE (APBPERIPH_BASE + 0x0000B000UL)
  526. #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL)
  527. #define VREFBUF_BASE (APBPERIPH_BASE + 0x00010030UL)
  528. #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
  529. #define ADC1_COMMON_BASE (APBPERIPH_BASE + 0x00012708UL)
  530. #define ADC_BASE (ADC1_COMMON_BASE) /* Kept for legacy purpose */
  531. #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL)
  532. #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
  533. #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL)
  534. #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL)
  535. #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL)
  536. #define DBG_BASE (APBPERIPH_BASE + 0x00015800UL)
  537. /*!< AHB peripherals */
  538. #define DMA1_BASE (AHBPERIPH_BASE)
  539. #define DMAMUX1_BASE (AHBPERIPH_BASE + 0x00000800UL)
  540. #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
  541. #define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL)
  542. #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
  543. #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
  544. #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL)
  545. #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL)
  546. #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
  547. #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
  548. #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
  549. #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
  550. #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x00000004UL)
  551. #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x00000008UL)
  552. #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x0000000CUL)
  553. #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x00000010UL)
  554. #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x00000100UL)
  555. #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x00000104UL)
  556. #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x00000108UL)
  557. #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x0000010CUL)
  558. #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x00000080UL)
  559. #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x00000140UL)
  560. /*!< IOPORT */
  561. #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL)
  562. #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL)
  563. #define GPIOC_BASE (IOPORT_BASE + 0x00000800UL)
  564. #define GPIOD_BASE (IOPORT_BASE + 0x00000C00UL)
  565. #define GPIOF_BASE (IOPORT_BASE + 0x00001400UL)
  566. /*!< Device Electronic Signature */
  567. #define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
  568. #define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
  569. #define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
  570. /**
  571. * @}
  572. */
  573. /** @addtogroup Peripheral_declaration
  574. * @{
  575. */
  576. #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
  577. #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
  578. #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
  579. #define RTC ((RTC_TypeDef *) RTC_BASE)
  580. #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
  581. #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
  582. #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
  583. #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
  584. #define USART2 ((USART_TypeDef *) USART2_BASE)
  585. #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
  586. #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
  587. #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
  588. #define PWR ((PWR_TypeDef *) PWR_BASE)
  589. #define RCC ((RCC_TypeDef *) RCC_BASE)
  590. #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
  591. #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
  592. #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
  593. #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
  594. #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
  595. #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
  596. #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
  597. #define USART1 ((USART_TypeDef *) USART1_BASE)
  598. #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
  599. #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
  600. #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
  601. #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
  602. #define CRC ((CRC_TypeDef *) CRC_BASE)
  603. #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
  604. #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
  605. #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
  606. #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
  607. #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
  608. #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
  609. #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
  610. #define ADC (ADC1_COMMON) /* Kept for legacy purpose */
  611. #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
  612. #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
  613. #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
  614. #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
  615. #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
  616. #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
  617. #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
  618. #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
  619. #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
  620. #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
  621. #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
  622. #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
  623. #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
  624. #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
  625. #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
  626. #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
  627. #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
  628. #define DBG ((DBG_TypeDef *) DBG_BASE)
  629. /**
  630. * @}
  631. */
  632. /** @addtogroup Exported_constants
  633. * @{
  634. */
  635. /** @addtogroup Peripheral_Registers_Bits_Definition
  636. * @{
  637. */
  638. /******************************************************************************/
  639. /* Peripheral Registers Bits Definition */
  640. /******************************************************************************/
  641. /******************************************************************************/
  642. /* */
  643. /* Analog to Digital Converter (ADC) */
  644. /* */
  645. /******************************************************************************/
  646. /******************** Bit definition for ADC_ISR register *******************/
  647. #define ADC_ISR_ADRDY_Pos (0U)
  648. #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
  649. #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
  650. #define ADC_ISR_EOSMP_Pos (1U)
  651. #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
  652. #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
  653. #define ADC_ISR_EOC_Pos (2U)
  654. #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
  655. #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
  656. #define ADC_ISR_EOS_Pos (3U)
  657. #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
  658. #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
  659. #define ADC_ISR_OVR_Pos (4U)
  660. #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
  661. #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
  662. #define ADC_ISR_AWD1_Pos (7U)
  663. #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
  664. #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
  665. #define ADC_ISR_AWD2_Pos (8U)
  666. #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
  667. #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
  668. #define ADC_ISR_AWD3_Pos (9U)
  669. #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
  670. #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
  671. #define ADC_ISR_EOCAL_Pos (11U)
  672. #define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */
  673. #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC end of calibration flag */
  674. #define ADC_ISR_CCRDY_Pos (13U)
  675. #define ADC_ISR_CCRDY_Msk (0x1UL << ADC_ISR_CCRDY_Pos) /*!< 0x00002000 */
  676. #define ADC_ISR_CCRDY ADC_ISR_CCRDY_Msk /*!< ADC channel configuration ready flag */
  677. /* Legacy defines */
  678. #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
  679. /******************** Bit definition for ADC_IER register *******************/
  680. #define ADC_IER_ADRDYIE_Pos (0U)
  681. #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
  682. #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
  683. #define ADC_IER_EOSMPIE_Pos (1U)
  684. #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
  685. #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
  686. #define ADC_IER_EOCIE_Pos (2U)
  687. #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
  688. #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
  689. #define ADC_IER_EOSIE_Pos (3U)
  690. #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
  691. #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
  692. #define ADC_IER_OVRIE_Pos (4U)
  693. #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
  694. #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
  695. #define ADC_IER_AWD1IE_Pos (7U)
  696. #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
  697. #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
  698. #define ADC_IER_AWD2IE_Pos (8U)
  699. #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
  700. #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
  701. #define ADC_IER_AWD3IE_Pos (9U)
  702. #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
  703. #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
  704. #define ADC_IER_EOCALIE_Pos (11U)
  705. #define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */
  706. #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC end of calibration interrupt */
  707. #define ADC_IER_CCRDYIE_Pos (13U)
  708. #define ADC_IER_CCRDYIE_Msk (0x1UL << ADC_IER_CCRDYIE_Pos) /*!< 0x00002000 */
  709. #define ADC_IER_CCRDYIE ADC_IER_CCRDYIE_Msk /*!< ADC channel configuration ready interrupt */
  710. /* Legacy defines */
  711. #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
  712. /******************** Bit definition for ADC_CR register ********************/
  713. #define ADC_CR_ADEN_Pos (0U)
  714. #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
  715. #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
  716. #define ADC_CR_ADDIS_Pos (1U)
  717. #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
  718. #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
  719. #define ADC_CR_ADSTART_Pos (2U)
  720. #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
  721. #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
  722. #define ADC_CR_ADSTP_Pos (4U)
  723. #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
  724. #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
  725. #define ADC_CR_ADVREGEN_Pos (28U)
  726. #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
  727. #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
  728. #define ADC_CR_ADCAL_Pos (31U)
  729. #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
  730. #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
  731. /******************** Bit definition for ADC_CFGR1 register *****************/
  732. #define ADC_CFGR1_DMAEN_Pos (0U)
  733. #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
  734. #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
  735. #define ADC_CFGR1_DMACFG_Pos (1U)
  736. #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
  737. #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
  738. #define ADC_CFGR1_SCANDIR_Pos (2U)
  739. #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
  740. #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
  741. #define ADC_CFGR1_RES_Pos (3U)
  742. #define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
  743. #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
  744. #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
  745. #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
  746. #define ADC_CFGR1_ALIGN_Pos (5U)
  747. #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
  748. #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
  749. #define ADC_CFGR1_EXTSEL_Pos (6U)
  750. #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
  751. #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
  752. #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
  753. #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
  754. #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
  755. #define ADC_CFGR1_EXTEN_Pos (10U)
  756. #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
  757. #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
  758. #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
  759. #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
  760. #define ADC_CFGR1_OVRMOD_Pos (12U)
  761. #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
  762. #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
  763. #define ADC_CFGR1_CONT_Pos (13U)
  764. #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
  765. #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
  766. #define ADC_CFGR1_WAIT_Pos (14U)
  767. #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
  768. #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
  769. #define ADC_CFGR1_AUTOFF_Pos (15U)
  770. #define ADC_CFGR1_AUTOFF_Msk (0x1UL << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
  771. #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
  772. #define ADC_CFGR1_DISCEN_Pos (16U)
  773. #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
  774. #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
  775. #define ADC_CFGR1_CHSELRMOD_Pos (21U)
  776. #define ADC_CFGR1_CHSELRMOD_Msk (0x1UL << ADC_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */
  777. #define ADC_CFGR1_CHSELRMOD ADC_CFGR1_CHSELRMOD_Msk /*!< ADC group regular sequencer mode */
  778. #define ADC_CFGR1_AWD1SGL_Pos (22U)
  779. #define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
  780. #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
  781. #define ADC_CFGR1_AWD1EN_Pos (23U)
  782. #define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
  783. #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
  784. #define ADC_CFGR1_AWD1CH_Pos (26U)
  785. #define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
  786. #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
  787. #define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
  788. #define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
  789. #define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
  790. #define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
  791. #define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
  792. /* Legacy defines */
  793. #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
  794. /******************** Bit definition for ADC_CFGR2 register *****************/
  795. #define ADC_CFGR2_OVSE_Pos (0U)
  796. #define ADC_CFGR2_OVSE_Msk (0x1UL << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */
  797. #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
  798. #define ADC_CFGR2_OVSR_Pos (2U)
  799. #define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
  800. #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
  801. #define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
  802. #define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
  803. #define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
  804. #define ADC_CFGR2_OVSS_Pos (5U)
  805. #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
  806. #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
  807. #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
  808. #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
  809. #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
  810. #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
  811. #define ADC_CFGR2_TOVS_Pos (9U)
  812. #define ADC_CFGR2_TOVS_Msk (0x1UL << ADC_CFGR2_TOVS_Pos) /*!< 0x00000200 */
  813. #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
  814. #define ADC_CFGR2_LFTRIG_Pos (29U)
  815. #define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */
  816. #define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */
  817. #define ADC_CFGR2_CKMODE_Pos (30U)
  818. #define ADC_CFGR2_CKMODE_Msk (0x3UL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
  819. #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
  820. #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
  821. #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
  822. /******************** Bit definition for ADC_SMPR register ******************/
  823. #define ADC_SMPR_SMP1_Pos (0U)
  824. #define ADC_SMPR_SMP1_Msk (0x7UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000007 */
  825. #define ADC_SMPR_SMP1 ADC_SMPR_SMP1_Msk /*!< ADC group of channels sampling time 1 */
  826. #define ADC_SMPR_SMP1_0 (0x1UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000001 */
  827. #define ADC_SMPR_SMP1_1 (0x2UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000002 */
  828. #define ADC_SMPR_SMP1_2 (0x4UL << ADC_SMPR_SMP1_Pos) /*!< 0x00000004 */
  829. #define ADC_SMPR_SMP2_Pos (4U)
  830. #define ADC_SMPR_SMP2_Msk (0x7UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000070 */
  831. #define ADC_SMPR_SMP2 ADC_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */
  832. #define ADC_SMPR_SMP2_0 (0x1UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000010 */
  833. #define ADC_SMPR_SMP2_1 (0x2UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000020 */
  834. #define ADC_SMPR_SMP2_2 (0x4UL << ADC_SMPR_SMP2_Pos) /*!< 0x00000040 */
  835. #define ADC_SMPR_SMPSEL_Pos (8U)
  836. #define ADC_SMPR_SMPSEL_Msk (0x7FFFFUL << ADC_SMPR_SMPSEL_Pos) /*!< 0x07FFFF00 */
  837. #define ADC_SMPR_SMPSEL ADC_SMPR_SMPSEL_Msk /*!< ADC all channels sampling time selection */
  838. #define ADC_SMPR_SMPSEL0_Pos (8U)
  839. #define ADC_SMPR_SMPSEL0_Msk (0x1UL << ADC_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */
  840. #define ADC_SMPR_SMPSEL0 ADC_SMPR_SMPSEL0_Msk /*!< ADC channel 0 sampling time selection */
  841. #define ADC_SMPR_SMPSEL1_Pos (9U)
  842. #define ADC_SMPR_SMPSEL1_Msk (0x1UL << ADC_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */
  843. #define ADC_SMPR_SMPSEL1 ADC_SMPR_SMPSEL1_Msk /*!< ADC channel 1 sampling time selection */
  844. #define ADC_SMPR_SMPSEL2_Pos (10U)
  845. #define ADC_SMPR_SMPSEL2_Msk (0x1UL << ADC_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */
  846. #define ADC_SMPR_SMPSEL2 ADC_SMPR_SMPSEL2_Msk /*!< ADC channel 2 sampling time selection */
  847. #define ADC_SMPR_SMPSEL3_Pos (11U)
  848. #define ADC_SMPR_SMPSEL3_Msk (0x1UL << ADC_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */
  849. #define ADC_SMPR_SMPSEL3 ADC_SMPR_SMPSEL3_Msk /*!< ADC channel 3 sampling time selection */
  850. #define ADC_SMPR_SMPSEL4_Pos (12U)
  851. #define ADC_SMPR_SMPSEL4_Msk (0x1UL << ADC_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */
  852. #define ADC_SMPR_SMPSEL4 ADC_SMPR_SMPSEL4_Msk /*!< ADC channel 4 sampling time selection */
  853. #define ADC_SMPR_SMPSEL5_Pos (13U)
  854. #define ADC_SMPR_SMPSEL5_Msk (0x1UL << ADC_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */
  855. #define ADC_SMPR_SMPSEL5 ADC_SMPR_SMPSEL5_Msk /*!< ADC channel 5 sampling time selection */
  856. #define ADC_SMPR_SMPSEL6_Pos (14U)
  857. #define ADC_SMPR_SMPSEL6_Msk (0x1UL << ADC_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */
  858. #define ADC_SMPR_SMPSEL6 ADC_SMPR_SMPSEL6_Msk /*!< ADC channel 6 sampling time selection */
  859. #define ADC_SMPR_SMPSEL7_Pos (15U)
  860. #define ADC_SMPR_SMPSEL7_Msk (0x1UL << ADC_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */
  861. #define ADC_SMPR_SMPSEL7 ADC_SMPR_SMPSEL7_Msk /*!< ADC channel 7 sampling time selection */
  862. #define ADC_SMPR_SMPSEL8_Pos (16U)
  863. #define ADC_SMPR_SMPSEL8_Msk (0x1UL << ADC_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */
  864. #define ADC_SMPR_SMPSEL8 ADC_SMPR_SMPSEL8_Msk /*!< ADC channel 8 sampling time selection */
  865. #define ADC_SMPR_SMPSEL9_Pos (17U)
  866. #define ADC_SMPR_SMPSEL9_Msk (0x1UL << ADC_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */
  867. #define ADC_SMPR_SMPSEL9 ADC_SMPR_SMPSEL9_Msk /*!< ADC channel 9 sampling time selection */
  868. #define ADC_SMPR_SMPSEL10_Pos (18U)
  869. #define ADC_SMPR_SMPSEL10_Msk (0x1UL << ADC_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */
  870. #define ADC_SMPR_SMPSEL10 ADC_SMPR_SMPSEL10_Msk /*!< ADC channel 10 sampling time selection */
  871. #define ADC_SMPR_SMPSEL11_Pos (19U)
  872. #define ADC_SMPR_SMPSEL11_Msk (0x1UL << ADC_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */
  873. #define ADC_SMPR_SMPSEL11 ADC_SMPR_SMPSEL11_Msk /*!< ADC channel 11 sampling time selection */
  874. #define ADC_SMPR_SMPSEL12_Pos (20U)
  875. #define ADC_SMPR_SMPSEL12_Msk (0x1UL << ADC_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */
  876. #define ADC_SMPR_SMPSEL12 ADC_SMPR_SMPSEL12_Msk /*!< ADC channel 12 sampling time selection */
  877. #define ADC_SMPR_SMPSEL13_Pos (21U)
  878. #define ADC_SMPR_SMPSEL13_Msk (0x1UL << ADC_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */
  879. #define ADC_SMPR_SMPSEL13 ADC_SMPR_SMPSEL13_Msk /*!< ADC channel 13 sampling time selection */
  880. #define ADC_SMPR_SMPSEL14_Pos (22U)
  881. #define ADC_SMPR_SMPSEL14_Msk (0x1UL << ADC_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */
  882. #define ADC_SMPR_SMPSEL14 ADC_SMPR_SMPSEL14_Msk /*!< ADC channel 14 sampling time selection */
  883. #define ADC_SMPR_SMPSEL15_Pos (23U)
  884. #define ADC_SMPR_SMPSEL15_Msk (0x1UL << ADC_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */
  885. #define ADC_SMPR_SMPSEL15 ADC_SMPR_SMPSEL15_Msk /*!< ADC channel 15 sampling time selection */
  886. #define ADC_SMPR_SMPSEL16_Pos (24U)
  887. #define ADC_SMPR_SMPSEL16_Msk (0x1UL << ADC_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */
  888. #define ADC_SMPR_SMPSEL16 ADC_SMPR_SMPSEL16_Msk /*!< ADC channel 16 sampling time selection */
  889. #define ADC_SMPR_SMPSEL17_Pos (25U)
  890. #define ADC_SMPR_SMPSEL17_Msk (0x1UL << ADC_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */
  891. #define ADC_SMPR_SMPSEL17 ADC_SMPR_SMPSEL17_Msk /*!< ADC channel 17 sampling time selection */
  892. #define ADC_SMPR_SMPSEL18_Pos (26U)
  893. #define ADC_SMPR_SMPSEL18_Msk (0x1UL << ADC_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */
  894. #define ADC_SMPR_SMPSEL18 ADC_SMPR_SMPSEL18_Msk /*!< ADC channel 18 sampling time selection */
  895. /******************** Bit definition for ADC_TR1 register *******************/
  896. #define ADC_TR1_LT1_Pos (0U)
  897. #define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
  898. #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
  899. #define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
  900. #define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
  901. #define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
  902. #define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
  903. #define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
  904. #define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
  905. #define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
  906. #define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
  907. #define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
  908. #define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
  909. #define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
  910. #define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
  911. #define ADC_TR1_HT1_Pos (16U)
  912. #define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
  913. #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
  914. #define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
  915. #define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
  916. #define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
  917. #define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
  918. #define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
  919. #define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
  920. #define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
  921. #define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
  922. #define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
  923. #define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
  924. #define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
  925. #define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
  926. /******************** Bit definition for ADC_TR2 register *******************/
  927. #define ADC_TR2_LT2_Pos (0U)
  928. #define ADC_TR2_LT2_Msk (0xFFFUL << ADC_TR2_LT2_Pos) /*!< 0x00000FFF */
  929. #define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
  930. #define ADC_TR2_LT2_0 (0x001UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
  931. #define ADC_TR2_LT2_1 (0x002UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
  932. #define ADC_TR2_LT2_2 (0x004UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
  933. #define ADC_TR2_LT2_3 (0x008UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
  934. #define ADC_TR2_LT2_4 (0x010UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
  935. #define ADC_TR2_LT2_5 (0x020UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
  936. #define ADC_TR2_LT2_6 (0x040UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
  937. #define ADC_TR2_LT2_7 (0x080UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
  938. #define ADC_TR2_LT2_8 (0x100UL << ADC_TR2_LT2_Pos) /*!< 0x00000100 */
  939. #define ADC_TR2_LT2_9 (0x200UL << ADC_TR2_LT2_Pos) /*!< 0x00000200 */
  940. #define ADC_TR2_LT2_10 (0x400UL << ADC_TR2_LT2_Pos) /*!< 0x00000400 */
  941. #define ADC_TR2_LT2_11 (0x800UL << ADC_TR2_LT2_Pos) /*!< 0x00000800 */
  942. #define ADC_TR2_HT2_Pos (16U)
  943. #define ADC_TR2_HT2_Msk (0xFFFUL << ADC_TR2_HT2_Pos) /*!< 0x0FFF0000 */
  944. #define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
  945. #define ADC_TR2_HT2_0 (0x001UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
  946. #define ADC_TR2_HT2_1 (0x002UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
  947. #define ADC_TR2_HT2_2 (0x004UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
  948. #define ADC_TR2_HT2_3 (0x008UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
  949. #define ADC_TR2_HT2_4 (0x010UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
  950. #define ADC_TR2_HT2_5 (0x020UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
  951. #define ADC_TR2_HT2_6 (0x040UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
  952. #define ADC_TR2_HT2_7 (0x080UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
  953. #define ADC_TR2_HT2_8 (0x100UL << ADC_TR2_HT2_Pos) /*!< 0x01000000 */
  954. #define ADC_TR2_HT2_9 (0x200UL << ADC_TR2_HT2_Pos) /*!< 0x02000000 */
  955. #define ADC_TR2_HT2_10 (0x400UL << ADC_TR2_HT2_Pos) /*!< 0x04000000 */
  956. #define ADC_TR2_HT2_11 (0x800UL << ADC_TR2_HT2_Pos) /*!< 0x08000000 */
  957. /******************** Bit definition for ADC_CHSELR register ****************/
  958. #define ADC_CHSELR_CHSEL_Pos (0U)
  959. #define ADC_CHSELR_CHSEL_Msk (0x7FFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
  960. #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
  961. #define ADC_CHSELR_CHSEL18_Pos (18U)
  962. #define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
  963. #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
  964. #define ADC_CHSELR_CHSEL17_Pos (17U)
  965. #define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
  966. #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
  967. #define ADC_CHSELR_CHSEL16_Pos (16U)
  968. #define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
  969. #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
  970. #define ADC_CHSELR_CHSEL15_Pos (15U)
  971. #define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
  972. #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
  973. #define ADC_CHSELR_CHSEL14_Pos (14U)
  974. #define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
  975. #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
  976. #define ADC_CHSELR_CHSEL13_Pos (13U)
  977. #define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
  978. #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
  979. #define ADC_CHSELR_CHSEL12_Pos (12U)
  980. #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
  981. #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
  982. #define ADC_CHSELR_CHSEL11_Pos (11U)
  983. #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
  984. #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
  985. #define ADC_CHSELR_CHSEL10_Pos (10U)
  986. #define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
  987. #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
  988. #define ADC_CHSELR_CHSEL9_Pos (9U)
  989. #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
  990. #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
  991. #define ADC_CHSELR_CHSEL8_Pos (8U)
  992. #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
  993. #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
  994. #define ADC_CHSELR_CHSEL7_Pos (7U)
  995. #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
  996. #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
  997. #define ADC_CHSELR_CHSEL6_Pos (6U)
  998. #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
  999. #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
  1000. #define ADC_CHSELR_CHSEL5_Pos (5U)
  1001. #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
  1002. #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
  1003. #define ADC_CHSELR_CHSEL4_Pos (4U)
  1004. #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
  1005. #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
  1006. #define ADC_CHSELR_CHSEL3_Pos (3U)
  1007. #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
  1008. #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
  1009. #define ADC_CHSELR_CHSEL2_Pos (2U)
  1010. #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
  1011. #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
  1012. #define ADC_CHSELR_CHSEL1_Pos (1U)
  1013. #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
  1014. #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
  1015. #define ADC_CHSELR_CHSEL0_Pos (0U)
  1016. #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
  1017. #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
  1018. #define ADC_CHSELR_SQ_ALL_Pos (0U)
  1019. #define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
  1020. #define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
  1021. #define ADC_CHSELR_SQ8_Pos (28U)
  1022. #define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */
  1023. #define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
  1024. #define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */
  1025. #define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */
  1026. #define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */
  1027. #define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */
  1028. #define ADC_CHSELR_SQ7_Pos (24U)
  1029. #define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */
  1030. #define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
  1031. #define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */
  1032. #define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */
  1033. #define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */
  1034. #define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */
  1035. #define ADC_CHSELR_SQ6_Pos (20U)
  1036. #define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */
  1037. #define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
  1038. #define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */
  1039. #define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */
  1040. #define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */
  1041. #define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */
  1042. #define ADC_CHSELR_SQ5_Pos (16U)
  1043. #define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */
  1044. #define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
  1045. #define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */
  1046. #define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */
  1047. #define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */
  1048. #define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */
  1049. #define ADC_CHSELR_SQ4_Pos (12U)
  1050. #define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */
  1051. #define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
  1052. #define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */
  1053. #define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */
  1054. #define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */
  1055. #define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */
  1056. #define ADC_CHSELR_SQ3_Pos (8U)
  1057. #define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */
  1058. #define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
  1059. #define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */
  1060. #define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */
  1061. #define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */
  1062. #define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */
  1063. #define ADC_CHSELR_SQ2_Pos (4U)
  1064. #define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */
  1065. #define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
  1066. #define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */
  1067. #define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */
  1068. #define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */
  1069. #define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */
  1070. #define ADC_CHSELR_SQ1_Pos (0U)
  1071. #define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */
  1072. #define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
  1073. #define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */
  1074. #define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */
  1075. #define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */
  1076. #define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */
  1077. /******************** Bit definition for ADC_TR3 register *******************/
  1078. #define ADC_TR3_LT3_Pos (0U)
  1079. #define ADC_TR3_LT3_Msk (0xFFFUL << ADC_TR3_LT3_Pos) /*!< 0x00000FFF */
  1080. #define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
  1081. #define ADC_TR3_LT3_0 (0x001UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
  1082. #define ADC_TR3_LT3_1 (0x002UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
  1083. #define ADC_TR3_LT3_2 (0x004UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
  1084. #define ADC_TR3_LT3_3 (0x008UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
  1085. #define ADC_TR3_LT3_4 (0x010UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
  1086. #define ADC_TR3_LT3_5 (0x020UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
  1087. #define ADC_TR3_LT3_6 (0x040UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
  1088. #define ADC_TR3_LT3_7 (0x080UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
  1089. #define ADC_TR3_LT3_8 (0x100UL << ADC_TR3_LT3_Pos) /*!< 0x00000100 */
  1090. #define ADC_TR3_LT3_9 (0x200UL << ADC_TR3_LT3_Pos) /*!< 0x00000200 */
  1091. #define ADC_TR3_LT3_10 (0x400UL << ADC_TR3_LT3_Pos) /*!< 0x00000400 */
  1092. #define ADC_TR3_LT3_11 (0x800UL << ADC_TR3_LT3_Pos) /*!< 0x00000800 */
  1093. #define ADC_TR3_HT3_Pos (16U)
  1094. #define ADC_TR3_HT3_Msk (0xFFFUL << ADC_TR3_HT3_Pos) /*!< 0x0FFF0000 */
  1095. #define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
  1096. #define ADC_TR3_HT3_0 (0x001UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
  1097. #define ADC_TR3_HT3_1 (0x002UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
  1098. #define ADC_TR3_HT3_2 (0x004UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
  1099. #define ADC_TR3_HT3_3 (0x008UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
  1100. #define ADC_TR3_HT3_4 (0x010UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
  1101. #define ADC_TR3_HT3_5 (0x020UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
  1102. #define ADC_TR3_HT3_6 (0x040UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
  1103. #define ADC_TR3_HT3_7 (0x080UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
  1104. #define ADC_TR3_HT3_8 (0x100UL << ADC_TR3_HT3_Pos) /*!< 0x01000000 */
  1105. #define ADC_TR3_HT3_9 (0x200UL << ADC_TR3_HT3_Pos) /*!< 0x02000000 */
  1106. #define ADC_TR3_HT3_10 (0x400UL << ADC_TR3_HT3_Pos) /*!< 0x04000000 */
  1107. #define ADC_TR3_HT3_11 (0x800UL << ADC_TR3_HT3_Pos) /*!< 0x08000000 */
  1108. /******************** Bit definition for ADC_DR register ********************/
  1109. #define ADC_DR_DATA_Pos (0U)
  1110. #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
  1111. #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
  1112. #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */
  1113. #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */
  1114. #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */
  1115. #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */
  1116. #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */
  1117. #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */
  1118. #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */
  1119. #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */
  1120. #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */
  1121. #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */
  1122. #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */
  1123. #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */
  1124. #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */
  1125. #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */
  1126. #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */
  1127. #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */
  1128. /******************** Bit definition for ADC_AWD2CR register ****************/
  1129. #define ADC_AWD2CR_AWD2CH_Pos (0U)
  1130. #define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
  1131. #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
  1132. #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
  1133. #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
  1134. #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
  1135. #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
  1136. #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
  1137. #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
  1138. #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
  1139. #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
  1140. #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
  1141. #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
  1142. #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
  1143. #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
  1144. #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
  1145. #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
  1146. #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
  1147. #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
  1148. #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
  1149. #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
  1150. #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
  1151. /******************** Bit definition for ADC_AWD3CR register ****************/
  1152. #define ADC_AWD3CR_AWD3CH_Pos (0U)
  1153. #define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
  1154. #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
  1155. #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
  1156. #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
  1157. #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
  1158. #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
  1159. #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
  1160. #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
  1161. #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
  1162. #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
  1163. #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
  1164. #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
  1165. #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
  1166. #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
  1167. #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
  1168. #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
  1169. #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
  1170. #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
  1171. #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
  1172. #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
  1173. #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
  1174. /******************** Bit definition for ADC_CALFACT register ***************/
  1175. #define ADC_CALFACT_CALFACT_Pos (0U)
  1176. #define ADC_CALFACT_CALFACT_Msk (0x7FUL << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */
  1177. #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */
  1178. #define ADC_CALFACT_CALFACT_0 (0x01UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000001 */
  1179. #define ADC_CALFACT_CALFACT_1 (0x02UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000002 */
  1180. #define ADC_CALFACT_CALFACT_2 (0x04UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000004 */
  1181. #define ADC_CALFACT_CALFACT_3 (0x08UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000008 */
  1182. #define ADC_CALFACT_CALFACT_4 (0x10UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000010 */
  1183. #define ADC_CALFACT_CALFACT_5 (0x20UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000020 */
  1184. #define ADC_CALFACT_CALFACT_6 (0x40UL << ADC_CALFACT_CALFACT_Pos) /*!< 0x00000040 */
  1185. /************************* ADC Common registers *****************************/
  1186. /******************** Bit definition for ADC_CCR register *******************/
  1187. #define ADC_CCR_PRESC_Pos (18U)
  1188. #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
  1189. #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
  1190. #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
  1191. #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
  1192. #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
  1193. #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
  1194. #define ADC_CCR_VREFEN_Pos (22U)
  1195. #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
  1196. #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
  1197. #define ADC_CCR_TSEN_Pos (23U)
  1198. #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
  1199. #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
  1200. #define ADC_CCR_VBATEN_Pos (24U)
  1201. #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
  1202. #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
  1203. /* Legacy */
  1204. #define ADC_CCR_LFMEN_Pos (25U)
  1205. #define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */
  1206. #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Legacy feature, useless on STM32G0 (ADC common clock low frequency mode is automatically managed by ADC peripheral on STM32G0) */
  1207. /******************************************************************************/
  1208. /* */
  1209. /* CRC calculation unit */
  1210. /* */
  1211. /******************************************************************************/
  1212. /******************* Bit definition for CRC_DR register *********************/
  1213. #define CRC_DR_DR_Pos (0U)
  1214. #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
  1215. #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
  1216. /******************* Bit definition for CRC_IDR register ********************/
  1217. #define CRC_IDR_IDR_Pos (0U)
  1218. #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
  1219. #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */
  1220. /******************** Bit definition for CRC_CR register ********************/
  1221. #define CRC_CR_RESET_Pos (0U)
  1222. #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
  1223. #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
  1224. #define CRC_CR_POLYSIZE_Pos (3U)
  1225. #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
  1226. #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
  1227. #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
  1228. #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
  1229. #define CRC_CR_REV_IN_Pos (5U)
  1230. #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
  1231. #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
  1232. #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
  1233. #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
  1234. #define CRC_CR_REV_OUT_Pos (7U)
  1235. #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
  1236. #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
  1237. /******************* Bit definition for CRC_INIT register *******************/
  1238. #define CRC_INIT_INIT_Pos (0U)
  1239. #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
  1240. #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
  1241. /******************* Bit definition for CRC_POL register ********************/
  1242. #define CRC_POL_POL_Pos (0U)
  1243. #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
  1244. #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
  1245. /******************************************************************************/
  1246. /* */
  1247. /* Debug MCU */
  1248. /* */
  1249. /******************************************************************************/
  1250. /******************************************************************************/
  1251. /* */
  1252. /* DMA Controller (DMA) */
  1253. /* */
  1254. /******************************************************************************/
  1255. /******************* Bit definition for DMA_ISR register ********************/
  1256. #define DMA_ISR_GIF1_Pos (0U)
  1257. #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
  1258. #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
  1259. #define DMA_ISR_TCIF1_Pos (1U)
  1260. #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
  1261. #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
  1262. #define DMA_ISR_HTIF1_Pos (2U)
  1263. #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
  1264. #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
  1265. #define DMA_ISR_TEIF1_Pos (3U)
  1266. #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
  1267. #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
  1268. #define DMA_ISR_GIF2_Pos (4U)
  1269. #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
  1270. #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
  1271. #define DMA_ISR_TCIF2_Pos (5U)
  1272. #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
  1273. #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
  1274. #define DMA_ISR_HTIF2_Pos (6U)
  1275. #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
  1276. #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
  1277. #define DMA_ISR_TEIF2_Pos (7U)
  1278. #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
  1279. #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
  1280. #define DMA_ISR_GIF3_Pos (8U)
  1281. #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
  1282. #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
  1283. #define DMA_ISR_TCIF3_Pos (9U)
  1284. #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
  1285. #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
  1286. #define DMA_ISR_HTIF3_Pos (10U)
  1287. #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
  1288. #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
  1289. #define DMA_ISR_TEIF3_Pos (11U)
  1290. #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
  1291. #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
  1292. #define DMA_ISR_GIF4_Pos (12U)
  1293. #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
  1294. #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
  1295. #define DMA_ISR_TCIF4_Pos (13U)
  1296. #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
  1297. #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
  1298. #define DMA_ISR_HTIF4_Pos (14U)
  1299. #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
  1300. #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
  1301. #define DMA_ISR_TEIF4_Pos (15U)
  1302. #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
  1303. #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
  1304. #define DMA_ISR_GIF5_Pos (16U)
  1305. #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
  1306. #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
  1307. #define DMA_ISR_TCIF5_Pos (17U)
  1308. #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
  1309. #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
  1310. #define DMA_ISR_HTIF5_Pos (18U)
  1311. #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
  1312. #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
  1313. #define DMA_ISR_TEIF5_Pos (19U)
  1314. #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
  1315. #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
  1316. #define DMA_ISR_GIF6_Pos (20U)
  1317. #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
  1318. #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
  1319. #define DMA_ISR_TCIF6_Pos (21U)
  1320. #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
  1321. #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
  1322. #define DMA_ISR_HTIF6_Pos (22U)
  1323. #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
  1324. #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
  1325. #define DMA_ISR_TEIF6_Pos (23U)
  1326. #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
  1327. #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
  1328. #define DMA_ISR_GIF7_Pos (24U)
  1329. #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
  1330. #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
  1331. #define DMA_ISR_TCIF7_Pos (25U)
  1332. #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
  1333. #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
  1334. #define DMA_ISR_HTIF7_Pos (26U)
  1335. #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
  1336. #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
  1337. #define DMA_ISR_TEIF7_Pos (27U)
  1338. #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
  1339. #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
  1340. /******************* Bit definition for DMA_IFCR register *******************/
  1341. #define DMA_IFCR_CGIF1_Pos (0U)
  1342. #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
  1343. #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
  1344. #define DMA_IFCR_CTCIF1_Pos (1U)
  1345. #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
  1346. #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
  1347. #define DMA_IFCR_CHTIF1_Pos (2U)
  1348. #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
  1349. #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
  1350. #define DMA_IFCR_CTEIF1_Pos (3U)
  1351. #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
  1352. #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
  1353. #define DMA_IFCR_CGIF2_Pos (4U)
  1354. #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
  1355. #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
  1356. #define DMA_IFCR_CTCIF2_Pos (5U)
  1357. #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
  1358. #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
  1359. #define DMA_IFCR_CHTIF2_Pos (6U)
  1360. #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
  1361. #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
  1362. #define DMA_IFCR_CTEIF2_Pos (7U)
  1363. #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
  1364. #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
  1365. #define DMA_IFCR_CGIF3_Pos (8U)
  1366. #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
  1367. #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
  1368. #define DMA_IFCR_CTCIF3_Pos (9U)
  1369. #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
  1370. #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
  1371. #define DMA_IFCR_CHTIF3_Pos (10U)
  1372. #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
  1373. #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
  1374. #define DMA_IFCR_CTEIF3_Pos (11U)
  1375. #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
  1376. #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
  1377. #define DMA_IFCR_CGIF4_Pos (12U)
  1378. #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
  1379. #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
  1380. #define DMA_IFCR_CTCIF4_Pos (13U)
  1381. #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
  1382. #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
  1383. #define DMA_IFCR_CHTIF4_Pos (14U)
  1384. #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
  1385. #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
  1386. #define DMA_IFCR_CTEIF4_Pos (15U)
  1387. #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
  1388. #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
  1389. #define DMA_IFCR_CGIF5_Pos (16U)
  1390. #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
  1391. #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
  1392. #define DMA_IFCR_CTCIF5_Pos (17U)
  1393. #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
  1394. #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
  1395. #define DMA_IFCR_CHTIF5_Pos (18U)
  1396. #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
  1397. #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
  1398. #define DMA_IFCR_CTEIF5_Pos (19U)
  1399. #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
  1400. #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
  1401. #define DMA_IFCR_CGIF6_Pos (20U)
  1402. #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
  1403. #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
  1404. #define DMA_IFCR_CTCIF6_Pos (21U)
  1405. #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
  1406. #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
  1407. #define DMA_IFCR_CHTIF6_Pos (22U)
  1408. #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
  1409. #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
  1410. #define DMA_IFCR_CTEIF6_Pos (23U)
  1411. #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
  1412. #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
  1413. #define DMA_IFCR_CGIF7_Pos (24U)
  1414. #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
  1415. #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
  1416. #define DMA_IFCR_CTCIF7_Pos (25U)
  1417. #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
  1418. #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
  1419. #define DMA_IFCR_CHTIF7_Pos (26U)
  1420. #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
  1421. #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
  1422. #define DMA_IFCR_CTEIF7_Pos (27U)
  1423. #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
  1424. #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
  1425. /******************* Bit definition for DMA_CCR register ********************/
  1426. #define DMA_CCR_EN_Pos (0U)
  1427. #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
  1428. #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
  1429. #define DMA_CCR_TCIE_Pos (1U)
  1430. #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
  1431. #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
  1432. #define DMA_CCR_HTIE_Pos (2U)
  1433. #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
  1434. #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
  1435. #define DMA_CCR_TEIE_Pos (3U)
  1436. #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
  1437. #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
  1438. #define DMA_CCR_DIR_Pos (4U)
  1439. #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
  1440. #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
  1441. #define DMA_CCR_CIRC_Pos (5U)
  1442. #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
  1443. #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
  1444. #define DMA_CCR_PINC_Pos (6U)
  1445. #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
  1446. #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
  1447. #define DMA_CCR_MINC_Pos (7U)
  1448. #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
  1449. #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
  1450. #define DMA_CCR_PSIZE_Pos (8U)
  1451. #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
  1452. #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
  1453. #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
  1454. #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
  1455. #define DMA_CCR_MSIZE_Pos (10U)
  1456. #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
  1457. #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
  1458. #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
  1459. #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
  1460. #define DMA_CCR_PL_Pos (12U)
  1461. #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
  1462. #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
  1463. #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
  1464. #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
  1465. #define DMA_CCR_MEM2MEM_Pos (14U)
  1466. #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
  1467. #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
  1468. /****************** Bit definition for DMA_CNDTR register *******************/
  1469. #define DMA_CNDTR_NDT_Pos (0U)
  1470. #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
  1471. #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
  1472. /****************** Bit definition for DMA_CPAR register ********************/
  1473. #define DMA_CPAR_PA_Pos (0U)
  1474. #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
  1475. #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
  1476. /****************** Bit definition for DMA_CMAR register ********************/
  1477. #define DMA_CMAR_MA_Pos (0U)
  1478. #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
  1479. #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
  1480. /******************************************************************************/
  1481. /* */
  1482. /* DMAMUX Controller */
  1483. /* */
  1484. /******************************************************************************/
  1485. /******************** Bits definition for DMAMUX_CxCR register **************/
  1486. #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
  1487. #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
  1488. #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA Request ID */
  1489. #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
  1490. #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
  1491. #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
  1492. #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
  1493. #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
  1494. #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
  1495. #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
  1496. #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
  1497. #define DMAMUX_CxCR_SOIE_Pos (8U)
  1498. #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
  1499. #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchro overrun interrupt enable */
  1500. #define DMAMUX_CxCR_EGE_Pos (9U)
  1501. #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
  1502. #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation interrupt enable */
  1503. #define DMAMUX_CxCR_SE_Pos (16U)
  1504. #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
  1505. #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
  1506. #define DMAMUX_CxCR_SPOL_Pos (17U)
  1507. #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
  1508. #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
  1509. #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
  1510. #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
  1511. #define DMAMUX_CxCR_NBREQ_Pos (19U)
  1512. #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
  1513. #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of request */
  1514. #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
  1515. #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
  1516. #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
  1517. #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
  1518. #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
  1519. #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
  1520. #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
  1521. #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization ID */
  1522. #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
  1523. #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
  1524. #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
  1525. #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
  1526. #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
  1527. /******************* Bits definition for DMAMUX_CSR register **************/
  1528. #define DMAMUX_CSR_SOF0_Pos (0U)
  1529. #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
  1530. #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Synchronization Overrun Flag 0 */
  1531. #define DMAMUX_CSR_SOF1_Pos (1U)
  1532. #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
  1533. #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Synchronization Overrun Flag 1 */
  1534. #define DMAMUX_CSR_SOF2_Pos (2U)
  1535. #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
  1536. #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Synchronization Overrun Flag 2 */
  1537. #define DMAMUX_CSR_SOF3_Pos (3U)
  1538. #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
  1539. #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Synchronization Overrun Flag 3 */
  1540. #define DMAMUX_CSR_SOF4_Pos (4U)
  1541. #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
  1542. #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Synchronization Overrun Flag 4 */
  1543. #define DMAMUX_CSR_SOF5_Pos (5U)
  1544. #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
  1545. #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Synchronization Overrun Flag 5 */
  1546. #define DMAMUX_CSR_SOF6_Pos (6U)
  1547. #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
  1548. #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Synchronization Overrun Flag 6 */
  1549. /******************** Bits definition for DMAMUX_CFR register **************/
  1550. #define DMAMUX_CFR_CSOF0_Pos (0U)
  1551. #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
  1552. #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Clear Overrun Flag 0 */
  1553. #define DMAMUX_CFR_CSOF1_Pos (1U)
  1554. #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
  1555. #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Clear Overrun Flag 1 */
  1556. #define DMAMUX_CFR_CSOF2_Pos (2U)
  1557. #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
  1558. #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Clear Overrun Flag 2 */
  1559. #define DMAMUX_CFR_CSOF3_Pos (3U)
  1560. #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
  1561. #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Clear Overrun Flag 3 */
  1562. #define DMAMUX_CFR_CSOF4_Pos (4U)
  1563. #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
  1564. #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Clear Overrun Flag 4 */
  1565. #define DMAMUX_CFR_CSOF5_Pos (5U)
  1566. #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
  1567. #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Clear Overrun Flag 5 */
  1568. #define DMAMUX_CFR_CSOF6_Pos (6U)
  1569. #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
  1570. #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Clear Overrun Flag 6 */
  1571. /******************** Bits definition for DMAMUX_RGxCR register ************/
  1572. #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
  1573. #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
  1574. #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal ID */
  1575. #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
  1576. #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
  1577. #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
  1578. #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
  1579. #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
  1580. #define DMAMUX_RGxCR_OIE_Pos (8U)
  1581. #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
  1582. #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Overrun interrupt enable */
  1583. #define DMAMUX_RGxCR_GE_Pos (16U)
  1584. #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
  1585. #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< Generation enable */
  1586. #define DMAMUX_RGxCR_GPOL_Pos (17U)
  1587. #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
  1588. #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< Generation polarity */
  1589. #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
  1590. #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
  1591. #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
  1592. #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
  1593. #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of request */
  1594. #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
  1595. #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
  1596. #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
  1597. #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
  1598. #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
  1599. /******************** Bits definition for DMAMUX_RGSR register **************/
  1600. #define DMAMUX_RGSR_OF0_Pos (0U)
  1601. #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
  1602. #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Overrun flag 0 */
  1603. #define DMAMUX_RGSR_OF1_Pos (1U)
  1604. #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
  1605. #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Overrun flag 1 */
  1606. #define DMAMUX_RGSR_OF2_Pos (2U)
  1607. #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
  1608. #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Overrun flag 2 */
  1609. #define DMAMUX_RGSR_OF3_Pos (3U)
  1610. #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
  1611. #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Overrun flag 3 */
  1612. /******************** Bits definition for DMAMUX_RGCFR register **************/
  1613. #define DMAMUX_RGCFR_COF0_Pos (0U)
  1614. #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
  1615. #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Clear Overrun flag 0 */
  1616. #define DMAMUX_RGCFR_COF1_Pos (1U)
  1617. #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
  1618. #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Clear Overrun flag 1 */
  1619. #define DMAMUX_RGCFR_COF2_Pos (2U)
  1620. #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
  1621. #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Clear Overrun flag 2 */
  1622. #define DMAMUX_RGCFR_COF3_Pos (3U)
  1623. #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
  1624. #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Clear Overrun flag 3 */
  1625. /******************************************************************************/
  1626. /* */
  1627. /* External Interrupt/Event Controller */
  1628. /* */
  1629. /******************************************************************************/
  1630. /****************** Bit definition for EXTI_RTSR1 register ******************/
  1631. #define EXTI_RTSR1_RT0_Pos (0U)
  1632. #define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
  1633. #define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger configuration for input line 0 */
  1634. #define EXTI_RTSR1_RT1_Pos (1U)
  1635. #define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
  1636. #define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger configuration for input line 1 */
  1637. #define EXTI_RTSR1_RT2_Pos (2U)
  1638. #define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
  1639. #define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger configuration for input line 2 */
  1640. #define EXTI_RTSR1_RT3_Pos (3U)
  1641. #define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
  1642. #define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger configuration for input line 3 */
  1643. #define EXTI_RTSR1_RT4_Pos (4U)
  1644. #define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
  1645. #define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger configuration for input line 4 */
  1646. #define EXTI_RTSR1_RT5_Pos (5U)
  1647. #define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
  1648. #define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger configuration for input line 5 */
  1649. #define EXTI_RTSR1_RT6_Pos (6U)
  1650. #define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
  1651. #define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger configuration for input line 6 */
  1652. #define EXTI_RTSR1_RT7_Pos (7U)
  1653. #define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
  1654. #define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger configuration for input line 7 */
  1655. #define EXTI_RTSR1_RT8_Pos (8U)
  1656. #define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
  1657. #define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger configuration for input line 8 */
  1658. #define EXTI_RTSR1_RT9_Pos (9U)
  1659. #define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
  1660. #define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger configuration for input line 9 */
  1661. #define EXTI_RTSR1_RT10_Pos (10U)
  1662. #define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
  1663. #define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger configuration for input line 10 */
  1664. #define EXTI_RTSR1_RT11_Pos (11U)
  1665. #define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
  1666. #define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger configuration for input line 11 */
  1667. #define EXTI_RTSR1_RT12_Pos (12U)
  1668. #define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
  1669. #define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger configuration for input line 12 */
  1670. #define EXTI_RTSR1_RT13_Pos (13U)
  1671. #define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
  1672. #define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger configuration for input line 13 */
  1673. #define EXTI_RTSR1_RT14_Pos (14U)
  1674. #define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
  1675. #define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger configuration for input line 14 */
  1676. #define EXTI_RTSR1_RT15_Pos (15U)
  1677. #define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
  1678. #define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger configuration for input line 15 */
  1679. #define EXTI_RTSR1_RT16_Pos (16U)
  1680. #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
  1681. #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger configuration for input line 16 */
  1682. /****************** Bit definition for EXTI_FTSR1 register ******************/
  1683. #define EXTI_FTSR1_FT0_Pos (0U)
  1684. #define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
  1685. #define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger configuration for input line 0 */
  1686. #define EXTI_FTSR1_FT1_Pos (1U)
  1687. #define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
  1688. #define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger configuration for input line 1 */
  1689. #define EXTI_FTSR1_FT2_Pos (2U)
  1690. #define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
  1691. #define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger configuration for input line 2 */
  1692. #define EXTI_FTSR1_FT3_Pos (3U)
  1693. #define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
  1694. #define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger configuration for input line 3 */
  1695. #define EXTI_FTSR1_FT4_Pos (4U)
  1696. #define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
  1697. #define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger configuration for input line 4 */
  1698. #define EXTI_FTSR1_FT5_Pos (5U)
  1699. #define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
  1700. #define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger configuration for input line 5 */
  1701. #define EXTI_FTSR1_FT6_Pos (6U)
  1702. #define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
  1703. #define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger configuration for input line 6 */
  1704. #define EXTI_FTSR1_FT7_Pos (7U)
  1705. #define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
  1706. #define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger configuration for input line 7 */
  1707. #define EXTI_FTSR1_FT8_Pos (8U)
  1708. #define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
  1709. #define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger configuration for input line 8 */
  1710. #define EXTI_FTSR1_FT9_Pos (9U)
  1711. #define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
  1712. #define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger configuration for input line 9 */
  1713. #define EXTI_FTSR1_FT10_Pos (10U)
  1714. #define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
  1715. #define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger configuration for input line 10 */
  1716. #define EXTI_FTSR1_FT11_Pos (11U)
  1717. #define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
  1718. #define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger configuration for input line 11 */
  1719. #define EXTI_FTSR1_FT12_Pos (12U)
  1720. #define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
  1721. #define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger configuration for input line 12 */
  1722. #define EXTI_FTSR1_FT13_Pos (13U)
  1723. #define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
  1724. #define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger configuration for input line 13 */
  1725. #define EXTI_FTSR1_FT14_Pos (14U)
  1726. #define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
  1727. #define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger configuration for input line 14 */
  1728. #define EXTI_FTSR1_FT15_Pos (15U)
  1729. #define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
  1730. #define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger configuration for input line 15 */
  1731. #define EXTI_FTSR1_FT16_Pos (16U)
  1732. #define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
  1733. #define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger configuration for input line 16 */
  1734. /****************** Bit definition for EXTI_SWIER1 register *****************/
  1735. #define EXTI_SWIER1_SWI0_Pos (0U)
  1736. #define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
  1737. #define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
  1738. #define EXTI_SWIER1_SWI1_Pos (1U)
  1739. #define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
  1740. #define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
  1741. #define EXTI_SWIER1_SWI2_Pos (2U)
  1742. #define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
  1743. #define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
  1744. #define EXTI_SWIER1_SWI3_Pos (3U)
  1745. #define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
  1746. #define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
  1747. #define EXTI_SWIER1_SWI4_Pos (4U)
  1748. #define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
  1749. #define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
  1750. #define EXTI_SWIER1_SWI5_Pos (5U)
  1751. #define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
  1752. #define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
  1753. #define EXTI_SWIER1_SWI6_Pos (6U)
  1754. #define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
  1755. #define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
  1756. #define EXTI_SWIER1_SWI7_Pos (7U)
  1757. #define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
  1758. #define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
  1759. #define EXTI_SWIER1_SWI8_Pos (8U)
  1760. #define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
  1761. #define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
  1762. #define EXTI_SWIER1_SWI9_Pos (9U)
  1763. #define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
  1764. #define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
  1765. #define EXTI_SWIER1_SWI10_Pos (10U)
  1766. #define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
  1767. #define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
  1768. #define EXTI_SWIER1_SWI11_Pos (11U)
  1769. #define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
  1770. #define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
  1771. #define EXTI_SWIER1_SWI12_Pos (12U)
  1772. #define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
  1773. #define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
  1774. #define EXTI_SWIER1_SWI13_Pos (13U)
  1775. #define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
  1776. #define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
  1777. #define EXTI_SWIER1_SWI14_Pos (14U)
  1778. #define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
  1779. #define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
  1780. #define EXTI_SWIER1_SWI15_Pos (15U)
  1781. #define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
  1782. #define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
  1783. #define EXTI_SWIER1_SWI16_Pos (16U)
  1784. #define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
  1785. #define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
  1786. /******************* Bit definition for EXTI_RPR1 register ******************/
  1787. #define EXTI_RPR1_RPIF0_Pos (0U)
  1788. #define EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) /*!< 0x00000001 */
  1789. #define EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk /*!< Rising Pending Interrupt Flag on line 0 */
  1790. #define EXTI_RPR1_RPIF1_Pos (1U)
  1791. #define EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) /*!< 0x00000002 */
  1792. #define EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk /*!< Rising Pending Interrupt Flag on line 1 */
  1793. #define EXTI_RPR1_RPIF2_Pos (2U)
  1794. #define EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) /*!< 0x00000004 */
  1795. #define EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk /*!< Rising Pending Interrupt Flag on line 2 */
  1796. #define EXTI_RPR1_RPIF3_Pos (3U)
  1797. #define EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) /*!< 0x00000008 */
  1798. #define EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk /*!< Rising Pending Interrupt Flag on line 3 */
  1799. #define EXTI_RPR1_RPIF4_Pos (4U)
  1800. #define EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) /*!< 0x00000010 */
  1801. #define EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk /*!< Rising Pending Interrupt Flag on line 4 */
  1802. #define EXTI_RPR1_RPIF5_Pos (5U)
  1803. #define EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) /*!< 0x00000020 */
  1804. #define EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk /*!< Rising Pending Interrupt Flag on line 5 */
  1805. #define EXTI_RPR1_RPIF6_Pos (6U)
  1806. #define EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) /*!< 0x00000040 */
  1807. #define EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk /*!< Rising Pending Interrupt Flag on line 6 */
  1808. #define EXTI_RPR1_RPIF7_Pos (7U)
  1809. #define EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) /*!< 0x00000080 */
  1810. #define EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk /*!< Rising Pending Interrupt Flag on line 7 */
  1811. #define EXTI_RPR1_RPIF8_Pos (8U)
  1812. #define EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) /*!< 0x00000100 */
  1813. #define EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk /*!< Rising Pending Interrupt Flag on line 8 */
  1814. #define EXTI_RPR1_RPIF9_Pos (9U)
  1815. #define EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) /*!< 0x00000200 */
  1816. #define EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk /*!< Rising Pending Interrupt Flag on line 9 */
  1817. #define EXTI_RPR1_RPIF10_Pos (10U)
  1818. #define EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) /*!< 0x00000400 */
  1819. #define EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk /*!< Rising Pending Interrupt Flag on line 10 */
  1820. #define EXTI_RPR1_RPIF11_Pos (11U)
  1821. #define EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) /*!< 0x00000800 */
  1822. #define EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk /*!< Rising Pending Interrupt Flag on line 11 */
  1823. #define EXTI_RPR1_RPIF12_Pos (12U)
  1824. #define EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) /*!< 0x00001000 */
  1825. #define EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk /*!< Rising Pending Interrupt Flag on line 12 */
  1826. #define EXTI_RPR1_RPIF13_Pos (13U)
  1827. #define EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) /*!< 0x00002000 */
  1828. #define EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk /*!< Rising Pending Interrupt Flag on line 13 */
  1829. #define EXTI_RPR1_RPIF14_Pos (14U)
  1830. #define EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) /*!< 0x00004000 */
  1831. #define EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk /*!< Rising Pending Interrupt Flag on line 14 */
  1832. #define EXTI_RPR1_RPIF15_Pos (15U)
  1833. #define EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) /*!< 0x00008000 */
  1834. #define EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk /*!< Rising Pending Interrupt Flag on line 15 */
  1835. #define EXTI_RPR1_RPIF16_Pos (16U)
  1836. #define EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) /*!< 0x00010000 */
  1837. #define EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk /*!< Rising Pending Interrupt Flag on line 16 */
  1838. /******************* Bit definition for EXTI_FPR1 register ******************/
  1839. #define EXTI_FPR1_FPIF0_Pos (0U)
  1840. #define EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) /*!< 0x00000001 */
  1841. #define EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk /*!< Falling Pending Interrupt Flag on line 0 */
  1842. #define EXTI_FPR1_FPIF1_Pos (1U)
  1843. #define EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) /*!< 0x00000002 */
  1844. #define EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk /*!< Falling Pending Interrupt Flag on line 1 */
  1845. #define EXTI_FPR1_FPIF2_Pos (2U)
  1846. #define EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) /*!< 0x00000004 */
  1847. #define EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk /*!< Falling Pending Interrupt Flag on line 2 */
  1848. #define EXTI_FPR1_FPIF3_Pos (3U)
  1849. #define EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) /*!< 0x00000008 */
  1850. #define EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk /*!< Falling Pending Interrupt Flag on line 3 */
  1851. #define EXTI_FPR1_FPIF4_Pos (4U)
  1852. #define EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) /*!< 0x00000010 */
  1853. #define EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk /*!< Falling Pending Interrupt Flag on line 4 */
  1854. #define EXTI_FPR1_FPIF5_Pos (5U)
  1855. #define EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) /*!< 0x00000020 */
  1856. #define EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk /*!< Falling Pending Interrupt Flag on line 5 */
  1857. #define EXTI_FPR1_FPIF6_Pos (6U)
  1858. #define EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) /*!< 0x00000040 */
  1859. #define EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk /*!< Falling Pending Interrupt Flag on line 6 */
  1860. #define EXTI_FPR1_FPIF7_Pos (7U)
  1861. #define EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) /*!< 0x00000080 */
  1862. #define EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk /*!< Falling Pending Interrupt Flag on line 7 */
  1863. #define EXTI_FPR1_FPIF8_Pos (8U)
  1864. #define EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) /*!< 0x00000100 */
  1865. #define EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk /*!< Falling Pending Interrupt Flag on line 8 */
  1866. #define EXTI_FPR1_FPIF9_Pos (9U)
  1867. #define EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) /*!< 0x00000200 */
  1868. #define EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk /*!< Falling Pending Interrupt Flag on line 9 */
  1869. #define EXTI_FPR1_FPIF10_Pos (10U)
  1870. #define EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) /*!< 0x00000400 */
  1871. #define EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk /*!< Falling Pending Interrupt Flag on line 10 */
  1872. #define EXTI_FPR1_FPIF11_Pos (11U)
  1873. #define EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) /*!< 0x00000800 */
  1874. #define EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk /*!< Falling Pending Interrupt Flag on line 11 */
  1875. #define EXTI_FPR1_FPIF12_Pos (12U)
  1876. #define EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) /*!< 0x00001000 */
  1877. #define EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk /*!< Falling Pending Interrupt Flag on line 12 */
  1878. #define EXTI_FPR1_FPIF13_Pos (13U)
  1879. #define EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) /*!< 0x00002000 */
  1880. #define EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk /*!< Falling Pending Interrupt Flag on line 13 */
  1881. #define EXTI_FPR1_FPIF14_Pos (14U)
  1882. #define EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) /*!< 0x00004000 */
  1883. #define EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk /*!< Falling Pending Interrupt Flag on line 14 */
  1884. #define EXTI_FPR1_FPIF15_Pos (15U)
  1885. #define EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) /*!< 0x00008000 */
  1886. #define EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk /*!< Falling Pending Interrupt Flag on line 15 */
  1887. #define EXTI_FPR1_FPIF16_Pos (16U)
  1888. #define EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) /*!< 0x00010000 */
  1889. #define EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk /*!< Falling Pending Interrupt Flag on line 16 */
  1890. /***************** Bit definition for EXTI_EXTICR1 register **************/
  1891. #define EXTI_EXTICR1_EXTI0_Pos (0U)
  1892. #define EXTI_EXTICR1_EXTI0_Msk (0x7UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000007 */
  1893. #define EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
  1894. #define EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000001 */
  1895. #define EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000002 */
  1896. #define EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) /*!< 0x00000004 */
  1897. #define EXTI_EXTICR1_EXTI1_Pos (8U)
  1898. #define EXTI_EXTICR1_EXTI1_Msk (0x7UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000700 */
  1899. #define EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
  1900. #define EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000100 */
  1901. #define EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000200 */
  1902. #define EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) /*!< 0x00000400 */
  1903. #define EXTI_EXTICR1_EXTI2_Pos (16U)
  1904. #define EXTI_EXTICR1_EXTI2_Msk (0x7UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00070000 */
  1905. #define EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
  1906. #define EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00010000 */
  1907. #define EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00020000 */
  1908. #define EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) /*!< 0x00040000 */
  1909. #define EXTI_EXTICR1_EXTI3_Pos (24U)
  1910. #define EXTI_EXTICR1_EXTI3_Msk (0x7UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x07000000 */
  1911. #define EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
  1912. #define EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x01000000 */
  1913. #define EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x02000000 */
  1914. #define EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) /*!< 0x04000000 */
  1915. /***************** Bit definition for EXTI_EXTICR2 register **************/
  1916. #define EXTI_EXTICR2_EXTI4_Pos (0U)
  1917. #define EXTI_EXTICR2_EXTI4_Msk (0x7UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000007 */
  1918. #define EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
  1919. #define EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000001 */
  1920. #define EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000002 */
  1921. #define EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) /*!< 0x00000004 */
  1922. #define EXTI_EXTICR2_EXTI5_Pos (8U)
  1923. #define EXTI_EXTICR2_EXTI5_Msk (0x7UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000700 */
  1924. #define EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
  1925. #define EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000100 */
  1926. #define EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000200 */
  1927. #define EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) /*!< 0x00000400 */
  1928. #define EXTI_EXTICR2_EXTI6_Pos (16U)
  1929. #define EXTI_EXTICR2_EXTI6_Msk (0x7UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00070000 */
  1930. #define EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
  1931. #define EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00010000 */
  1932. #define EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00020000 */
  1933. #define EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) /*!< 0x00040000 */
  1934. #define EXTI_EXTICR2_EXTI7_Pos (24U)
  1935. #define EXTI_EXTICR2_EXTI7_Msk (0x7UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x07000000 */
  1936. #define EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
  1937. #define EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x01000000 */
  1938. #define EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x02000000 */
  1939. #define EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) /*!< 0x04000000 */
  1940. /***************** Bit definition for EXTI_EXTICR3 register **************/
  1941. #define EXTI_EXTICR3_EXTI8_Pos (0U)
  1942. #define EXTI_EXTICR3_EXTI8_Msk (0x7UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000007 */
  1943. #define EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
  1944. #define EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000001 */
  1945. #define EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000002 */
  1946. #define EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) /*!< 0x00000004 */
  1947. #define EXTI_EXTICR3_EXTI9_Pos (8U)
  1948. #define EXTI_EXTICR3_EXTI9_Msk (0x7UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000700 */
  1949. #define EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
  1950. #define EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000100 */
  1951. #define EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000200 */
  1952. #define EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) /*!< 0x00000400 */
  1953. #define EXTI_EXTICR3_EXTI10_Pos (16U)
  1954. #define EXTI_EXTICR3_EXTI10_Msk (0x7UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00070000 */
  1955. #define EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
  1956. #define EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00010000 */
  1957. #define EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00020000 */
  1958. #define EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) /*!< 0x00040000 */
  1959. #define EXTI_EXTICR3_EXTI11_Pos (24U)
  1960. #define EXTI_EXTICR3_EXTI11_Msk (0x7UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x07000000 */
  1961. #define EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
  1962. #define EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x01000000 */
  1963. #define EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x02000000 */
  1964. #define EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) /*!< 0x04000000 */
  1965. /***************** Bit definition for EXTI_EXTICR4 register **************/
  1966. #define EXTI_EXTICR4_EXTI12_Pos (0U)
  1967. #define EXTI_EXTICR4_EXTI12_Msk (0x7UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
  1968. #define EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
  1969. #define EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000001 */
  1970. #define EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000002 */
  1971. #define EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) /*!< 0x00000004 */
  1972. #define EXTI_EXTICR4_EXTI13_Pos (8U)
  1973. #define EXTI_EXTICR4_EXTI13_Msk (0x7UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000700 */
  1974. #define EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
  1975. #define EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000100 */
  1976. #define EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000200 */
  1977. #define EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) /*!< 0x00000400 */
  1978. #define EXTI_EXTICR4_EXTI14_Pos (16U)
  1979. #define EXTI_EXTICR4_EXTI14_Msk (0x7UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00070000 */
  1980. #define EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
  1981. #define EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00010000 */
  1982. #define EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00020000 */
  1983. #define EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) /*!< 0x00040000 */
  1984. #define EXTI_EXTICR4_EXTI15_Pos (24U)
  1985. #define EXTI_EXTICR4_EXTI15_Msk (0x7UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x07000000 */
  1986. #define EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
  1987. #define EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x01000000 */
  1988. #define EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x02000000 */
  1989. #define EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) /*!< 0x04000000 */
  1990. /******************* Bit definition for EXTI_IMR1 register ******************/
  1991. #define EXTI_IMR1_IM0_Pos (0U)
  1992. #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
  1993. #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
  1994. #define EXTI_IMR1_IM1_Pos (1U)
  1995. #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
  1996. #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
  1997. #define EXTI_IMR1_IM2_Pos (2U)
  1998. #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
  1999. #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
  2000. #define EXTI_IMR1_IM3_Pos (3U)
  2001. #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
  2002. #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
  2003. #define EXTI_IMR1_IM4_Pos (4U)
  2004. #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
  2005. #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
  2006. #define EXTI_IMR1_IM5_Pos (5U)
  2007. #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
  2008. #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
  2009. #define EXTI_IMR1_IM6_Pos (6U)
  2010. #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
  2011. #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
  2012. #define EXTI_IMR1_IM7_Pos (7U)
  2013. #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
  2014. #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
  2015. #define EXTI_IMR1_IM8_Pos (8U)
  2016. #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
  2017. #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
  2018. #define EXTI_IMR1_IM9_Pos (9U)
  2019. #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
  2020. #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
  2021. #define EXTI_IMR1_IM10_Pos (10U)
  2022. #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
  2023. #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
  2024. #define EXTI_IMR1_IM11_Pos (11U)
  2025. #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
  2026. #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
  2027. #define EXTI_IMR1_IM12_Pos (12U)
  2028. #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
  2029. #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
  2030. #define EXTI_IMR1_IM13_Pos (13U)
  2031. #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
  2032. #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
  2033. #define EXTI_IMR1_IM14_Pos (14U)
  2034. #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
  2035. #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
  2036. #define EXTI_IMR1_IM15_Pos (15U)
  2037. #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
  2038. #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
  2039. #define EXTI_IMR1_IM16_Pos (16U)
  2040. #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
  2041. #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
  2042. #define EXTI_IMR1_IM19_Pos (19U)
  2043. #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
  2044. #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
  2045. #define EXTI_IMR1_IM20_Pos (20U)
  2046. #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
  2047. #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
  2048. #define EXTI_IMR1_IM21_Pos (21U)
  2049. #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
  2050. #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
  2051. #define EXTI_IMR1_IM22_Pos (22U)
  2052. #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
  2053. #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
  2054. #define EXTI_IMR1_IM23_Pos (23U)
  2055. #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
  2056. #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
  2057. #define EXTI_IMR1_IM24_Pos (24U)
  2058. #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
  2059. #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
  2060. #define EXTI_IMR1_IM25_Pos (25U)
  2061. #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
  2062. #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
  2063. #define EXTI_IMR1_IM26_Pos (26U)
  2064. #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
  2065. #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
  2066. #define EXTI_IMR1_IM28_Pos (28U)
  2067. #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
  2068. #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
  2069. #define EXTI_IMR1_IM29_Pos (29U)
  2070. #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
  2071. #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
  2072. #define EXTI_IMR1_IM30_Pos (30U)
  2073. #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
  2074. #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
  2075. #define EXTI_IMR1_IM31_Pos (31U)
  2076. #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
  2077. #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
  2078. #define EXTI_IMR1_IM_Pos (0U)
  2079. #define EXTI_IMR1_IM_Msk (0xF2A9FFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xF6A8FFFFU */
  2080. #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
  2081. /******************* Bit definition for EXTI_EMR1 register ******************/
  2082. #define EXTI_EMR1_EM0_Pos (0U)
  2083. #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
  2084. #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
  2085. #define EXTI_EMR1_EM1_Pos (1U)
  2086. #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
  2087. #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
  2088. #define EXTI_EMR1_EM2_Pos (2U)
  2089. #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
  2090. #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
  2091. #define EXTI_EMR1_EM3_Pos (3U)
  2092. #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
  2093. #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
  2094. #define EXTI_EMR1_EM4_Pos (4U)
  2095. #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
  2096. #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
  2097. #define EXTI_EMR1_EM5_Pos (5U)
  2098. #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
  2099. #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
  2100. #define EXTI_EMR1_EM6_Pos (6U)
  2101. #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
  2102. #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
  2103. #define EXTI_EMR1_EM7_Pos (7U)
  2104. #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
  2105. #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
  2106. #define EXTI_EMR1_EM8_Pos (8U)
  2107. #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
  2108. #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
  2109. #define EXTI_EMR1_EM9_Pos (9U)
  2110. #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
  2111. #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
  2112. #define EXTI_EMR1_EM10_Pos (10U)
  2113. #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
  2114. #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
  2115. #define EXTI_EMR1_EM11_Pos (11U)
  2116. #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
  2117. #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
  2118. #define EXTI_EMR1_EM12_Pos (12U)
  2119. #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
  2120. #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
  2121. #define EXTI_EMR1_EM13_Pos (13U)
  2122. #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
  2123. #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
  2124. #define EXTI_EMR1_EM14_Pos (14U)
  2125. #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
  2126. #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
  2127. #define EXTI_EMR1_EM15_Pos (15U)
  2128. #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
  2129. #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
  2130. #define EXTI_EMR1_EM16_Pos (16U)
  2131. #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
  2132. #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
  2133. #define EXTI_EMR1_EM17_Pos (17U)
  2134. #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
  2135. #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
  2136. #define EXTI_EMR1_EM18_Pos (18U)
  2137. #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
  2138. #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
  2139. #define EXTI_EMR1_EM19_Pos (19U)
  2140. #define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
  2141. #define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
  2142. #define EXTI_EMR1_EM21_Pos (21U)
  2143. #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
  2144. #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
  2145. #define EXTI_EMR1_EM23_Pos (23U)
  2146. #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
  2147. #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
  2148. #define EXTI_EMR1_EM25_Pos (25U)
  2149. #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
  2150. #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
  2151. #define EXTI_EMR1_EM26_Pos (26U)
  2152. #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
  2153. #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
  2154. #define EXTI_EMR1_EM28_Pos (28U)
  2155. #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
  2156. #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
  2157. #define EXTI_EMR1_EM29_Pos (29U)
  2158. #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
  2159. #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
  2160. #define EXTI_EMR1_EM30_Pos (30U)
  2161. #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
  2162. #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
  2163. #define EXTI_EMR1_EM31_Pos (31U)
  2164. #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
  2165. #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
  2166. /******************************************************************************/
  2167. /* */
  2168. /* FLASH */
  2169. /* */
  2170. /******************************************************************************/
  2171. #define GPIO_NRST_CONFIG_SUPPORT /*!< GPIO feature available only on specific devices: Configure NRST pin */
  2172. #define FLASH_SECURABLE_MEMORY_SUPPORT /*!< Flash feature available only on specific devices: allow to secure memory */
  2173. #define FLASH_PCROP_SUPPORT /*!< Flash feature available only on specific devices: proprietary code read protection areas selected by option */
  2174. /******************* Bits definition for FLASH_ACR register *****************/
  2175. #define FLASH_ACR_LATENCY_Pos (0U)
  2176. #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
  2177. #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
  2178. #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
  2179. #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
  2180. #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
  2181. #define FLASH_ACR_PRFTEN_Pos (8U)
  2182. #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
  2183. #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
  2184. #define FLASH_ACR_ICEN_Pos (9U)
  2185. #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
  2186. #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
  2187. #define FLASH_ACR_ICRST_Pos (11U)
  2188. #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
  2189. #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
  2190. #define FLASH_ACR_PROGEMPTY_Pos (16U)
  2191. #define FLASH_ACR_PROGEMPTY_Msk (0x1UL << FLASH_ACR_PROGEMPTY_Pos) /*!< 0x00010000 */
  2192. #define FLASH_ACR_PROGEMPTY FLASH_ACR_PROGEMPTY_Msk
  2193. #define FLASH_ACR_DBG_SWEN_Pos (18U)
  2194. #define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
  2195. #define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk
  2196. /******************* Bits definition for FLASH_SR register ******************/
  2197. #define FLASH_SR_EOP_Pos (0U)
  2198. #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
  2199. #define FLASH_SR_EOP FLASH_SR_EOP_Msk
  2200. #define FLASH_SR_OPERR_Pos (1U)
  2201. #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
  2202. #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
  2203. #define FLASH_SR_PROGERR_Pos (3U)
  2204. #define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
  2205. #define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
  2206. #define FLASH_SR_WRPERR_Pos (4U)
  2207. #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
  2208. #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
  2209. #define FLASH_SR_PGAERR_Pos (5U)
  2210. #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
  2211. #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
  2212. #define FLASH_SR_SIZERR_Pos (6U)
  2213. #define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
  2214. #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
  2215. #define FLASH_SR_PGSERR_Pos (7U)
  2216. #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
  2217. #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
  2218. #define FLASH_SR_MISERR_Pos (8U)
  2219. #define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
  2220. #define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
  2221. #define FLASH_SR_FASTERR_Pos (9U)
  2222. #define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
  2223. #define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
  2224. #define FLASH_SR_RDERR_Pos (14U)
  2225. #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
  2226. #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
  2227. #define FLASH_SR_OPTVERR_Pos (15U)
  2228. #define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
  2229. #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
  2230. #define FLASH_SR_BSY1_Pos (16U)
  2231. #define FLASH_SR_BSY1_Msk (0x1UL << FLASH_SR_BSY1_Pos) /*!< 0x00010000 */
  2232. #define FLASH_SR_BSY1 FLASH_SR_BSY1_Msk
  2233. #define FLASH_SR_CFGBSY_Pos (18U)
  2234. #define FLASH_SR_CFGBSY_Msk (0x1UL << FLASH_SR_CFGBSY_Pos) /*!< 0x00040000 */
  2235. #define FLASH_SR_CFGBSY FLASH_SR_CFGBSY_Msk
  2236. /******************* Bits definition for FLASH_CR register ******************/
  2237. #define FLASH_CR_PG_Pos (0U)
  2238. #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
  2239. #define FLASH_CR_PG FLASH_CR_PG_Msk
  2240. #define FLASH_CR_PER_Pos (1U)
  2241. #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
  2242. #define FLASH_CR_PER FLASH_CR_PER_Msk
  2243. #define FLASH_CR_MER1_Pos (2U)
  2244. #define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
  2245. #define FLASH_CR_MER1 FLASH_CR_MER1_Msk
  2246. #define FLASH_CR_PNB_Pos (3U)
  2247. #define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
  2248. #define FLASH_CR_PNB FLASH_CR_PNB_Msk
  2249. #define FLASH_CR_STRT_Pos (16U)
  2250. #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
  2251. #define FLASH_CR_STRT FLASH_CR_STRT_Msk
  2252. #define FLASH_CR_OPTSTRT_Pos (17U)
  2253. #define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
  2254. #define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
  2255. #define FLASH_CR_FSTPG_Pos (18U)
  2256. #define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
  2257. #define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
  2258. #define FLASH_CR_EOPIE_Pos (24U)
  2259. #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
  2260. #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
  2261. #define FLASH_CR_ERRIE_Pos (25U)
  2262. #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
  2263. #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
  2264. #define FLASH_CR_RDERRIE_Pos (26U)
  2265. #define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
  2266. #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
  2267. #define FLASH_CR_OBL_LAUNCH_Pos (27U)
  2268. #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
  2269. #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
  2270. #define FLASH_CR_SEC_PROT_Pos (28U)
  2271. #define FLASH_CR_SEC_PROT_Msk (0x1UL << FLASH_CR_SEC_PROT_Pos) /*!< 0x10000000 */
  2272. #define FLASH_CR_SEC_PROT FLASH_CR_SEC_PROT_Msk
  2273. #define FLASH_CR_OPTLOCK_Pos (30U)
  2274. #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
  2275. #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
  2276. #define FLASH_CR_LOCK_Pos (31U)
  2277. #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
  2278. #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
  2279. /******************* Bits definition for FLASH_ECCR register ****************/
  2280. #define FLASH_ECCR_ADDR_ECC_Pos (0U)
  2281. #define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x00003FFF */
  2282. #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
  2283. #define FLASH_ECCR_SYSF_ECC_Pos (20U)
  2284. #define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
  2285. #define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
  2286. #define FLASH_ECCR_ECCCIE_Pos (24U)
  2287. #define FLASH_ECCR_ECCCIE_Msk (0x1UL << FLASH_ECCR_ECCCIE_Pos) /*!< 0x01000000 */
  2288. #define FLASH_ECCR_ECCCIE FLASH_ECCR_ECCCIE_Msk
  2289. #define FLASH_ECCR_ECCC_Pos (30U)
  2290. #define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
  2291. #define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
  2292. #define FLASH_ECCR_ECCD_Pos (31U)
  2293. #define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
  2294. #define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
  2295. /******************* Bits definition for FLASH_OPTR register ****************/
  2296. #define FLASH_OPTR_RDP_Pos (0U)
  2297. #define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
  2298. #define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
  2299. #define FLASH_OPTR_BOR_EN_Pos (8U)
  2300. #define FLASH_OPTR_BOR_EN_Msk (0x1UL << FLASH_OPTR_BOR_EN_Pos) /*!< 0x00000100 */
  2301. #define FLASH_OPTR_BOR_EN FLASH_OPTR_BOR_EN_Msk
  2302. #define FLASH_OPTR_BORF_LEV_Pos (9U)
  2303. #define FLASH_OPTR_BORF_LEV_Msk (0x3UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000600 */
  2304. #define FLASH_OPTR_BORF_LEV FLASH_OPTR_BORF_LEV_Msk
  2305. #define FLASH_OPTR_BORF_LEV_0 (0x1UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000200 */
  2306. #define FLASH_OPTR_BORF_LEV_1 (0x2UL << FLASH_OPTR_BORF_LEV_Pos) /*!< 0x00000400 */
  2307. #define FLASH_OPTR_BORR_LEV_Pos (11U)
  2308. #define FLASH_OPTR_BORR_LEV_Msk (0x3UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001800 */
  2309. #define FLASH_OPTR_BORR_LEV FLASH_OPTR_BORR_LEV_Msk
  2310. #define FLASH_OPTR_BORR_LEV_0 (0x1UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00000800 */
  2311. #define FLASH_OPTR_BORR_LEV_1 (0x2UL << FLASH_OPTR_BORR_LEV_Pos) /*!< 0x00001000 */
  2312. #define FLASH_OPTR_nRST_STOP_Pos (13U)
  2313. #define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00002000 */
  2314. #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
  2315. #define FLASH_OPTR_nRST_STDBY_Pos (14U)
  2316. #define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00004000 */
  2317. #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
  2318. #define FLASH_OPTR_nRST_SHDW_Pos (15U)
  2319. #define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00008000 */
  2320. #define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
  2321. #define FLASH_OPTR_IWDG_SW_Pos (16U)
  2322. #define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
  2323. #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
  2324. #define FLASH_OPTR_IWDG_STOP_Pos (17U)
  2325. #define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
  2326. #define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
  2327. #define FLASH_OPTR_IWDG_STDBY_Pos (18U)
  2328. #define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
  2329. #define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
  2330. #define FLASH_OPTR_WWDG_SW_Pos (19U)
  2331. #define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
  2332. #define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
  2333. #define FLASH_OPTR_RAM_PARITY_CHECK_Pos (22U)
  2334. #define FLASH_OPTR_RAM_PARITY_CHECK_Msk (0x1UL << FLASH_OPTR_RAM_PARITY_CHECK_Pos) /*!< 0x00400000 */
  2335. #define FLASH_OPTR_RAM_PARITY_CHECK FLASH_OPTR_RAM_PARITY_CHECK_Msk
  2336. #define FLASH_OPTR_nBOOT_SEL_Pos (24U)
  2337. #define FLASH_OPTR_nBOOT_SEL_Msk (0x1UL << FLASH_OPTR_nBOOT_SEL_Pos) /*!< 0x01000000 */
  2338. #define FLASH_OPTR_nBOOT_SEL FLASH_OPTR_nBOOT_SEL_Msk
  2339. #define FLASH_OPTR_nBOOT1_Pos (25U)
  2340. #define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x02000000 */
  2341. #define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
  2342. #define FLASH_OPTR_nBOOT0_Pos (26U)
  2343. #define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x04000000 */
  2344. #define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
  2345. #define FLASH_OPTR_NRST_MODE_Pos (27U)
  2346. #define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x18000000 */
  2347. #define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
  2348. #define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x08000000 */
  2349. #define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
  2350. #define FLASH_OPTR_IRHEN_Pos (29U)
  2351. #define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x20000000 */
  2352. #define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
  2353. /****************** Bits definition for FLASH_PCROP1ASR register ************/
  2354. #define FLASH_PCROP1ASR_PCROP1A_STRT_Pos (0U)
  2355. #define FLASH_PCROP1ASR_PCROP1A_STRT_Msk (0x7FUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos) /*!< 0x0000007F */
  2356. #define FLASH_PCROP1ASR_PCROP1A_STRT FLASH_PCROP1ASR_PCROP1A_STRT_Msk
  2357. /****************** Bits definition for FLASH_PCROP1AER register ************/
  2358. #define FLASH_PCROP1AER_PCROP1A_END_Pos (0U)
  2359. #define FLASH_PCROP1AER_PCROP1A_END_Msk (0x7FUL << FLASH_PCROP1AER_PCROP1A_END_Pos) /*!< 0x0000007F */
  2360. #define FLASH_PCROP1AER_PCROP1A_END FLASH_PCROP1AER_PCROP1A_END_Msk
  2361. #define FLASH_PCROP1AER_PCROP_RDP_Pos (31U)
  2362. #define FLASH_PCROP1AER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos) /*!< 0x80000000 */
  2363. #define FLASH_PCROP1AER_PCROP_RDP FLASH_PCROP1AER_PCROP_RDP_Msk
  2364. /****************** Bits definition for FLASH_WRP1AR register ***************/
  2365. #define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
  2366. #define FLASH_WRP1AR_WRP1A_STRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_STRT_Pos) /*!< 0x0000001F */
  2367. #define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
  2368. #define FLASH_WRP1AR_WRP1A_END_Pos (16U)
  2369. #define FLASH_WRP1AR_WRP1A_END_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_END_Pos) /*!< 0x001F0000 */
  2370. #define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
  2371. /****************** Bits definition for FLASH_WRP1BR register ***************/
  2372. #define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
  2373. #define FLASH_WRP1BR_WRP1B_STRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_STRT_Pos) /*!< 0x0000001F */
  2374. #define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
  2375. #define FLASH_WRP1BR_WRP1B_END_Pos (16U)
  2376. #define FLASH_WRP1BR_WRP1B_END_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_END_Pos) /*!< 0x001F0000 */
  2377. #define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
  2378. /****************** Bits definition for FLASH_PCROP1BSR register ************/
  2379. #define FLASH_PCROP1BSR_PCROP1B_STRT_Pos (0U)
  2380. #define FLASH_PCROP1BSR_PCROP1B_STRT_Msk (0x7FUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos) /*!< 0x0000007F */
  2381. #define FLASH_PCROP1BSR_PCROP1B_STRT FLASH_PCROP1BSR_PCROP1B_STRT_Msk
  2382. /****************** Bits definition for FLASH_PCROP1BER register ************/
  2383. #define FLASH_PCROP1BER_PCROP1B_END_Pos (0U)
  2384. #define FLASH_PCROP1BER_PCROP1B_END_Msk (0x7FUL << FLASH_PCROP1BER_PCROP1B_END_Pos) /*!< 0x0000007F */
  2385. #define FLASH_PCROP1BER_PCROP1B_END FLASH_PCROP1BER_PCROP1B_END_Msk
  2386. /****************** Bits definition for FLASH_SECR register *****************/
  2387. #define FLASH_SECR_SEC_SIZE_Pos (0U)
  2388. #define FLASH_SECR_SEC_SIZE_Msk (0x3FUL << FLASH_SECR_SEC_SIZE_Pos) /*!< 0x0000003F */
  2389. #define FLASH_SECR_SEC_SIZE FLASH_SECR_SEC_SIZE_Msk
  2390. #define FLASH_SECR_BOOT_LOCK_Pos (16U)
  2391. #define FLASH_SECR_BOOT_LOCK_Msk (0x1UL << FLASH_SECR_BOOT_LOCK_Pos) /*!< 0x00010000 */
  2392. #define FLASH_SECR_BOOT_LOCK FLASH_SECR_BOOT_LOCK_Msk
  2393. /******************************************************************************/
  2394. /* */
  2395. /* General Purpose I/O */
  2396. /* */
  2397. /******************************************************************************/
  2398. /****************** Bits definition for GPIO_MODER register *****************/
  2399. #define GPIO_MODER_MODE0_Pos (0U)
  2400. #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
  2401. #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
  2402. #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
  2403. #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
  2404. #define GPIO_MODER_MODE1_Pos (2U)
  2405. #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
  2406. #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
  2407. #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
  2408. #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
  2409. #define GPIO_MODER_MODE2_Pos (4U)
  2410. #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
  2411. #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
  2412. #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
  2413. #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
  2414. #define GPIO_MODER_MODE3_Pos (6U)
  2415. #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
  2416. #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
  2417. #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
  2418. #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
  2419. #define GPIO_MODER_MODE4_Pos (8U)
  2420. #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
  2421. #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
  2422. #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
  2423. #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
  2424. #define GPIO_MODER_MODE5_Pos (10U)
  2425. #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
  2426. #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
  2427. #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
  2428. #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
  2429. #define GPIO_MODER_MODE6_Pos (12U)
  2430. #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
  2431. #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
  2432. #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
  2433. #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
  2434. #define GPIO_MODER_MODE7_Pos (14U)
  2435. #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
  2436. #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
  2437. #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
  2438. #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
  2439. #define GPIO_MODER_MODE8_Pos (16U)
  2440. #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
  2441. #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
  2442. #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
  2443. #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
  2444. #define GPIO_MODER_MODE9_Pos (18U)
  2445. #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
  2446. #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
  2447. #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
  2448. #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
  2449. #define GPIO_MODER_MODE10_Pos (20U)
  2450. #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
  2451. #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
  2452. #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
  2453. #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
  2454. #define GPIO_MODER_MODE11_Pos (22U)
  2455. #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
  2456. #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
  2457. #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
  2458. #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
  2459. #define GPIO_MODER_MODE12_Pos (24U)
  2460. #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
  2461. #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
  2462. #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
  2463. #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
  2464. #define GPIO_MODER_MODE13_Pos (26U)
  2465. #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
  2466. #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
  2467. #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
  2468. #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
  2469. #define GPIO_MODER_MODE14_Pos (28U)
  2470. #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
  2471. #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
  2472. #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
  2473. #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
  2474. #define GPIO_MODER_MODE15_Pos (30U)
  2475. #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
  2476. #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
  2477. #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
  2478. #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
  2479. /****************** Bits definition for GPIO_OTYPER register ****************/
  2480. #define GPIO_OTYPER_OT0_Pos (0U)
  2481. #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
  2482. #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
  2483. #define GPIO_OTYPER_OT1_Pos (1U)
  2484. #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
  2485. #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
  2486. #define GPIO_OTYPER_OT2_Pos (2U)
  2487. #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
  2488. #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
  2489. #define GPIO_OTYPER_OT3_Pos (3U)
  2490. #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
  2491. #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
  2492. #define GPIO_OTYPER_OT4_Pos (4U)
  2493. #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
  2494. #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
  2495. #define GPIO_OTYPER_OT5_Pos (5U)
  2496. #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
  2497. #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
  2498. #define GPIO_OTYPER_OT6_Pos (6U)
  2499. #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
  2500. #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
  2501. #define GPIO_OTYPER_OT7_Pos (7U)
  2502. #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
  2503. #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
  2504. #define GPIO_OTYPER_OT8_Pos (8U)
  2505. #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
  2506. #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
  2507. #define GPIO_OTYPER_OT9_Pos (9U)
  2508. #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
  2509. #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
  2510. #define GPIO_OTYPER_OT10_Pos (10U)
  2511. #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
  2512. #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
  2513. #define GPIO_OTYPER_OT11_Pos (11U)
  2514. #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
  2515. #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
  2516. #define GPIO_OTYPER_OT12_Pos (12U)
  2517. #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
  2518. #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
  2519. #define GPIO_OTYPER_OT13_Pos (13U)
  2520. #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
  2521. #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
  2522. #define GPIO_OTYPER_OT14_Pos (14U)
  2523. #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
  2524. #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
  2525. #define GPIO_OTYPER_OT15_Pos (15U)
  2526. #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
  2527. #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
  2528. /****************** Bits definition for GPIO_OSPEEDR register ***************/
  2529. #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
  2530. #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
  2531. #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
  2532. #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
  2533. #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
  2534. #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
  2535. #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
  2536. #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
  2537. #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
  2538. #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
  2539. #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
  2540. #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
  2541. #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
  2542. #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
  2543. #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
  2544. #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
  2545. #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
  2546. #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
  2547. #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
  2548. #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
  2549. #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
  2550. #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
  2551. #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
  2552. #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
  2553. #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
  2554. #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
  2555. #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
  2556. #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
  2557. #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
  2558. #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
  2559. #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
  2560. #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
  2561. #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
  2562. #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
  2563. #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
  2564. #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
  2565. #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
  2566. #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
  2567. #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
  2568. #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
  2569. #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
  2570. #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
  2571. #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
  2572. #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
  2573. #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
  2574. #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
  2575. #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
  2576. #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
  2577. #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
  2578. #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
  2579. #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
  2580. #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
  2581. #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
  2582. #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
  2583. #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
  2584. #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
  2585. #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
  2586. #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
  2587. #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
  2588. #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
  2589. #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
  2590. #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
  2591. #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
  2592. #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
  2593. #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
  2594. #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
  2595. #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
  2596. #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
  2597. #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
  2598. #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
  2599. #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
  2600. #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
  2601. #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
  2602. #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
  2603. #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
  2604. #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
  2605. #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
  2606. #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
  2607. #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
  2608. #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
  2609. /****************** Bits definition for GPIO_PUPDR register *****************/
  2610. #define GPIO_PUPDR_PUPD0_Pos (0U)
  2611. #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
  2612. #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
  2613. #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
  2614. #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
  2615. #define GPIO_PUPDR_PUPD1_Pos (2U)
  2616. #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
  2617. #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
  2618. #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
  2619. #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
  2620. #define GPIO_PUPDR_PUPD2_Pos (4U)
  2621. #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
  2622. #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
  2623. #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
  2624. #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
  2625. #define GPIO_PUPDR_PUPD3_Pos (6U)
  2626. #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
  2627. #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
  2628. #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
  2629. #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
  2630. #define GPIO_PUPDR_PUPD4_Pos (8U)
  2631. #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
  2632. #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
  2633. #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
  2634. #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
  2635. #define GPIO_PUPDR_PUPD5_Pos (10U)
  2636. #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
  2637. #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
  2638. #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
  2639. #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
  2640. #define GPIO_PUPDR_PUPD6_Pos (12U)
  2641. #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
  2642. #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
  2643. #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
  2644. #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
  2645. #define GPIO_PUPDR_PUPD7_Pos (14U)
  2646. #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
  2647. #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
  2648. #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
  2649. #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
  2650. #define GPIO_PUPDR_PUPD8_Pos (16U)
  2651. #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
  2652. #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
  2653. #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
  2654. #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
  2655. #define GPIO_PUPDR_PUPD9_Pos (18U)
  2656. #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
  2657. #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
  2658. #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
  2659. #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
  2660. #define GPIO_PUPDR_PUPD10_Pos (20U)
  2661. #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
  2662. #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
  2663. #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
  2664. #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
  2665. #define GPIO_PUPDR_PUPD11_Pos (22U)
  2666. #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
  2667. #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
  2668. #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
  2669. #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
  2670. #define GPIO_PUPDR_PUPD12_Pos (24U)
  2671. #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
  2672. #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
  2673. #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
  2674. #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
  2675. #define GPIO_PUPDR_PUPD13_Pos (26U)
  2676. #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
  2677. #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
  2678. #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
  2679. #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
  2680. #define GPIO_PUPDR_PUPD14_Pos (28U)
  2681. #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
  2682. #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
  2683. #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
  2684. #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
  2685. #define GPIO_PUPDR_PUPD15_Pos (30U)
  2686. #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
  2687. #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
  2688. #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
  2689. #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
  2690. /****************** Bits definition for GPIO_IDR register *******************/
  2691. #define GPIO_IDR_ID0_Pos (0U)
  2692. #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
  2693. #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
  2694. #define GPIO_IDR_ID1_Pos (1U)
  2695. #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
  2696. #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
  2697. #define GPIO_IDR_ID2_Pos (2U)
  2698. #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
  2699. #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
  2700. #define GPIO_IDR_ID3_Pos (3U)
  2701. #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
  2702. #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
  2703. #define GPIO_IDR_ID4_Pos (4U)
  2704. #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
  2705. #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
  2706. #define GPIO_IDR_ID5_Pos (5U)
  2707. #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
  2708. #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
  2709. #define GPIO_IDR_ID6_Pos (6U)
  2710. #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
  2711. #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
  2712. #define GPIO_IDR_ID7_Pos (7U)
  2713. #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
  2714. #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
  2715. #define GPIO_IDR_ID8_Pos (8U)
  2716. #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
  2717. #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
  2718. #define GPIO_IDR_ID9_Pos (9U)
  2719. #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
  2720. #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
  2721. #define GPIO_IDR_ID10_Pos (10U)
  2722. #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
  2723. #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
  2724. #define GPIO_IDR_ID11_Pos (11U)
  2725. #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
  2726. #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
  2727. #define GPIO_IDR_ID12_Pos (12U)
  2728. #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
  2729. #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
  2730. #define GPIO_IDR_ID13_Pos (13U)
  2731. #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
  2732. #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
  2733. #define GPIO_IDR_ID14_Pos (14U)
  2734. #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
  2735. #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
  2736. #define GPIO_IDR_ID15_Pos (15U)
  2737. #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
  2738. #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
  2739. /****************** Bits definition for GPIO_ODR register *******************/
  2740. #define GPIO_ODR_OD0_Pos (0U)
  2741. #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
  2742. #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
  2743. #define GPIO_ODR_OD1_Pos (1U)
  2744. #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
  2745. #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
  2746. #define GPIO_ODR_OD2_Pos (2U)
  2747. #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
  2748. #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
  2749. #define GPIO_ODR_OD3_Pos (3U)
  2750. #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
  2751. #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
  2752. #define GPIO_ODR_OD4_Pos (4U)
  2753. #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
  2754. #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
  2755. #define GPIO_ODR_OD5_Pos (5U)
  2756. #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
  2757. #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
  2758. #define GPIO_ODR_OD6_Pos (6U)
  2759. #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
  2760. #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
  2761. #define GPIO_ODR_OD7_Pos (7U)
  2762. #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
  2763. #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
  2764. #define GPIO_ODR_OD8_Pos (8U)
  2765. #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
  2766. #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
  2767. #define GPIO_ODR_OD9_Pos (9U)
  2768. #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
  2769. #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
  2770. #define GPIO_ODR_OD10_Pos (10U)
  2771. #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
  2772. #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
  2773. #define GPIO_ODR_OD11_Pos (11U)
  2774. #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
  2775. #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
  2776. #define GPIO_ODR_OD12_Pos (12U)
  2777. #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
  2778. #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
  2779. #define GPIO_ODR_OD13_Pos (13U)
  2780. #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
  2781. #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
  2782. #define GPIO_ODR_OD14_Pos (14U)
  2783. #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
  2784. #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
  2785. #define GPIO_ODR_OD15_Pos (15U)
  2786. #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
  2787. #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
  2788. /****************** Bits definition for GPIO_BSRR register ******************/
  2789. #define GPIO_BSRR_BS0_Pos (0U)
  2790. #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
  2791. #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
  2792. #define GPIO_BSRR_BS1_Pos (1U)
  2793. #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
  2794. #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
  2795. #define GPIO_BSRR_BS2_Pos (2U)
  2796. #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
  2797. #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
  2798. #define GPIO_BSRR_BS3_Pos (3U)
  2799. #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
  2800. #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
  2801. #define GPIO_BSRR_BS4_Pos (4U)
  2802. #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
  2803. #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
  2804. #define GPIO_BSRR_BS5_Pos (5U)
  2805. #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
  2806. #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
  2807. #define GPIO_BSRR_BS6_Pos (6U)
  2808. #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
  2809. #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
  2810. #define GPIO_BSRR_BS7_Pos (7U)
  2811. #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
  2812. #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
  2813. #define GPIO_BSRR_BS8_Pos (8U)
  2814. #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
  2815. #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
  2816. #define GPIO_BSRR_BS9_Pos (9U)
  2817. #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
  2818. #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
  2819. #define GPIO_BSRR_BS10_Pos (10U)
  2820. #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
  2821. #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
  2822. #define GPIO_BSRR_BS11_Pos (11U)
  2823. #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
  2824. #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
  2825. #define GPIO_BSRR_BS12_Pos (12U)
  2826. #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
  2827. #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
  2828. #define GPIO_BSRR_BS13_Pos (13U)
  2829. #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
  2830. #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
  2831. #define GPIO_BSRR_BS14_Pos (14U)
  2832. #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
  2833. #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
  2834. #define GPIO_BSRR_BS15_Pos (15U)
  2835. #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
  2836. #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
  2837. #define GPIO_BSRR_BR0_Pos (16U)
  2838. #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
  2839. #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
  2840. #define GPIO_BSRR_BR1_Pos (17U)
  2841. #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
  2842. #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
  2843. #define GPIO_BSRR_BR2_Pos (18U)
  2844. #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
  2845. #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
  2846. #define GPIO_BSRR_BR3_Pos (19U)
  2847. #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
  2848. #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
  2849. #define GPIO_BSRR_BR4_Pos (20U)
  2850. #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
  2851. #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
  2852. #define GPIO_BSRR_BR5_Pos (21U)
  2853. #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
  2854. #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
  2855. #define GPIO_BSRR_BR6_Pos (22U)
  2856. #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
  2857. #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
  2858. #define GPIO_BSRR_BR7_Pos (23U)
  2859. #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
  2860. #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
  2861. #define GPIO_BSRR_BR8_Pos (24U)
  2862. #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
  2863. #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
  2864. #define GPIO_BSRR_BR9_Pos (25U)
  2865. #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
  2866. #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
  2867. #define GPIO_BSRR_BR10_Pos (26U)
  2868. #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
  2869. #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
  2870. #define GPIO_BSRR_BR11_Pos (27U)
  2871. #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
  2872. #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
  2873. #define GPIO_BSRR_BR12_Pos (28U)
  2874. #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
  2875. #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
  2876. #define GPIO_BSRR_BR13_Pos (29U)
  2877. #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
  2878. #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
  2879. #define GPIO_BSRR_BR14_Pos (30U)
  2880. #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
  2881. #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
  2882. #define GPIO_BSRR_BR15_Pos (31U)
  2883. #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
  2884. #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
  2885. /****************** Bit definition for GPIO_LCKR register *********************/
  2886. #define GPIO_LCKR_LCK0_Pos (0U)
  2887. #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
  2888. #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
  2889. #define GPIO_LCKR_LCK1_Pos (1U)
  2890. #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
  2891. #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
  2892. #define GPIO_LCKR_LCK2_Pos (2U)
  2893. #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
  2894. #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
  2895. #define GPIO_LCKR_LCK3_Pos (3U)
  2896. #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
  2897. #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
  2898. #define GPIO_LCKR_LCK4_Pos (4U)
  2899. #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
  2900. #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
  2901. #define GPIO_LCKR_LCK5_Pos (5U)
  2902. #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
  2903. #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
  2904. #define GPIO_LCKR_LCK6_Pos (6U)
  2905. #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
  2906. #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
  2907. #define GPIO_LCKR_LCK7_Pos (7U)
  2908. #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
  2909. #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
  2910. #define GPIO_LCKR_LCK8_Pos (8U)
  2911. #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
  2912. #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
  2913. #define GPIO_LCKR_LCK9_Pos (9U)
  2914. #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
  2915. #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
  2916. #define GPIO_LCKR_LCK10_Pos (10U)
  2917. #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
  2918. #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
  2919. #define GPIO_LCKR_LCK11_Pos (11U)
  2920. #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
  2921. #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
  2922. #define GPIO_LCKR_LCK12_Pos (12U)
  2923. #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
  2924. #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
  2925. #define GPIO_LCKR_LCK13_Pos (13U)
  2926. #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
  2927. #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
  2928. #define GPIO_LCKR_LCK14_Pos (14U)
  2929. #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
  2930. #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
  2931. #define GPIO_LCKR_LCK15_Pos (15U)
  2932. #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
  2933. #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
  2934. #define GPIO_LCKR_LCKK_Pos (16U)
  2935. #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
  2936. #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
  2937. /****************** Bit definition for GPIO_AFRL register *********************/
  2938. #define GPIO_AFRL_AFSEL0_Pos (0U)
  2939. #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
  2940. #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
  2941. #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
  2942. #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
  2943. #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
  2944. #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
  2945. #define GPIO_AFRL_AFSEL1_Pos (4U)
  2946. #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
  2947. #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
  2948. #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
  2949. #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
  2950. #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
  2951. #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
  2952. #define GPIO_AFRL_AFSEL2_Pos (8U)
  2953. #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
  2954. #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
  2955. #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
  2956. #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
  2957. #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
  2958. #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
  2959. #define GPIO_AFRL_AFSEL3_Pos (12U)
  2960. #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
  2961. #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
  2962. #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
  2963. #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
  2964. #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
  2965. #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
  2966. #define GPIO_AFRL_AFSEL4_Pos (16U)
  2967. #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
  2968. #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
  2969. #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
  2970. #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
  2971. #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
  2972. #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
  2973. #define GPIO_AFRL_AFSEL5_Pos (20U)
  2974. #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
  2975. #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
  2976. #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
  2977. #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
  2978. #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
  2979. #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
  2980. #define GPIO_AFRL_AFSEL6_Pos (24U)
  2981. #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
  2982. #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
  2983. #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
  2984. #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
  2985. #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
  2986. #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
  2987. #define GPIO_AFRL_AFSEL7_Pos (28U)
  2988. #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
  2989. #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
  2990. #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
  2991. #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
  2992. #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
  2993. #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
  2994. /****************** Bit definition for GPIO_AFRH register *********************/
  2995. #define GPIO_AFRH_AFSEL8_Pos (0U)
  2996. #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
  2997. #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
  2998. #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
  2999. #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
  3000. #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
  3001. #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
  3002. #define GPIO_AFRH_AFSEL9_Pos (4U)
  3003. #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
  3004. #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
  3005. #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
  3006. #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
  3007. #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
  3008. #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
  3009. #define GPIO_AFRH_AFSEL10_Pos (8U)
  3010. #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
  3011. #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
  3012. #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
  3013. #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
  3014. #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
  3015. #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
  3016. #define GPIO_AFRH_AFSEL11_Pos (12U)
  3017. #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
  3018. #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
  3019. #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
  3020. #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
  3021. #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
  3022. #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
  3023. #define GPIO_AFRH_AFSEL12_Pos (16U)
  3024. #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
  3025. #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
  3026. #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
  3027. #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
  3028. #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
  3029. #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
  3030. #define GPIO_AFRH_AFSEL13_Pos (20U)
  3031. #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
  3032. #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
  3033. #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
  3034. #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
  3035. #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
  3036. #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
  3037. #define GPIO_AFRH_AFSEL14_Pos (24U)
  3038. #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
  3039. #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
  3040. #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
  3041. #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
  3042. #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
  3043. #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
  3044. #define GPIO_AFRH_AFSEL15_Pos (28U)
  3045. #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
  3046. #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
  3047. #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
  3048. #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
  3049. #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
  3050. #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
  3051. /****************** Bits definition for GPIO_BRR register ******************/
  3052. #define GPIO_BRR_BR0_Pos (0U)
  3053. #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
  3054. #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
  3055. #define GPIO_BRR_BR1_Pos (1U)
  3056. #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
  3057. #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
  3058. #define GPIO_BRR_BR2_Pos (2U)
  3059. #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
  3060. #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
  3061. #define GPIO_BRR_BR3_Pos (3U)
  3062. #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
  3063. #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
  3064. #define GPIO_BRR_BR4_Pos (4U)
  3065. #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
  3066. #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
  3067. #define GPIO_BRR_BR5_Pos (5U)
  3068. #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
  3069. #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
  3070. #define GPIO_BRR_BR6_Pos (6U)
  3071. #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
  3072. #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
  3073. #define GPIO_BRR_BR7_Pos (7U)
  3074. #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
  3075. #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
  3076. #define GPIO_BRR_BR8_Pos (8U)
  3077. #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
  3078. #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
  3079. #define GPIO_BRR_BR9_Pos (9U)
  3080. #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
  3081. #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
  3082. #define GPIO_BRR_BR10_Pos (10U)
  3083. #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
  3084. #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
  3085. #define GPIO_BRR_BR11_Pos (11U)
  3086. #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
  3087. #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
  3088. #define GPIO_BRR_BR12_Pos (12U)
  3089. #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
  3090. #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
  3091. #define GPIO_BRR_BR13_Pos (13U)
  3092. #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
  3093. #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
  3094. #define GPIO_BRR_BR14_Pos (14U)
  3095. #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
  3096. #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
  3097. #define GPIO_BRR_BR15_Pos (15U)
  3098. #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
  3099. #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
  3100. /******************************************************************************/
  3101. /* */
  3102. /* Inter-integrated Circuit Interface (I2C) */
  3103. /* */
  3104. /******************************************************************************/
  3105. /******************* Bit definition for I2C_CR1 register *******************/
  3106. #define I2C_CR1_PE_Pos (0U)
  3107. #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
  3108. #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
  3109. #define I2C_CR1_TXIE_Pos (1U)
  3110. #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
  3111. #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
  3112. #define I2C_CR1_RXIE_Pos (2U)
  3113. #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
  3114. #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
  3115. #define I2C_CR1_ADDRIE_Pos (3U)
  3116. #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
  3117. #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
  3118. #define I2C_CR1_NACKIE_Pos (4U)
  3119. #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
  3120. #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
  3121. #define I2C_CR1_STOPIE_Pos (5U)
  3122. #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
  3123. #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
  3124. #define I2C_CR1_TCIE_Pos (6U)
  3125. #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
  3126. #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
  3127. #define I2C_CR1_ERRIE_Pos (7U)
  3128. #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
  3129. #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
  3130. #define I2C_CR1_DNF_Pos (8U)
  3131. #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
  3132. #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
  3133. #define I2C_CR1_ANFOFF_Pos (12U)
  3134. #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
  3135. #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
  3136. #define I2C_CR1_SWRST_Pos (13U)
  3137. #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
  3138. #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
  3139. #define I2C_CR1_TXDMAEN_Pos (14U)
  3140. #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
  3141. #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
  3142. #define I2C_CR1_RXDMAEN_Pos (15U)
  3143. #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
  3144. #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
  3145. #define I2C_CR1_SBC_Pos (16U)
  3146. #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
  3147. #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
  3148. #define I2C_CR1_NOSTRETCH_Pos (17U)
  3149. #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
  3150. #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
  3151. #define I2C_CR1_WUPEN_Pos (18U)
  3152. #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
  3153. #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
  3154. #define I2C_CR1_GCEN_Pos (19U)
  3155. #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
  3156. #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
  3157. #define I2C_CR1_SMBHEN_Pos (20U)
  3158. #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
  3159. #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
  3160. #define I2C_CR1_SMBDEN_Pos (21U)
  3161. #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
  3162. #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
  3163. #define I2C_CR1_ALERTEN_Pos (22U)
  3164. #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
  3165. #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
  3166. #define I2C_CR1_PECEN_Pos (23U)
  3167. #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
  3168. #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
  3169. /****************** Bit definition for I2C_CR2 register ********************/
  3170. #define I2C_CR2_SADD_Pos (0U)
  3171. #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
  3172. #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
  3173. #define I2C_CR2_RD_WRN_Pos (10U)
  3174. #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
  3175. #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
  3176. #define I2C_CR2_ADD10_Pos (11U)
  3177. #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
  3178. #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
  3179. #define I2C_CR2_HEAD10R_Pos (12U)
  3180. #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
  3181. #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
  3182. #define I2C_CR2_START_Pos (13U)
  3183. #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
  3184. #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
  3185. #define I2C_CR2_STOP_Pos (14U)
  3186. #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
  3187. #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
  3188. #define I2C_CR2_NACK_Pos (15U)
  3189. #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
  3190. #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
  3191. #define I2C_CR2_NBYTES_Pos (16U)
  3192. #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
  3193. #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
  3194. #define I2C_CR2_RELOAD_Pos (24U)
  3195. #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
  3196. #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
  3197. #define I2C_CR2_AUTOEND_Pos (25U)
  3198. #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
  3199. #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
  3200. #define I2C_CR2_PECBYTE_Pos (26U)
  3201. #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
  3202. #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
  3203. /******************* Bit definition for I2C_OAR1 register ******************/
  3204. #define I2C_OAR1_OA1_Pos (0U)
  3205. #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
  3206. #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
  3207. #define I2C_OAR1_OA1MODE_Pos (10U)
  3208. #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
  3209. #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
  3210. #define I2C_OAR1_OA1EN_Pos (15U)
  3211. #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
  3212. #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
  3213. /******************* Bit definition for I2C_OAR2 register ******************/
  3214. #define I2C_OAR2_OA2_Pos (1U)
  3215. #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
  3216. #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
  3217. #define I2C_OAR2_OA2MSK_Pos (8U)
  3218. #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
  3219. #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
  3220. #define I2C_OAR2_OA2NOMASK (0U) /*!< No mask */
  3221. #define I2C_OAR2_OA2MASK01_Pos (8U)
  3222. #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
  3223. #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
  3224. #define I2C_OAR2_OA2MASK02_Pos (9U)
  3225. #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
  3226. #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
  3227. #define I2C_OAR2_OA2MASK03_Pos (8U)
  3228. #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
  3229. #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
  3230. #define I2C_OAR2_OA2MASK04_Pos (10U)
  3231. #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
  3232. #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
  3233. #define I2C_OAR2_OA2MASK05_Pos (8U)
  3234. #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
  3235. #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
  3236. #define I2C_OAR2_OA2MASK06_Pos (9U)
  3237. #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
  3238. #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
  3239. #define I2C_OAR2_OA2MASK07_Pos (8U)
  3240. #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
  3241. #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
  3242. #define I2C_OAR2_OA2EN_Pos (15U)
  3243. #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
  3244. #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
  3245. /******************* Bit definition for I2C_TIMINGR register *******************/
  3246. #define I2C_TIMINGR_SCLL_Pos (0U)
  3247. #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
  3248. #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
  3249. #define I2C_TIMINGR_SCLH_Pos (8U)
  3250. #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
  3251. #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
  3252. #define I2C_TIMINGR_SDADEL_Pos (16U)
  3253. #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
  3254. #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
  3255. #define I2C_TIMINGR_SCLDEL_Pos (20U)
  3256. #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
  3257. #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
  3258. #define I2C_TIMINGR_PRESC_Pos (28U)
  3259. #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
  3260. #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
  3261. /******************* Bit definition for I2C_TIMEOUTR register *******************/
  3262. #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
  3263. #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
  3264. #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
  3265. #define I2C_TIMEOUTR_TIDLE_Pos (12U)
  3266. #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
  3267. #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
  3268. #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
  3269. #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
  3270. #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
  3271. #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
  3272. #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
  3273. #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
  3274. #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
  3275. #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
  3276. #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
  3277. /****************** Bit definition for I2C_ISR register *********************/
  3278. #define I2C_ISR_TXE_Pos (0U)
  3279. #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
  3280. #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
  3281. #define I2C_ISR_TXIS_Pos (1U)
  3282. #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
  3283. #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
  3284. #define I2C_ISR_RXNE_Pos (2U)
  3285. #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
  3286. #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
  3287. #define I2C_ISR_ADDR_Pos (3U)
  3288. #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
  3289. #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
  3290. #define I2C_ISR_NACKF_Pos (4U)
  3291. #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
  3292. #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
  3293. #define I2C_ISR_STOPF_Pos (5U)
  3294. #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
  3295. #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
  3296. #define I2C_ISR_TC_Pos (6U)
  3297. #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
  3298. #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
  3299. #define I2C_ISR_TCR_Pos (7U)
  3300. #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
  3301. #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
  3302. #define I2C_ISR_BERR_Pos (8U)
  3303. #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
  3304. #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
  3305. #define I2C_ISR_ARLO_Pos (9U)
  3306. #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
  3307. #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
  3308. #define I2C_ISR_OVR_Pos (10U)
  3309. #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
  3310. #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
  3311. #define I2C_ISR_PECERR_Pos (11U)
  3312. #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
  3313. #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
  3314. #define I2C_ISR_TIMEOUT_Pos (12U)
  3315. #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
  3316. #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
  3317. #define I2C_ISR_ALERT_Pos (13U)
  3318. #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
  3319. #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
  3320. #define I2C_ISR_BUSY_Pos (15U)
  3321. #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
  3322. #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
  3323. #define I2C_ISR_DIR_Pos (16U)
  3324. #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
  3325. #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
  3326. #define I2C_ISR_ADDCODE_Pos (17U)
  3327. #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
  3328. #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
  3329. /****************** Bit definition for I2C_ICR register *********************/
  3330. #define I2C_ICR_ADDRCF_Pos (3U)
  3331. #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
  3332. #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
  3333. #define I2C_ICR_NACKCF_Pos (4U)
  3334. #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
  3335. #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
  3336. #define I2C_ICR_STOPCF_Pos (5U)
  3337. #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
  3338. #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
  3339. #define I2C_ICR_BERRCF_Pos (8U)
  3340. #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
  3341. #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
  3342. #define I2C_ICR_ARLOCF_Pos (9U)
  3343. #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
  3344. #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
  3345. #define I2C_ICR_OVRCF_Pos (10U)
  3346. #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
  3347. #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
  3348. #define I2C_ICR_PECCF_Pos (11U)
  3349. #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
  3350. #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
  3351. #define I2C_ICR_TIMOUTCF_Pos (12U)
  3352. #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
  3353. #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
  3354. #define I2C_ICR_ALERTCF_Pos (13U)
  3355. #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
  3356. #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
  3357. /****************** Bit definition for I2C_PECR register *********************/
  3358. #define I2C_PECR_PEC_Pos (0U)
  3359. #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
  3360. #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
  3361. /****************** Bit definition for I2C_RXDR register *********************/
  3362. #define I2C_RXDR_RXDATA_Pos (0U)
  3363. #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
  3364. #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
  3365. /****************** Bit definition for I2C_TXDR register *********************/
  3366. #define I2C_TXDR_TXDATA_Pos (0U)
  3367. #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
  3368. #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
  3369. /******************************************************************************/
  3370. /* */
  3371. /* Independent WATCHDOG (IWDG) */
  3372. /* */
  3373. /******************************************************************************/
  3374. /******************* Bit definition for IWDG_KR register ********************/
  3375. #define IWDG_KR_KEY_Pos (0U)
  3376. #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
  3377. #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
  3378. /******************* Bit definition for IWDG_PR register ********************/
  3379. #define IWDG_PR_PR_Pos (0U)
  3380. #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
  3381. #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
  3382. #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
  3383. #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
  3384. #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
  3385. /******************* Bit definition for IWDG_RLR register *******************/
  3386. #define IWDG_RLR_RL_Pos (0U)
  3387. #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
  3388. #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
  3389. /******************* Bit definition for IWDG_SR register ********************/
  3390. #define IWDG_SR_PVU_Pos (0U)
  3391. #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
  3392. #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
  3393. #define IWDG_SR_RVU_Pos (1U)
  3394. #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
  3395. #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
  3396. #define IWDG_SR_WVU_Pos (2U)
  3397. #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
  3398. #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
  3399. /******************* Bit definition for IWDG_KR register ********************/
  3400. #define IWDG_WINR_WIN_Pos (0U)
  3401. #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
  3402. #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
  3403. /******************************************************************************/
  3404. /* */
  3405. /* Power Control */
  3406. /* */
  3407. /******************************************************************************/
  3408. #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
  3409. #define PWR_BOR_SUPPORT /*!< PWR feature available only on specific devices: Brown-Out Reset feature */
  3410. #define PWR_SHDW_SUPPORT /*!< PWR feature available only on specific devices: Shutdown mode */
  3411. /******************** Bit definition for PWR_CR1 register ********************/
  3412. #define PWR_CR1_LPMS_Pos (0U)
  3413. #define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
  3414. #define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low Power Mode Selection */
  3415. #define PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) /*!< 0x00000001 */
  3416. #define PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) /*!< 0x00000002 */
  3417. #define PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) /*!< 0x00000004 */
  3418. #define PWR_CR1_FPD_STOP_Pos (3U)
  3419. #define PWR_CR1_FPD_STOP_Msk (0x1UL << PWR_CR1_FPD_STOP_Pos) /*!< 0x00000008 */
  3420. #define PWR_CR1_FPD_STOP PWR_CR1_FPD_STOP_Msk /*!< Flash power down mode during stop */
  3421. #define PWR_CR1_FPD_LPRUN_Pos (4U)
  3422. #define PWR_CR1_FPD_LPRUN_Msk (0x1UL << PWR_CR1_FPD_LPRUN_Pos) /*!< 0x00000010 */
  3423. #define PWR_CR1_FPD_LPRUN PWR_CR1_FPD_LPRUN_Msk /*!< Flash power down mode during run */
  3424. #define PWR_CR1_FPD_LPSLP_Pos (5U)
  3425. #define PWR_CR1_FPD_LPSLP_Msk (0x1UL << PWR_CR1_FPD_LPSLP_Pos) /*!< 0x00000020 */
  3426. #define PWR_CR1_FPD_LPSLP PWR_CR1_FPD_LPSLP_Msk /*!< Flash power down mode during sleep */
  3427. #define PWR_CR1_DBP_Pos (8U)
  3428. #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
  3429. #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */
  3430. #define PWR_CR1_VOS_Pos (9U)
  3431. #define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
  3432. #define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< Voltage scaling */
  3433. #define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 0 */
  3434. #define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< Voltage scaling bit 1 */
  3435. #define PWR_CR1_LPR_Pos (14U)
  3436. #define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
  3437. #define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator Low-Power Run mode */
  3438. /******************** Bit definition for PWR_CR2 register ********************/
  3439. #define PWR_CR2_PVDE_Pos (0U)
  3440. #define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
  3441. #define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Programmable Voltage Detector Enable */
  3442. #define PWR_CR2_PVDFT_Pos (1U)
  3443. #define PWR_CR2_PVDFT_Msk (0x7UL << PWR_CR2_PVDFT_Pos) /*!< 0x0000000E */
  3444. #define PWR_CR2_PVDFT PWR_CR2_PVDFT_Msk /*!< PVD Falling Threshold Selection bit field */
  3445. #define PWR_CR2_PVDFT_0 (0x1UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000002 */
  3446. #define PWR_CR2_PVDFT_1 (0x2UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000004 */
  3447. #define PWR_CR2_PVDFT_2 (0x4UL << PWR_CR2_PVDFT_Pos) /*!< 0x00000008 */
  3448. #define PWR_CR2_PVDRT_Pos (4U)
  3449. #define PWR_CR2_PVDRT_Msk (0x7UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000070 */
  3450. #define PWR_CR2_PVDRT PWR_CR2_PVDRT_Msk /*!< PVD Rising Threshold Selection bit field */
  3451. #define PWR_CR2_PVDRT_0 (0x1UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000010 */
  3452. #define PWR_CR2_PVDRT_1 (0x2UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000020 */
  3453. #define PWR_CR2_PVDRT_2 (0x4UL << PWR_CR2_PVDRT_Pos) /*!< 0x00000040 */
  3454. /******************** Bit definition for PWR_CR3 register ********************/
  3455. #define PWR_CR3_EWUP_Pos (0U)
  3456. #define PWR_CR3_EWUP_Msk (0x2BUL << PWR_CR3_EWUP_Pos) /*!< 0x0000002B */
  3457. #define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable all Wake-Up Pins */
  3458. #define PWR_CR3_EWUP1_Pos (0U)
  3459. #define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
  3460. #define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable WKUP pin 1 */
  3461. #define PWR_CR3_EWUP2_Pos (1U)
  3462. #define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
  3463. #define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable WKUP pin 2 */
  3464. #define PWR_CR3_EWUP4_Pos (3U)
  3465. #define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
  3466. #define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable WKUP pin 4 */
  3467. #define PWR_CR3_EWUP6_Pos (5U)
  3468. #define PWR_CR3_EWUP6_Msk (0x1UL << PWR_CR3_EWUP6_Pos) /*!< 0x00000020 */
  3469. #define PWR_CR3_EWUP6 PWR_CR3_EWUP6_Msk /*!< Enable WKUP pin 6 */
  3470. #define PWR_CR3_RRS_Pos (8U)
  3471. #define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
  3472. #define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< RAM retention in Standby mode */
  3473. #define PWR_CR3_ENB_ULP_Pos (9U)
  3474. #define PWR_CR3_ENB_ULP_Msk (0x1UL << PWR_CR3_ENB_ULP_Pos) /*!< 0x00000200 */
  3475. #define PWR_CR3_ENB_ULP PWR_CR3_ENB_ULP_Msk /*!< Enable sampling resistor bridge in the LPMU_RESET block */
  3476. #define PWR_CR3_APC_Pos (10U)
  3477. #define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
  3478. #define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
  3479. #define PWR_CR3_EIWUL_Pos (15U)
  3480. #define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
  3481. #define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
  3482. /******************** Bit definition for PWR_CR4 register ********************/
  3483. #define PWR_CR4_WP_Pos (0U)
  3484. #define PWR_CR4_WP_Msk (0x2BUL << PWR_CR4_WP_Pos) /*!< 0x0000002B */
  3485. #define PWR_CR4_WP PWR_CR4_WP_Msk /*!< all Wake-Up Pin polarity */
  3486. #define PWR_CR4_WP1_Pos (0U)
  3487. #define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
  3488. #define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
  3489. #define PWR_CR4_WP2_Pos (1U)
  3490. #define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
  3491. #define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
  3492. #define PWR_CR4_WP4_Pos (3U)
  3493. #define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
  3494. #define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
  3495. #define PWR_CR4_WP6_Pos (5U)
  3496. #define PWR_CR4_WP6_Msk (0x1UL << PWR_CR4_WP6_Pos) /*!< 0x00000020 */
  3497. #define PWR_CR4_WP6 PWR_CR4_WP6_Msk /*!< Wake-Up Pin 6 polarity */
  3498. #define PWR_CR4_VBE_Pos (8U)
  3499. #define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
  3500. #define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
  3501. #define PWR_CR4_VBRS_Pos (9U)
  3502. #define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
  3503. #define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
  3504. /******************** Bit definition for PWR_SR1 register ********************/
  3505. #define PWR_SR1_WUF_Pos (0U)
  3506. #define PWR_SR1_WUF_Msk (0x2BUL << PWR_SR1_WUF_Pos) /*!< 0x0000002B */
  3507. #define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wakeup Flags */
  3508. #define PWR_SR1_WUF1_Pos (0U)
  3509. #define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
  3510. #define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wakeup Flag 1 */
  3511. #define PWR_SR1_WUF2_Pos (1U)
  3512. #define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
  3513. #define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wakeup Flag 2 */
  3514. #define PWR_SR1_WUF4_Pos (3U)
  3515. #define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
  3516. #define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wakeup Flag 4 */
  3517. #define PWR_SR1_WUF6_Pos (5U)
  3518. #define PWR_SR1_WUF6_Msk (0x1UL << PWR_SR1_WUF6_Pos) /*!< 0x00000020 */
  3519. #define PWR_SR1_WUF6 PWR_SR1_WUF6_Msk /*!< Wakeup Flag 6 */
  3520. #define PWR_SR1_SBF_Pos (8U)
  3521. #define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
  3522. #define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Standby Flag */
  3523. #define PWR_SR1_WUFI_Pos (15U)
  3524. #define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
  3525. #define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wakeup Flag Internal */
  3526. /******************** Bit definition for PWR_SR2 register ********************/
  3527. #define PWR_SR2_FLASH_RDY_Pos (7U)
  3528. #define PWR_SR2_FLASH_RDY_Msk (0x1UL << PWR_SR2_FLASH_RDY_Pos) /*!< 0x00000080 */
  3529. #define PWR_SR2_FLASH_RDY PWR_SR2_FLASH_RDY_Msk /*!< Flash Ready */
  3530. #define PWR_SR2_REGLPS_Pos (8U)
  3531. #define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
  3532. #define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Regulator Low Power started */
  3533. #define PWR_SR2_REGLPF_Pos (9U)
  3534. #define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
  3535. #define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Regulator Low Power flag */
  3536. #define PWR_SR2_VOSF_Pos (10U)
  3537. #define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
  3538. #define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
  3539. #define PWR_SR2_PVDO_Pos (11U)
  3540. #define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
  3541. #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
  3542. /******************** Bit definition for PWR_SCR register ********************/
  3543. #define PWR_SCR_CWUF_Pos (0U)
  3544. #define PWR_SCR_CWUF_Msk (0x2BUL << PWR_SCR_CWUF_Pos) /*!< 0x0000002B */
  3545. #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
  3546. #define PWR_SCR_CWUF1_Pos (0U)
  3547. #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
  3548. #define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
  3549. #define PWR_SCR_CWUF2_Pos (1U)
  3550. #define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
  3551. #define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
  3552. #define PWR_SCR_CWUF4_Pos (3U)
  3553. #define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
  3554. #define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
  3555. #define PWR_SCR_CWUF6_Pos (5U)
  3556. #define PWR_SCR_CWUF6_Msk (0x1UL << PWR_SCR_CWUF6_Pos) /*!< 0x00000020 */
  3557. #define PWR_SCR_CWUF6 PWR_SCR_CWUF6_Msk /*!< Clear Wake-up Flag 6 */
  3558. #define PWR_SCR_CSBF_Pos (8U)
  3559. #define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
  3560. #define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Standby Flag */
  3561. /******************** Bit definition for PWR_PUCRA register *****************/
  3562. #define PWR_PUCRA_PU0_Pos (0U)
  3563. #define PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) /*!< 0x00000001 */
  3564. #define PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk /*!< Pin PA0 Pull-Up set */
  3565. #define PWR_PUCRA_PU1_Pos (1U)
  3566. #define PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) /*!< 0x00000002 */
  3567. #define PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk /*!< Pin PA1 Pull-Up set */
  3568. #define PWR_PUCRA_PU2_Pos (2U)
  3569. #define PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) /*!< 0x00000004 */
  3570. #define PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk /*!< Pin PA2 Pull-Up set */
  3571. #define PWR_PUCRA_PU3_Pos (3U)
  3572. #define PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) /*!< 0x00000008 */
  3573. #define PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk /*!< Pin PA3 Pull-Up set */
  3574. #define PWR_PUCRA_PU4_Pos (4U)
  3575. #define PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) /*!< 0x00000010 */
  3576. #define PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk /*!< Pin PA4 Pull-Up set */
  3577. #define PWR_PUCRA_PU5_Pos (5U)
  3578. #define PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) /*!< 0x00000020 */
  3579. #define PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk /*!< Pin PA5 Pull-Up set */
  3580. #define PWR_PUCRA_PU6_Pos (6U)
  3581. #define PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) /*!< 0x00000040 */
  3582. #define PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk /*!< Pin PA6 Pull-Up set */
  3583. #define PWR_PUCRA_PU7_Pos (7U)
  3584. #define PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) /*!< 0x00000080 */
  3585. #define PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk /*!< Pin PA7 Pull-Up set */
  3586. #define PWR_PUCRA_PU8_Pos (8U)
  3587. #define PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) /*!< 0x00000100 */
  3588. #define PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk /*!< Pin PA8 Pull-Up set */
  3589. #define PWR_PUCRA_PU9_Pos (9U)
  3590. #define PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) /*!< 0x00000200 */
  3591. #define PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk /*!< Pin PA9 Pull-Up set */
  3592. #define PWR_PUCRA_PU10_Pos (10U)
  3593. #define PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) /*!< 0x00000400 */
  3594. #define PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk /*!< Pin PA10 Pull-Up set */
  3595. #define PWR_PUCRA_PU11_Pos (11U)
  3596. #define PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) /*!< 0x00000800 */
  3597. #define PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk /*!< Pin PA11 Pull-Up set */
  3598. #define PWR_PUCRA_PU12_Pos (12U)
  3599. #define PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) /*!< 0x00001000 */
  3600. #define PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk /*!< Pin PA12 Pull-Up set */
  3601. #define PWR_PUCRA_PU13_Pos (13U)
  3602. #define PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) /*!< 0x00002000 */
  3603. #define PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk /*!< Pin PA13 Pull-Up set */
  3604. #define PWR_PUCRA_PU14_Pos (14U)
  3605. #define PWR_PUCRA_PU14_Msk (0x1UL << PWR_PUCRA_PU14_Pos) /*!< 0x00004000 */
  3606. #define PWR_PUCRA_PU14 PWR_PUCRA_PU14_Msk /*!< Pin PA14 Pull-Up set */
  3607. #define PWR_PUCRA_PU15_Pos (15U)
  3608. #define PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) /*!< 0x00008000 */
  3609. #define PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk /*!< Pin PA15 Pull-Up set */
  3610. /******************** Bit definition for PWR_PDCRA register *****************/
  3611. #define PWR_PDCRA_PD0_Pos (0U)
  3612. #define PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) /*!< 0x00000001 */
  3613. #define PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk /*!< Pin PA0 Pull-Down set */
  3614. #define PWR_PDCRA_PD1_Pos (1U)
  3615. #define PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) /*!< 0x00000002 */
  3616. #define PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk /*!< Pin PA1 Pull-Down set */
  3617. #define PWR_PDCRA_PD2_Pos (2U)
  3618. #define PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) /*!< 0x00000004 */
  3619. #define PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk /*!< Pin PA2 Pull-Down set */
  3620. #define PWR_PDCRA_PD3_Pos (3U)
  3621. #define PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) /*!< 0x00000008 */
  3622. #define PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk /*!< Pin PA3 Pull-Down set */
  3623. #define PWR_PDCRA_PD4_Pos (4U)
  3624. #define PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) /*!< 0x00000010 */
  3625. #define PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk /*!< Pin PA4 Pull-Down set */
  3626. #define PWR_PDCRA_PD5_Pos (5U)
  3627. #define PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) /*!< 0x00000020 */
  3628. #define PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk /*!< Pin PA5 Pull-Down set */
  3629. #define PWR_PDCRA_PD6_Pos (6U)
  3630. #define PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) /*!< 0x00000040 */
  3631. #define PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk /*!< Pin PA6 Pull-Down set */
  3632. #define PWR_PDCRA_PD7_Pos (7U)
  3633. #define PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) /*!< 0x00000080 */
  3634. #define PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk /*!< Pin PA7 Pull-Down set */
  3635. #define PWR_PDCRA_PD8_Pos (8U)
  3636. #define PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) /*!< 0x00000100 */
  3637. #define PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk /*!< Pin PA8 Pull-Down set */
  3638. #define PWR_PDCRA_PD9_Pos (9U)
  3639. #define PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) /*!< 0x00000200 */
  3640. #define PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk /*!< Pin PA9 Pull-Down set */
  3641. #define PWR_PDCRA_PD10_Pos (10U)
  3642. #define PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) /*!< 0x00000400 */
  3643. #define PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk /*!< Pin PA10 Pull-Down set */
  3644. #define PWR_PDCRA_PD11_Pos (11U)
  3645. #define PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) /*!< 0x00000800 */
  3646. #define PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk /*!< Pin PA11 Pull-Down set */
  3647. #define PWR_PDCRA_PD12_Pos (12U)
  3648. #define PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) /*!< 0x00001000 */
  3649. #define PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk /*!< Pin PA12 Pull-Down set */
  3650. #define PWR_PDCRA_PD13_Pos (13U)
  3651. #define PWR_PDCRA_PD13_Msk (0x1UL << PWR_PDCRA_PD13_Pos) /*!< 0x00002000 */
  3652. #define PWR_PDCRA_PD13 PWR_PDCRA_PD13_Msk /*!< Pin PA13 Pull-Down set */
  3653. #define PWR_PDCRA_PD14_Pos (14U)
  3654. #define PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) /*!< 0x00004000 */
  3655. #define PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk /*!< Pin PA14 Pull-Down set */
  3656. #define PWR_PDCRA_PD15_Pos (15U)
  3657. #define PWR_PDCRA_PD15_Msk (0x1UL << PWR_PDCRA_PD15_Pos) /*!< 0x00008000 */
  3658. #define PWR_PDCRA_PD15 PWR_PDCRA_PD15_Msk /*!< Pin PA15 Pull-Down set */
  3659. /******************** Bit definition for PWR_PUCRB register *****************/
  3660. #define PWR_PUCRB_PU0_Pos (0U)
  3661. #define PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) /*!< 0x00000001 */
  3662. #define PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk /*!< Pin PB0 Pull-Up set */
  3663. #define PWR_PUCRB_PU1_Pos (1U)
  3664. #define PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) /*!< 0x00000002 */
  3665. #define PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk /*!< Pin PB1 Pull-Up set */
  3666. #define PWR_PUCRB_PU2_Pos (2U)
  3667. #define PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) /*!< 0x00000004 */
  3668. #define PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk /*!< Pin PB2 Pull-Up set */
  3669. #define PWR_PUCRB_PU3_Pos (3U)
  3670. #define PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) /*!< 0x00000008 */
  3671. #define PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk /*!< Pin PB3 Pull-Up set */
  3672. #define PWR_PUCRB_PU4_Pos (4U)
  3673. #define PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) /*!< 0x00000010 */
  3674. #define PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk /*!< Pin PB4 Pull-Up set */
  3675. #define PWR_PUCRB_PU5_Pos (5U)
  3676. #define PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) /*!< 0x00000020 */
  3677. #define PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk /*!< Pin PB5 Pull-Up set */
  3678. #define PWR_PUCRB_PU6_Pos (6U)
  3679. #define PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) /*!< 0x00000040 */
  3680. #define PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk /*!< Pin PB6 Pull-Up set */
  3681. #define PWR_PUCRB_PU7_Pos (7U)
  3682. #define PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) /*!< 0x00000080 */
  3683. #define PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk /*!< Pin PB7 Pull-Up set */
  3684. #define PWR_PUCRB_PU8_Pos (8U)
  3685. #define PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) /*!< 0x00000100 */
  3686. #define PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk /*!< Pin PB8 Pull-Up set */
  3687. #define PWR_PUCRB_PU9_Pos (9U)
  3688. #define PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) /*!< 0x00000200 */
  3689. #define PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk /*!< Pin PB9 Pull-Up set */
  3690. #define PWR_PUCRB_PU10_Pos (10U)
  3691. #define PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) /*!< 0x00000400 */
  3692. #define PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk /*!< Pin PB10 Pull-Up set */
  3693. #define PWR_PUCRB_PU11_Pos (11U)
  3694. #define PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) /*!< 0x00000800 */
  3695. #define PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk /*!< Pin PB11 Pull-Up set */
  3696. #define PWR_PUCRB_PU12_Pos (12U)
  3697. #define PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) /*!< 0x00001000 */
  3698. #define PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk /*!< Pin PB12 Pull-Up set */
  3699. #define PWR_PUCRB_PU13_Pos (13U)
  3700. #define PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) /*!< 0x00002000 */
  3701. #define PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk /*!< Pin PB13 Pull-Up set */
  3702. #define PWR_PUCRB_PU14_Pos (14U)
  3703. #define PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) /*!< 0x00004000 */
  3704. #define PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk /*!< Pin PB14 Pull-Up set */
  3705. #define PWR_PUCRB_PU15_Pos (15U)
  3706. #define PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) /*!< 0x00008000 */
  3707. #define PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk /*!< Pin PB15 Pull-Up set */
  3708. /******************** Bit definition for PWR_PDCRB register *****************/
  3709. #define PWR_PDCRB_PD0_Pos (0U)
  3710. #define PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) /*!< 0x00000001 */
  3711. #define PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk /*!< Pin PB0 Pull-Down set */
  3712. #define PWR_PDCRB_PD1_Pos (1U)
  3713. #define PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) /*!< 0x00000002 */
  3714. #define PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk /*!< Pin PB1 Pull-Down set */
  3715. #define PWR_PDCRB_PD2_Pos (2U)
  3716. #define PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) /*!< 0x00000004 */
  3717. #define PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk /*!< Pin PB2 Pull-Down set */
  3718. #define PWR_PDCRB_PD3_Pos (3U)
  3719. #define PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) /*!< 0x00000008 */
  3720. #define PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk /*!< Pin PB3 Pull-Down set */
  3721. #define PWR_PDCRB_PD4_Pos (4U)
  3722. #define PWR_PDCRB_PD4_Msk (0x1UL << PWR_PDCRB_PD4_Pos) /*!< 0x00000010 */
  3723. #define PWR_PDCRB_PD4 PWR_PDCRB_PD4_Msk /*!< Pin PB4 Pull-Down set */
  3724. #define PWR_PDCRB_PD5_Pos (5U)
  3725. #define PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) /*!< 0x00000020 */
  3726. #define PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk /*!< Pin PB5 Pull-Down set */
  3727. #define PWR_PDCRB_PD6_Pos (6U)
  3728. #define PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) /*!< 0x00000040 */
  3729. #define PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk /*!< Pin PB6 Pull-Down set */
  3730. #define PWR_PDCRB_PD7_Pos (7U)
  3731. #define PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) /*!< 0x00000080 */
  3732. #define PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk /*!< Pin PB7 Pull-Down set */
  3733. #define PWR_PDCRB_PD8_Pos (8U)
  3734. #define PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) /*!< 0x00000100 */
  3735. #define PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk /*!< Pin PB8 Pull-Down set */
  3736. #define PWR_PDCRB_PD9_Pos (9U)
  3737. #define PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) /*!< 0x00000200 */
  3738. #define PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk /*!< Pin PB9 Pull-Down set */
  3739. #define PWR_PDCRB_PD10_Pos (10U)
  3740. #define PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) /*!< 0x00000400 */
  3741. #define PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk /*!< Pin PB10 Pull-Down set */
  3742. #define PWR_PDCRB_PD11_Pos (11U)
  3743. #define PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) /*!< 0x00000800 */
  3744. #define PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk /*!< Pin PB11 Pull-Down set */
  3745. #define PWR_PDCRB_PD12_Pos (12U)
  3746. #define PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) /*!< 0x00001000 */
  3747. #define PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk /*!< Pin PB12 Pull-Down set */
  3748. #define PWR_PDCRB_PD13_Pos (13U)
  3749. #define PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) /*!< 0x00002000 */
  3750. #define PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk /*!< Pin PB13 Pull-Down set */
  3751. #define PWR_PDCRB_PD14_Pos (14U)
  3752. #define PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) /*!< 0x00004000 */
  3753. #define PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk /*!< Pin PB14 Pull-Down set */
  3754. #define PWR_PDCRB_PD15_Pos (15U)
  3755. #define PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) /*!< 0x00008000 */
  3756. #define PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk /*!< Pin PB15 Pull-Down set */
  3757. /******************** Bit definition for PWR_PUCRC register *****************/
  3758. #define PWR_PUCRC_PU6_Pos (6U)
  3759. #define PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) /*!< 0x00000040 */
  3760. #define PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk /*!< Pin PC6 Pull-Up set */
  3761. #define PWR_PUCRC_PU7_Pos (7U)
  3762. #define PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) /*!< 0x00000080 */
  3763. #define PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk /*!< Pin PC7 Pull-Up set */
  3764. #define PWR_PUCRC_PU13_Pos (13U)
  3765. #define PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) /*!< 0x00002000 */
  3766. #define PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk /*!< Pin PC13 Pull-Up set */
  3767. #define PWR_PUCRC_PU14_Pos (14U)
  3768. #define PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) /*!< 0x00004000 */
  3769. #define PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk /*!< Pin PC14 Pull-Up set */
  3770. #define PWR_PUCRC_PU15_Pos (15U)
  3771. #define PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) /*!< 0x00008000 */
  3772. #define PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk /*!< Pin PC15 Pull-Up set */
  3773. /******************** Bit definition for PWR_PDCRC register *****************/
  3774. #define PWR_PDCRC_PD6_Pos (6U)
  3775. #define PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) /*!< 0x00000040 */
  3776. #define PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk /*!< Pin PC6 Pull-Down set */
  3777. #define PWR_PDCRC_PD7_Pos (7U)
  3778. #define PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) /*!< 0x00000080 */
  3779. #define PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk /*!< Pin PC7 Pull-Down set */
  3780. #define PWR_PDCRC_PD13_Pos (13U)
  3781. #define PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) /*!< 0x00002000 */
  3782. #define PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk /*!< Pin PC13 Pull-Down set */
  3783. #define PWR_PDCRC_PD14_Pos (14U)
  3784. #define PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) /*!< 0x00004000 */
  3785. #define PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk /*!< Pin PC14 Pull-Down set */
  3786. #define PWR_PDCRC_PD15_Pos (15U)
  3787. #define PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) /*!< 0x00008000 */
  3788. #define PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk /*!< Pin PC15 Pull-Down set */
  3789. /******************** Bit definition for PWR_PUCRD register *****************/
  3790. #define PWR_PUCRD_PU0_Pos (0U)
  3791. #define PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) /*!< 0x00000001 */
  3792. #define PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk /*!< Pin PD0 Pull-Up set */
  3793. #define PWR_PUCRD_PU1_Pos (1U)
  3794. #define PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) /*!< 0x00000002 */
  3795. #define PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk /*!< Pin PD1 Pull-Up set */
  3796. #define PWR_PUCRD_PU2_Pos (2U)
  3797. #define PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) /*!< 0x00000004 */
  3798. #define PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk /*!< Pin PD2 Pull-Up set */
  3799. #define PWR_PUCRD_PU3_Pos (3U)
  3800. #define PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) /*!< 0x00000008 */
  3801. #define PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk /*!< Pin PD3 Pull-Up set */
  3802. /******************** Bit definition for PWR_PDCRD register *****************/
  3803. #define PWR_PDCRD_PD0_Pos (0U)
  3804. #define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
  3805. #define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Pin PD0 Pull-Down set */
  3806. #define PWR_PDCRD_PD1_Pos (1U)
  3807. #define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
  3808. #define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Pin PD1 Pull-Down set */
  3809. #define PWR_PDCRD_PD2_Pos (2U)
  3810. #define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
  3811. #define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Pin PD2 Pull-Down set */
  3812. #define PWR_PDCRD_PD3_Pos (3U)
  3813. #define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
  3814. #define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Pin PD3 Pull-Down set */
  3815. /******************** Bit definition for PWR_PUCRF register *****************/
  3816. #define PWR_PUCRF_PU0_Pos (0U)
  3817. #define PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) /*!< 0x00000001 */
  3818. #define PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk /*!< Pin PF0 Pull-Up set */
  3819. #define PWR_PUCRF_PU1_Pos (1U)
  3820. #define PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) /*!< 0x00000002 */
  3821. #define PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk /*!< Pin PF1 Pull-Up set */
  3822. #define PWR_PUCRF_PU2_Pos (2U)
  3823. #define PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) /*!< 0x00000004 */
  3824. #define PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk /*!< Pin PF2 Pull-Up set */
  3825. /******************** Bit definition for PWR_PDCRF register *****************/
  3826. #define PWR_PDCRF_PD0_Pos (0U)
  3827. #define PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) /*!< 0x00000001 */
  3828. #define PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk /*!< Pin PF0 Pull-Down set */
  3829. #define PWR_PDCRF_PD1_Pos (1U)
  3830. #define PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) /*!< 0x00000002 */
  3831. #define PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk /*!< Pin PF1 Pull-Down set */
  3832. #define PWR_PDCRF_PD2_Pos (2U)
  3833. #define PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) /*!< 0x00000004 */
  3834. #define PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk /*!< Pin PF2 Pull-Down set */
  3835. /******************************************************************************/
  3836. /* */
  3837. /* Reset and Clock Control */
  3838. /* */
  3839. /******************************************************************************/
  3840. /*
  3841. * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
  3842. */
  3843. #define RCC_PLLQ_SUPPORT
  3844. /******************** Bit definition for RCC_CR register *****************/
  3845. #define RCC_CR_HSION_Pos (8U)
  3846. #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
  3847. #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
  3848. #define RCC_CR_HSIKERON_Pos (9U)
  3849. #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
  3850. #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
  3851. #define RCC_CR_HSIRDY_Pos (10U)
  3852. #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
  3853. #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
  3854. #define RCC_CR_HSIDIV_Pos (11U)
  3855. #define RCC_CR_HSIDIV_Msk (0x7UL << RCC_CR_HSIDIV_Pos) /*!< 0x00003800 */
  3856. #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< HSIDIV[13:11] Internal High Speed clock division factor */
  3857. #define RCC_CR_HSIDIV_0 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000800 */
  3858. #define RCC_CR_HSIDIV_1 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00001000 */
  3859. #define RCC_CR_HSIDIV_2 (0x4UL << RCC_CR_HSIDIV_Pos) /*!< 0x00002000 */
  3860. #define RCC_CR_HSEON_Pos (16U)
  3861. #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
  3862. #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
  3863. #define RCC_CR_HSERDY_Pos (17U)
  3864. #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
  3865. #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
  3866. #define RCC_CR_HSEBYP_Pos (18U)
  3867. #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
  3868. #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
  3869. #define RCC_CR_CSSON_Pos (19U)
  3870. #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
  3871. #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
  3872. #define RCC_CR_PLLON_Pos (24U)
  3873. #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
  3874. #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
  3875. #define RCC_CR_PLLRDY_Pos (25U)
  3876. #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
  3877. #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
  3878. /******************** Bit definition for RCC_ICSCR register ***************/
  3879. /*!< HSICAL configuration */
  3880. #define RCC_ICSCR_HSICAL_Pos (0U)
  3881. #define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
  3882. #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
  3883. #define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000001 */
  3884. #define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000002 */
  3885. #define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000004 */
  3886. #define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000008 */
  3887. #define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000010 */
  3888. #define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000020 */
  3889. #define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000040 */
  3890. #define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00000080 */
  3891. /*!< HSITRIM configuration */
  3892. #define RCC_ICSCR_HSITRIM_Pos (8U)
  3893. #define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00007F00 */
  3894. #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[14:8] bits */
  3895. #define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000100 */
  3896. #define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000200 */
  3897. #define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000400 */
  3898. #define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00000800 */
  3899. #define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001000 */
  3900. #define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00002000 */
  3901. #define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00004000 */
  3902. /******************** Bit definition for RCC_CFGR register ***************/
  3903. /*!< SW configuration */
  3904. #define RCC_CFGR_SW_Pos (0U)
  3905. #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
  3906. #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
  3907. #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
  3908. #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
  3909. #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
  3910. /*!< SWS configuration */
  3911. #define RCC_CFGR_SWS_Pos (3U)
  3912. #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
  3913. #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
  3914. #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
  3915. #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
  3916. #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
  3917. #define RCC_CFGR_SWS_HSI (0UL) /*!< HSI used as system clock */
  3918. #define RCC_CFGR_SWS_HSE (0x00000008UL) /*!< HSE used as system clock */
  3919. #define RCC_CFGR_SWS_PLL (0x00000010UL) /*!< PLL used as system clock */
  3920. #define RCC_CFGR_SWS_LSI (0x00000018UL) /*!< LSI used as system clock */
  3921. #define RCC_CFGR_SWS_LSE (0x00000020UL) /*!< LSE used as system clock */
  3922. /*!< HPRE configuration */
  3923. #define RCC_CFGR_HPRE_Pos (8U)
  3924. #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x00000F00 */
  3925. #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
  3926. #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000100 */
  3927. #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000200 */
  3928. #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000400 */
  3929. #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000800 */
  3930. /*!< PPRE configuration */
  3931. #define RCC_CFGR_PPRE_Pos (12U)
  3932. #define RCC_CFGR_PPRE_Msk (0x7UL << RCC_CFGR_PPRE_Pos) /*!< 0x00007000 */
  3933. #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE1[2:0] bits (APB prescaler) */
  3934. #define RCC_CFGR_PPRE_0 (0x1UL << RCC_CFGR_PPRE_Pos) /*!< 0x00001000 */
  3935. #define RCC_CFGR_PPRE_1 (0x2UL << RCC_CFGR_PPRE_Pos) /*!< 0x00002000 */
  3936. #define RCC_CFGR_PPRE_2 (0x4UL << RCC_CFGR_PPRE_Pos) /*!< 0x00004000 */
  3937. /*!< MCOSEL configuration */
  3938. #define RCC_CFGR_MCOSEL_Pos (24U)
  3939. #define RCC_CFGR_MCOSEL_Msk (0x7UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
  3940. #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [2:0] bits (Clock output selection) */
  3941. #define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
  3942. #define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
  3943. #define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
  3944. /*!< MCO Prescaler configuration */
  3945. #define RCC_CFGR_MCOPRE_Pos (28U)
  3946. #define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
  3947. #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler [2:0] */
  3948. #define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
  3949. #define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
  3950. #define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
  3951. /******************** Bit definition for RCC_PLLCFGR register ***************/
  3952. #define RCC_PLLCFGR_PLLSRC_Pos (0U)
  3953. #define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
  3954. #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
  3955. #define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
  3956. #define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
  3957. #define RCC_PLLCFGR_PLLSRC_NONE (0x00000000UL) /*!< No clock sent to PLL */
  3958. #define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
  3959. #define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos) /*!< 0x00000002 */
  3960. #define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI source clock selected */
  3961. #define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
  3962. #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00000003 */
  3963. #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
  3964. #define RCC_PLLCFGR_PLLM_Pos (4U)
  3965. #define RCC_PLLCFGR_PLLM_Msk (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
  3966. #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
  3967. #define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
  3968. #define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
  3969. #define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
  3970. #define RCC_PLLCFGR_PLLN_Pos (8U)
  3971. #define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
  3972. #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
  3973. #define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
  3974. #define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
  3975. #define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
  3976. #define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
  3977. #define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
  3978. #define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
  3979. #define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
  3980. #define RCC_PLLCFGR_PLLPEN_Pos (16U)
  3981. #define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
  3982. #define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
  3983. #define RCC_PLLCFGR_PLLP_Pos (17U)
  3984. #define RCC_PLLCFGR_PLLP_Msk (0x1FUL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x003E0000 */
  3985. #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
  3986. #define RCC_PLLCFGR_PLLP_0 (0x01UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
  3987. #define RCC_PLLCFGR_PLLP_1 (0x02UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00040000 */
  3988. #define RCC_PLLCFGR_PLLP_2 (0x04UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00080000 */
  3989. #define RCC_PLLCFGR_PLLP_3 (0x08UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00100000 */
  3990. #define RCC_PLLCFGR_PLLP_4 (0x10UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00200000 */
  3991. #define RCC_PLLCFGR_PLLQEN_Pos (24U)
  3992. #define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x01000000 */
  3993. #define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
  3994. #define RCC_PLLCFGR_PLLQ_Pos (25U)
  3995. #define RCC_PLLCFGR_PLLQ_Msk (0x7UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0E000000 */
  3996. #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
  3997. #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
  3998. #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
  3999. #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
  4000. #define RCC_PLLCFGR_PLLREN_Pos (28U)
  4001. #define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x10000000 */
  4002. #define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
  4003. #define RCC_PLLCFGR_PLLR_Pos (29U)
  4004. #define RCC_PLLCFGR_PLLR_Msk (0x7UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0xE0000000 */
  4005. #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
  4006. #define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
  4007. #define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
  4008. #define RCC_PLLCFGR_PLLR_2 (0x4UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x80000000 */
  4009. /******************** Bit definition for RCC_CIER register ******************/
  4010. #define RCC_CIER_LSIRDYIE_Pos (0U)
  4011. #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
  4012. #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
  4013. #define RCC_CIER_LSERDYIE_Pos (1U)
  4014. #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
  4015. #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
  4016. #define RCC_CIER_HSIRDYIE_Pos (3U)
  4017. #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
  4018. #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
  4019. #define RCC_CIER_HSERDYIE_Pos (4U)
  4020. #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
  4021. #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
  4022. #define RCC_CIER_PLLRDYIE_Pos (5U)
  4023. #define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
  4024. #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
  4025. /******************** Bit definition for RCC_CIFR register ******************/
  4026. #define RCC_CIFR_LSIRDYF_Pos (0U)
  4027. #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
  4028. #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
  4029. #define RCC_CIFR_LSERDYF_Pos (1U)
  4030. #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
  4031. #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
  4032. #define RCC_CIFR_HSIRDYF_Pos (3U)
  4033. #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
  4034. #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
  4035. #define RCC_CIFR_HSERDYF_Pos (4U)
  4036. #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
  4037. #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
  4038. #define RCC_CIFR_PLLRDYF_Pos (5U)
  4039. #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
  4040. #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
  4041. #define RCC_CIFR_CSSF_Pos (8U)
  4042. #define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
  4043. #define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
  4044. #define RCC_CIFR_LSECSSF_Pos (9U)
  4045. #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
  4046. #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
  4047. /******************** Bit definition for RCC_CICR register ******************/
  4048. #define RCC_CICR_LSIRDYC_Pos (0U)
  4049. #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
  4050. #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
  4051. #define RCC_CICR_LSERDYC_Pos (1U)
  4052. #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
  4053. #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
  4054. #define RCC_CICR_HSIRDYC_Pos (3U)
  4055. #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
  4056. #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
  4057. #define RCC_CICR_HSERDYC_Pos (4U)
  4058. #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
  4059. #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
  4060. #define RCC_CICR_PLLRDYC_Pos (5U)
  4061. #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
  4062. #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
  4063. #define RCC_CICR_CSSC_Pos (8U)
  4064. #define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
  4065. #define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
  4066. #define RCC_CICR_LSECSSC_Pos (9U)
  4067. #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
  4068. #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
  4069. /******************** Bit definition for RCC_IOPRSTR register ****************/
  4070. #define RCC_IOPRSTR_GPIOARST_Pos (0U)
  4071. #define RCC_IOPRSTR_GPIOARST_Msk (0x1UL << RCC_IOPRSTR_GPIOARST_Pos) /*!< 0x00000001 */
  4072. #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_GPIOARST_Msk
  4073. #define RCC_IOPRSTR_GPIOBRST_Pos (1U)
  4074. #define RCC_IOPRSTR_GPIOBRST_Msk (0x1UL << RCC_IOPRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
  4075. #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_GPIOBRST_Msk
  4076. #define RCC_IOPRSTR_GPIOCRST_Pos (2U)
  4077. #define RCC_IOPRSTR_GPIOCRST_Msk (0x1UL << RCC_IOPRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
  4078. #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_GPIOCRST_Msk
  4079. #define RCC_IOPRSTR_GPIODRST_Pos (3U)
  4080. #define RCC_IOPRSTR_GPIODRST_Msk (0x1UL << RCC_IOPRSTR_GPIODRST_Pos) /*!< 0x00000008 */
  4081. #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_GPIODRST_Msk
  4082. #define RCC_IOPRSTR_GPIOFRST_Pos (5U)
  4083. #define RCC_IOPRSTR_GPIOFRST_Msk (0x1UL << RCC_IOPRSTR_GPIOFRST_Pos) /*!< 0x00000020 */
  4084. #define RCC_IOPRSTR_GPIOFRST RCC_IOPRSTR_GPIOFRST_Msk
  4085. /******************** Bit definition for RCC_AHBRSTR register ***************/
  4086. #define RCC_AHBRSTR_DMA1RST_Pos (0U)
  4087. #define RCC_AHBRSTR_DMA1RST_Msk (0x1UL << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x00000001 */
  4088. #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk
  4089. #define RCC_AHBRSTR_FLASHRST_Pos (8U)
  4090. #define RCC_AHBRSTR_FLASHRST_Msk (0x1UL << RCC_AHBRSTR_FLASHRST_Pos) /*!< 0x00000100 */
  4091. #define RCC_AHBRSTR_FLASHRST RCC_AHBRSTR_FLASHRST_Msk
  4092. #define RCC_AHBRSTR_CRCRST_Pos (12U)
  4093. #define RCC_AHBRSTR_CRCRST_Msk (0x1UL << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
  4094. #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk
  4095. /******************** Bit definition for RCC_APBRSTR1 register **************/
  4096. #define RCC_APBRSTR1_TIM2RST_Pos (0U)
  4097. #define RCC_APBRSTR1_TIM2RST_Msk (0x1UL << RCC_APBRSTR1_TIM2RST_Pos) /*!< 0x00000001 */
  4098. #define RCC_APBRSTR1_TIM2RST RCC_APBRSTR1_TIM2RST_Msk
  4099. #define RCC_APBRSTR1_TIM3RST_Pos (1U)
  4100. #define RCC_APBRSTR1_TIM3RST_Msk (0x1UL << RCC_APBRSTR1_TIM3RST_Pos) /*!< 0x00000002 */
  4101. #define RCC_APBRSTR1_TIM3RST RCC_APBRSTR1_TIM3RST_Msk
  4102. #define RCC_APBRSTR1_SPI2RST_Pos (14U)
  4103. #define RCC_APBRSTR1_SPI2RST_Msk (0x1UL << RCC_APBRSTR1_SPI2RST_Pos) /*!< 0x00004000 */
  4104. #define RCC_APBRSTR1_SPI2RST RCC_APBRSTR1_SPI2RST_Msk
  4105. #define RCC_APBRSTR1_USART2RST_Pos (17U)
  4106. #define RCC_APBRSTR1_USART2RST_Msk (0x1UL << RCC_APBRSTR1_USART2RST_Pos) /*!< 0x00020000 */
  4107. #define RCC_APBRSTR1_USART2RST RCC_APBRSTR1_USART2RST_Msk
  4108. #define RCC_APBRSTR1_LPUART1RST_Pos (20U)
  4109. #define RCC_APBRSTR1_LPUART1RST_Msk (0x1UL << RCC_APBRSTR1_LPUART1RST_Pos) /*!< 0x00100000 */
  4110. #define RCC_APBRSTR1_LPUART1RST RCC_APBRSTR1_LPUART1RST_Msk
  4111. #define RCC_APBRSTR1_I2C1RST_Pos (21U)
  4112. #define RCC_APBRSTR1_I2C1RST_Msk (0x1UL << RCC_APBRSTR1_I2C1RST_Pos) /*!< 0x00200000 */
  4113. #define RCC_APBRSTR1_I2C1RST RCC_APBRSTR1_I2C1RST_Msk
  4114. #define RCC_APBRSTR1_I2C2RST_Pos (22U)
  4115. #define RCC_APBRSTR1_I2C2RST_Msk (0x1UL << RCC_APBRSTR1_I2C2RST_Pos) /*!< 0x00400000 */
  4116. #define RCC_APBRSTR1_I2C2RST RCC_APBRSTR1_I2C2RST_Msk
  4117. #define RCC_APBRSTR1_DBGRST_Pos (27U)
  4118. #define RCC_APBRSTR1_DBGRST_Msk (0x1UL << RCC_APBRSTR1_DBGRST_Pos) /*!< 0x08000000 */
  4119. #define RCC_APBRSTR1_DBGRST RCC_APBRSTR1_DBGRST_Msk
  4120. #define RCC_APBRSTR1_PWRRST_Pos (28U)
  4121. #define RCC_APBRSTR1_PWRRST_Msk (0x1UL << RCC_APBRSTR1_PWRRST_Pos) /*!< 0x10000000 */
  4122. #define RCC_APBRSTR1_PWRRST RCC_APBRSTR1_PWRRST_Msk
  4123. #define RCC_APBRSTR1_LPTIM2RST_Pos (30U)
  4124. #define RCC_APBRSTR1_LPTIM2RST_Msk (0x1UL << RCC_APBRSTR1_LPTIM2RST_Pos) /*!< 0x40000000 */
  4125. #define RCC_APBRSTR1_LPTIM2RST RCC_APBRSTR1_LPTIM2RST_Msk
  4126. #define RCC_APBRSTR1_LPTIM1RST_Pos (31U)
  4127. #define RCC_APBRSTR1_LPTIM1RST_Msk (0x1UL << RCC_APBRSTR1_LPTIM1RST_Pos) /*!< 0x80000000 */
  4128. #define RCC_APBRSTR1_LPTIM1RST RCC_APBRSTR1_LPTIM1RST_Msk
  4129. /******************** Bit definition for RCC_APBRSTR2 register **************/
  4130. #define RCC_APBRSTR2_SYSCFGRST_Pos (0U)
  4131. #define RCC_APBRSTR2_SYSCFGRST_Msk (0x1UL << RCC_APBRSTR2_SYSCFGRST_Pos) /*!< 0x00000001 */
  4132. #define RCC_APBRSTR2_SYSCFGRST RCC_APBRSTR2_SYSCFGRST_Msk
  4133. #define RCC_APBRSTR2_TIM1RST_Pos (11U)
  4134. #define RCC_APBRSTR2_TIM1RST_Msk (0x1UL << RCC_APBRSTR2_TIM1RST_Pos) /*!< 0x00000800 */
  4135. #define RCC_APBRSTR2_TIM1RST RCC_APBRSTR2_TIM1RST_Msk
  4136. #define RCC_APBRSTR2_SPI1RST_Pos (12U)
  4137. #define RCC_APBRSTR2_SPI1RST_Msk (0x1UL << RCC_APBRSTR2_SPI1RST_Pos) /*!< 0x00001000 */
  4138. #define RCC_APBRSTR2_SPI1RST RCC_APBRSTR2_SPI1RST_Msk
  4139. #define RCC_APBRSTR2_USART1RST_Pos (14U)
  4140. #define RCC_APBRSTR2_USART1RST_Msk (0x1UL << RCC_APBRSTR2_USART1RST_Pos) /*!< 0x00004000 */
  4141. #define RCC_APBRSTR2_USART1RST RCC_APBRSTR2_USART1RST_Msk
  4142. #define RCC_APBRSTR2_TIM14RST_Pos (15U)
  4143. #define RCC_APBRSTR2_TIM14RST_Msk (0x1UL << RCC_APBRSTR2_TIM14RST_Pos) /*!< 0x00008000 */
  4144. #define RCC_APBRSTR2_TIM14RST RCC_APBRSTR2_TIM14RST_Msk
  4145. #define RCC_APBRSTR2_TIM16RST_Pos (17U)
  4146. #define RCC_APBRSTR2_TIM16RST_Msk (0x1UL << RCC_APBRSTR2_TIM16RST_Pos) /*!< 0x00020000 */
  4147. #define RCC_APBRSTR2_TIM16RST RCC_APBRSTR2_TIM16RST_Msk
  4148. #define RCC_APBRSTR2_TIM17RST_Pos (18U)
  4149. #define RCC_APBRSTR2_TIM17RST_Msk (0x1UL << RCC_APBRSTR2_TIM17RST_Pos) /*!< 0x00040000 */
  4150. #define RCC_APBRSTR2_TIM17RST RCC_APBRSTR2_TIM17RST_Msk
  4151. #define RCC_APBRSTR2_ADCRST_Pos (20U)
  4152. #define RCC_APBRSTR2_ADCRST_Msk (0x1UL << RCC_APBRSTR2_ADCRST_Pos) /*!< 0x00100000 */
  4153. #define RCC_APBRSTR2_ADCRST RCC_APBRSTR2_ADCRST_Msk
  4154. /******************** Bit definition for RCC_IOPENR register ****************/
  4155. #define RCC_IOPENR_GPIOAEN_Pos (0U)
  4156. #define RCC_IOPENR_GPIOAEN_Msk (0x1UL << RCC_IOPENR_GPIOAEN_Pos) /*!< 0x00000001 */
  4157. #define RCC_IOPENR_GPIOAEN RCC_IOPENR_GPIOAEN_Msk
  4158. #define RCC_IOPENR_GPIOBEN_Pos (1U)
  4159. #define RCC_IOPENR_GPIOBEN_Msk (0x1UL << RCC_IOPENR_GPIOBEN_Pos) /*!< 0x00000002 */
  4160. #define RCC_IOPENR_GPIOBEN RCC_IOPENR_GPIOBEN_Msk
  4161. #define RCC_IOPENR_GPIOCEN_Pos (2U)
  4162. #define RCC_IOPENR_GPIOCEN_Msk (0x1UL << RCC_IOPENR_GPIOCEN_Pos) /*!< 0x00000004 */
  4163. #define RCC_IOPENR_GPIOCEN RCC_IOPENR_GPIOCEN_Msk
  4164. #define RCC_IOPENR_GPIODEN_Pos (3U)
  4165. #define RCC_IOPENR_GPIODEN_Msk (0x1UL << RCC_IOPENR_GPIODEN_Pos) /*!< 0x00000008 */
  4166. #define RCC_IOPENR_GPIODEN RCC_IOPENR_GPIODEN_Msk
  4167. #define RCC_IOPENR_GPIOFEN_Pos (5U)
  4168. #define RCC_IOPENR_GPIOFEN_Msk (0x1UL << RCC_IOPENR_GPIOFEN_Pos) /*!< 0x00000020 */
  4169. #define RCC_IOPENR_GPIOFEN RCC_IOPENR_GPIOFEN_Msk
  4170. /******************** Bit definition for RCC_AHBENR register ****************/
  4171. #define RCC_AHBENR_DMA1EN_Pos (0U)
  4172. #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
  4173. #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
  4174. #define RCC_AHBENR_FLASHEN_Pos (8U)
  4175. #define RCC_AHBENR_FLASHEN_Msk (0x1UL << RCC_AHBENR_FLASHEN_Pos) /*!< 0x00000100 */
  4176. #define RCC_AHBENR_FLASHEN RCC_AHBENR_FLASHEN_Msk
  4177. #define RCC_AHBENR_CRCEN_Pos (12U)
  4178. #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
  4179. #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
  4180. /******************** Bit definition for RCC_APBENR1 register ***************/
  4181. #define RCC_APBENR1_TIM2EN_Pos (0U)
  4182. #define RCC_APBENR1_TIM2EN_Msk (0x1UL << RCC_APBENR1_TIM2EN_Pos) /*!< 0x00000001 */
  4183. #define RCC_APBENR1_TIM2EN RCC_APBENR1_TIM2EN_Msk
  4184. #define RCC_APBENR1_TIM3EN_Pos (1U)
  4185. #define RCC_APBENR1_TIM3EN_Msk (0x1UL << RCC_APBENR1_TIM3EN_Pos) /*!< 0x00000002 */
  4186. #define RCC_APBENR1_TIM3EN RCC_APBENR1_TIM3EN_Msk
  4187. #define RCC_APBENR1_RTCAPBEN_Pos (10U)
  4188. #define RCC_APBENR1_RTCAPBEN_Msk (0x1UL << RCC_APBENR1_RTCAPBEN_Pos) /*!< 0x00000400 */
  4189. #define RCC_APBENR1_RTCAPBEN RCC_APBENR1_RTCAPBEN_Msk
  4190. #define RCC_APBENR1_WWDGEN_Pos (11U)
  4191. #define RCC_APBENR1_WWDGEN_Msk (0x1UL << RCC_APBENR1_WWDGEN_Pos) /*!< 0x00000800 */
  4192. #define RCC_APBENR1_WWDGEN RCC_APBENR1_WWDGEN_Msk
  4193. #define RCC_APBENR1_SPI2EN_Pos (14U)
  4194. #define RCC_APBENR1_SPI2EN_Msk (0x1UL << RCC_APBENR1_SPI2EN_Pos) /*!< 0x00004000 */
  4195. #define RCC_APBENR1_SPI2EN RCC_APBENR1_SPI2EN_Msk
  4196. #define RCC_APBENR1_USART2EN_Pos (17U)
  4197. #define RCC_APBENR1_USART2EN_Msk (0x1UL << RCC_APBENR1_USART2EN_Pos) /*!< 0x00020000 */
  4198. #define RCC_APBENR1_USART2EN RCC_APBENR1_USART2EN_Msk
  4199. #define RCC_APBENR1_LPUART1EN_Pos (20U)
  4200. #define RCC_APBENR1_LPUART1EN_Msk (0x1UL << RCC_APBENR1_LPUART1EN_Pos) /*!< 0x00100000 */
  4201. #define RCC_APBENR1_LPUART1EN RCC_APBENR1_LPUART1EN_Msk
  4202. #define RCC_APBENR1_I2C1EN_Pos (21U)
  4203. #define RCC_APBENR1_I2C1EN_Msk (0x1UL << RCC_APBENR1_I2C1EN_Pos) /*!< 0x00200000 */
  4204. #define RCC_APBENR1_I2C1EN RCC_APBENR1_I2C1EN_Msk
  4205. #define RCC_APBENR1_I2C2EN_Pos (22U)
  4206. #define RCC_APBENR1_I2C2EN_Msk (0x1UL << RCC_APBENR1_I2C2EN_Pos) /*!< 0x00400000 */
  4207. #define RCC_APBENR1_I2C2EN RCC_APBENR1_I2C2EN_Msk
  4208. #define RCC_APBENR1_DBGEN_Pos (27U)
  4209. #define RCC_APBENR1_DBGEN_Msk (0x1UL << RCC_APBENR1_DBGEN_Pos) /*!< 0x08000000 */
  4210. #define RCC_APBENR1_DBGEN RCC_APBENR1_DBGEN_Msk
  4211. #define RCC_APBENR1_PWREN_Pos (28U)
  4212. #define RCC_APBENR1_PWREN_Msk (0x1UL << RCC_APBENR1_PWREN_Pos) /*!< 0x10000000 */
  4213. #define RCC_APBENR1_PWREN RCC_APBENR1_PWREN_Msk
  4214. #define RCC_APBENR1_LPTIM2EN_Pos (30U)
  4215. #define RCC_APBENR1_LPTIM2EN_Msk (0x1UL << RCC_APBENR1_LPTIM2EN_Pos) /*!< 0x40000000 */
  4216. #define RCC_APBENR1_LPTIM2EN RCC_APBENR1_LPTIM2EN_Msk
  4217. #define RCC_APBENR1_LPTIM1EN_Pos (31U)
  4218. #define RCC_APBENR1_LPTIM1EN_Msk (0x1UL << RCC_APBENR1_LPTIM1EN_Pos) /*!< 0x80000000 */
  4219. #define RCC_APBENR1_LPTIM1EN RCC_APBENR1_LPTIM1EN_Msk
  4220. /******************** Bit definition for RCC_APBENR2 register **************/
  4221. #define RCC_APBENR2_SYSCFGEN_Pos (0U)
  4222. #define RCC_APBENR2_SYSCFGEN_Msk (0x1UL << RCC_APBENR2_SYSCFGEN_Pos) /*!< 0x00000001 */
  4223. #define RCC_APBENR2_SYSCFGEN RCC_APBENR2_SYSCFGEN_Msk
  4224. #define RCC_APBENR2_TIM1EN_Pos (11U)
  4225. #define RCC_APBENR2_TIM1EN_Msk (0x1UL << RCC_APBENR2_TIM1EN_Pos) /*!< 0x00000800 */
  4226. #define RCC_APBENR2_TIM1EN RCC_APBENR2_TIM1EN_Msk
  4227. #define RCC_APBENR2_SPI1EN_Pos (12U)
  4228. #define RCC_APBENR2_SPI1EN_Msk (0x1UL << RCC_APBENR2_SPI1EN_Pos) /*!< 0x00001000 */
  4229. #define RCC_APBENR2_SPI1EN RCC_APBENR2_SPI1EN_Msk
  4230. #define RCC_APBENR2_USART1EN_Pos (14U)
  4231. #define RCC_APBENR2_USART1EN_Msk (0x1UL << RCC_APBENR2_USART1EN_Pos) /*!< 0x00004000 */
  4232. #define RCC_APBENR2_USART1EN RCC_APBENR2_USART1EN_Msk
  4233. #define RCC_APBENR2_TIM14EN_Pos (15U)
  4234. #define RCC_APBENR2_TIM14EN_Msk (0x1UL << RCC_APBENR2_TIM14EN_Pos) /*!< 0x00008000 */
  4235. #define RCC_APBENR2_TIM14EN RCC_APBENR2_TIM14EN_Msk
  4236. #define RCC_APBENR2_TIM16EN_Pos (17U)
  4237. #define RCC_APBENR2_TIM16EN_Msk (0x1UL << RCC_APBENR2_TIM16EN_Pos) /*!< 0x00020000 */
  4238. #define RCC_APBENR2_TIM16EN RCC_APBENR2_TIM16EN_Msk
  4239. #define RCC_APBENR2_TIM17EN_Pos (18U)
  4240. #define RCC_APBENR2_TIM17EN_Msk (0x1UL << RCC_APBENR2_TIM17EN_Pos) /*!< 0x00040000 */
  4241. #define RCC_APBENR2_TIM17EN RCC_APBENR2_TIM17EN_Msk
  4242. #define RCC_APBENR2_ADCEN_Pos (20U)
  4243. #define RCC_APBENR2_ADCEN_Msk (0x1UL << RCC_APBENR2_ADCEN_Pos) /*!< 0x00100000 */
  4244. #define RCC_APBENR2_ADCEN RCC_APBENR2_ADCEN_Msk
  4245. /******************** Bit definition for RCC_IOPSMENR register *************/
  4246. #define RCC_IOPSMENR_GPIOASMEN_Pos (0U)
  4247. #define RCC_IOPSMENR_GPIOASMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOASMEN_Pos) /*!< 0x00000001 */
  4248. #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_GPIOASMEN_Msk
  4249. #define RCC_IOPSMENR_GPIOBSMEN_Pos (1U)
  4250. #define RCC_IOPSMENR_GPIOBSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOBSMEN_Pos) /*!< 0x00000002 */
  4251. #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_GPIOBSMEN_Msk
  4252. #define RCC_IOPSMENR_GPIOCSMEN_Pos (2U)
  4253. #define RCC_IOPSMENR_GPIOCSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOCSMEN_Pos) /*!< 0x00000004 */
  4254. #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_GPIOCSMEN_Msk
  4255. #define RCC_IOPSMENR_GPIODSMEN_Pos (3U)
  4256. #define RCC_IOPSMENR_GPIODSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIODSMEN_Pos) /*!< 0x00000008 */
  4257. #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_GPIODSMEN_Msk
  4258. #define RCC_IOPSMENR_GPIOFSMEN_Pos (5U)
  4259. #define RCC_IOPSMENR_GPIOFSMEN_Msk (0x1UL << RCC_IOPSMENR_GPIOFSMEN_Pos) /*!< 0x00000020 */
  4260. #define RCC_IOPSMENR_GPIOFSMEN RCC_IOPSMENR_GPIOFSMEN_Msk
  4261. /******************** Bit definition for RCC_AHBSMENR register *************/
  4262. #define RCC_AHBSMENR_DMA1SMEN_Pos (0U)
  4263. #define RCC_AHBSMENR_DMA1SMEN_Msk (0x1UL << RCC_AHBSMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
  4264. #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMA1SMEN_Msk
  4265. #define RCC_AHBSMENR_FLASHSMEN_Pos (8U)
  4266. #define RCC_AHBSMENR_FLASHSMEN_Msk (0x1UL << RCC_AHBSMENR_FLASHSMEN_Pos) /*!< 0x00000100 */
  4267. #define RCC_AHBSMENR_FLASHSMEN RCC_AHBSMENR_FLASHSMEN_Msk
  4268. #define RCC_AHBSMENR_SRAMSMEN_Pos (9U)
  4269. #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1UL << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */
  4270. #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk
  4271. #define RCC_AHBSMENR_CRCSMEN_Pos (12U)
  4272. #define RCC_AHBSMENR_CRCSMEN_Msk (0x1UL << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */
  4273. #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk
  4274. /******************** Bit definition for RCC_APBSMENR1 register *************/
  4275. #define RCC_APBSMENR1_TIM2SMEN_Pos (0U)
  4276. #define RCC_APBSMENR1_TIM2SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM2SMEN_Pos) /*!< 0x00000001 */
  4277. #define RCC_APBSMENR1_TIM2SMEN RCC_APBSMENR1_TIM2SMEN_Msk
  4278. #define RCC_APBSMENR1_TIM3SMEN_Pos (1U)
  4279. #define RCC_APBSMENR1_TIM3SMEN_Msk (0x1UL << RCC_APBSMENR1_TIM3SMEN_Pos) /*!< 0x00000002 */
  4280. #define RCC_APBSMENR1_TIM3SMEN RCC_APBSMENR1_TIM3SMEN_Msk
  4281. #define RCC_APBSMENR1_RTCAPBSMEN_Pos (10U)
  4282. #define RCC_APBSMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APBSMENR1_RTCAPBSMEN_Pos) /*!< 0x00000400 */
  4283. #define RCC_APBSMENR1_RTCAPBSMEN RCC_APBSMENR1_RTCAPBSMEN_Msk
  4284. #define RCC_APBSMENR1_WWDGSMEN_Pos (11U)
  4285. #define RCC_APBSMENR1_WWDGSMEN_Msk (0x1UL << RCC_APBSMENR1_WWDGSMEN_Pos) /*!< 0x00000800 */
  4286. #define RCC_APBSMENR1_WWDGSMEN RCC_APBSMENR1_WWDGSMEN_Msk
  4287. #define RCC_APBSMENR1_SPI2SMEN_Pos (14U)
  4288. #define RCC_APBSMENR1_SPI2SMEN_Msk (0x1UL << RCC_APBSMENR1_SPI2SMEN_Pos) /*!< 0x00004000 */
  4289. #define RCC_APBSMENR1_SPI2SMEN RCC_APBSMENR1_SPI2SMEN_Msk
  4290. #define RCC_APBSMENR1_USART2SMEN_Pos (17U)
  4291. #define RCC_APBSMENR1_USART2SMEN_Msk (0x1UL << RCC_APBSMENR1_USART2SMEN_Pos) /*!< 0x00020000 */
  4292. #define RCC_APBSMENR1_USART2SMEN RCC_APBSMENR1_USART2SMEN_Msk
  4293. #define RCC_APBSMENR1_LPUART1SMEN_Pos (20U)
  4294. #define RCC_APBSMENR1_LPUART1SMEN_Msk (0x1UL << RCC_APBSMENR1_LPUART1SMEN_Pos) /*!< 0x00100000 */
  4295. #define RCC_APBSMENR1_LPUART1SMEN RCC_APBSMENR1_LPUART1SMEN_Msk
  4296. #define RCC_APBSMENR1_I2C1SMEN_Pos (21U)
  4297. #define RCC_APBSMENR1_I2C1SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C1SMEN_Pos) /*!< 0x00200000 */
  4298. #define RCC_APBSMENR1_I2C1SMEN RCC_APBSMENR1_I2C1SMEN_Msk
  4299. #define RCC_APBSMENR1_I2C2SMEN_Pos (22U)
  4300. #define RCC_APBSMENR1_I2C2SMEN_Msk (0x1UL << RCC_APBSMENR1_I2C2SMEN_Pos) /*!< 0x00400000 */
  4301. #define RCC_APBSMENR1_I2C2SMEN RCC_APBSMENR1_I2C2SMEN_Msk
  4302. #define RCC_APBSMENR1_DBGSMEN_Pos (27U)
  4303. #define RCC_APBSMENR1_DBGSMEN_Msk (0x1UL << RCC_APBSMENR1_DBGSMEN_Pos) /*!< 0x08000000 */
  4304. #define RCC_APBSMENR1_DBGSMEN RCC_APBSMENR1_DBGSMEN_Msk
  4305. #define RCC_APBSMENR1_PWRSMEN_Pos (28U)
  4306. #define RCC_APBSMENR1_PWRSMEN_Msk (0x1UL << RCC_APBSMENR1_PWRSMEN_Pos) /*!< 0x10000000 */
  4307. #define RCC_APBSMENR1_PWRSMEN RCC_APBSMENR1_PWRSMEN_Msk
  4308. #define RCC_APBSMENR1_LPTIM2SMEN_Pos (30U)
  4309. #define RCC_APBSMENR1_LPTIM2SMEN_Msk (0x1UL << RCC_APBSMENR1_LPTIM2SMEN_Pos) /*!< 0x40000000 */
  4310. #define RCC_APBSMENR1_LPTIM2SMEN RCC_APBSMENR1_LPTIM2SMEN_Msk
  4311. #define RCC_APBSMENR1_LPTIM1SMEN_Pos (31U)
  4312. #define RCC_APBSMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APBSMENR1_LPTIM1SMEN_Pos) /*!< 0x80000000 */
  4313. #define RCC_APBSMENR1_LPTIM1SMEN RCC_APBSMENR1_LPTIM1SMEN_Msk
  4314. /******************** Bit definition for RCC_APBSMENR2 register *************/
  4315. #define RCC_APBSMENR2_SYSCFGSMEN_Pos (0U)
  4316. #define RCC_APBSMENR2_SYSCFGSMEN_Msk (0x1UL << RCC_APBSMENR2_SYSCFGSMEN_Pos) /*!< 0x00000001 */
  4317. #define RCC_APBSMENR2_SYSCFGSMEN RCC_APBSMENR2_SYSCFGSMEN_Msk
  4318. #define RCC_APBSMENR2_TIM1SMEN_Pos (11U)
  4319. #define RCC_APBSMENR2_TIM1SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM1SMEN_Pos) /*!< 0x00000800 */
  4320. #define RCC_APBSMENR2_TIM1SMEN RCC_APBSMENR2_TIM1SMEN_Msk
  4321. #define RCC_APBSMENR2_SPI1SMEN_Pos (12U)
  4322. #define RCC_APBSMENR2_SPI1SMEN_Msk (0x1UL << RCC_APBSMENR2_SPI1SMEN_Pos) /*!< 0x00001000 */
  4323. #define RCC_APBSMENR2_SPI1SMEN RCC_APBSMENR2_SPI1SMEN_Msk
  4324. #define RCC_APBSMENR2_USART1SMEN_Pos (14U)
  4325. #define RCC_APBSMENR2_USART1SMEN_Msk (0x1UL << RCC_APBSMENR2_USART1SMEN_Pos) /*!< 0x00004000 */
  4326. #define RCC_APBSMENR2_USART1SMEN RCC_APBSMENR2_USART1SMEN_Msk
  4327. #define RCC_APBSMENR2_TIM14SMEN_Pos (15U)
  4328. #define RCC_APBSMENR2_TIM14SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM14SMEN_Pos) /*!< 0x00008000 */
  4329. #define RCC_APBSMENR2_TIM14SMEN RCC_APBSMENR2_TIM14SMEN_Msk
  4330. #define RCC_APBSMENR2_TIM16SMEN_Pos (17U)
  4331. #define RCC_APBSMENR2_TIM16SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM16SMEN_Pos) /*!< 0x00020000 */
  4332. #define RCC_APBSMENR2_TIM16SMEN RCC_APBSMENR2_TIM16SMEN_Msk
  4333. #define RCC_APBSMENR2_TIM17SMEN_Pos (18U)
  4334. #define RCC_APBSMENR2_TIM17SMEN_Msk (0x1UL << RCC_APBSMENR2_TIM17SMEN_Pos) /*!< 0x00040000 */
  4335. #define RCC_APBSMENR2_TIM17SMEN RCC_APBSMENR2_TIM17SMEN_Msk
  4336. #define RCC_APBSMENR2_ADCSMEN_Pos (20U)
  4337. #define RCC_APBSMENR2_ADCSMEN_Msk (0x1UL << RCC_APBSMENR2_ADCSMEN_Pos) /*!< 0x00100000 */
  4338. #define RCC_APBSMENR2_ADCSMEN RCC_APBSMENR2_ADCSMEN_Msk
  4339. /******************** Bit definition for RCC_CCIPR register ******************/
  4340. #define RCC_CCIPR_USART1SEL_Pos (0U)
  4341. #define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
  4342. #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
  4343. #define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
  4344. #define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
  4345. #define RCC_CCIPR_LPUART1SEL_Pos (10U)
  4346. #define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
  4347. #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
  4348. #define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
  4349. #define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
  4350. #define RCC_CCIPR_I2C1SEL_Pos (12U)
  4351. #define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
  4352. #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
  4353. #define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
  4354. #define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
  4355. #define RCC_CCIPR_I2S1SEL_Pos (14U)
  4356. #define RCC_CCIPR_I2S1SEL_Msk (0x3UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x0000C000 */
  4357. #define RCC_CCIPR_I2S1SEL RCC_CCIPR_I2S1SEL_Msk
  4358. #define RCC_CCIPR_I2S1SEL_0 (0x1UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00004000 */
  4359. #define RCC_CCIPR_I2S1SEL_1 (0x2UL << RCC_CCIPR_I2S1SEL_Pos) /*!< 0x00008000 */
  4360. #define RCC_CCIPR_LPTIM1SEL_Pos (18U)
  4361. #define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
  4362. #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
  4363. #define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
  4364. #define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
  4365. #define RCC_CCIPR_LPTIM2SEL_Pos (20U)
  4366. #define RCC_CCIPR_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
  4367. #define RCC_CCIPR_LPTIM2SEL RCC_CCIPR_LPTIM2SEL_Msk
  4368. #define RCC_CCIPR_LPTIM2SEL_0 (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
  4369. #define RCC_CCIPR_LPTIM2SEL_1 (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
  4370. #define RCC_CCIPR_TIM1SEL_Pos (22U)
  4371. #define RCC_CCIPR_TIM1SEL_Msk (0x1UL << RCC_CCIPR_TIM1SEL_Pos) /*!< 0x00400000 */
  4372. #define RCC_CCIPR_TIM1SEL RCC_CCIPR_TIM1SEL_Msk
  4373. #define RCC_CCIPR_ADCSEL_Pos (30U)
  4374. #define RCC_CCIPR_ADCSEL_Msk (0x3UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0xC0000000 */
  4375. #define RCC_CCIPR_ADCSEL RCC_CCIPR_ADCSEL_Msk
  4376. #define RCC_CCIPR_ADCSEL_0 (0x1UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x40000000 */
  4377. #define RCC_CCIPR_ADCSEL_1 (0x2UL << RCC_CCIPR_ADCSEL_Pos) /*!< 0x80000000 */
  4378. /******************** Bit definition for RCC_BDCR register ******************/
  4379. #define RCC_BDCR_LSEON_Pos (0U)
  4380. #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
  4381. #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
  4382. #define RCC_BDCR_LSERDY_Pos (1U)
  4383. #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
  4384. #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
  4385. #define RCC_BDCR_LSEBYP_Pos (2U)
  4386. #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
  4387. #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
  4388. #define RCC_BDCR_LSEDRV_Pos (3U)
  4389. #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
  4390. #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
  4391. #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
  4392. #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
  4393. #define RCC_BDCR_LSECSSON_Pos (5U)
  4394. #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
  4395. #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
  4396. #define RCC_BDCR_LSECSSD_Pos (6U)
  4397. #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
  4398. #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
  4399. #define RCC_BDCR_RTCSEL_Pos (8U)
  4400. #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
  4401. #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
  4402. #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
  4403. #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
  4404. #define RCC_BDCR_RTCEN_Pos (15U)
  4405. #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
  4406. #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
  4407. #define RCC_BDCR_BDRST_Pos (16U)
  4408. #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
  4409. #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
  4410. #define RCC_BDCR_LSCOEN_Pos (24U)
  4411. #define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
  4412. #define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
  4413. #define RCC_BDCR_LSCOSEL_Pos (25U)
  4414. #define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
  4415. #define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
  4416. /******************** Bit definition for RCC_CSR register *******************/
  4417. #define RCC_CSR_LSION_Pos (0U)
  4418. #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
  4419. #define RCC_CSR_LSION RCC_CSR_LSION_Msk
  4420. #define RCC_CSR_LSIRDY_Pos (1U)
  4421. #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
  4422. #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
  4423. #define RCC_CSR_RMVF_Pos (23U)
  4424. #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
  4425. #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
  4426. #define RCC_CSR_OBLRSTF_Pos (25U)
  4427. #define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
  4428. #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
  4429. #define RCC_CSR_PINRSTF_Pos (26U)
  4430. #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
  4431. #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
  4432. #define RCC_CSR_PWRRSTF_Pos (27U)
  4433. #define RCC_CSR_PWRRSTF_Msk (0x1UL << RCC_CSR_PWRRSTF_Pos) /*!< 0x08000000 */
  4434. #define RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF_Msk
  4435. #define RCC_CSR_SFTRSTF_Pos (28U)
  4436. #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
  4437. #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
  4438. #define RCC_CSR_IWDGRSTF_Pos (29U)
  4439. #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
  4440. #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
  4441. #define RCC_CSR_WWDGRSTF_Pos (30U)
  4442. #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
  4443. #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
  4444. #define RCC_CSR_LPWRRSTF_Pos (31U)
  4445. #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
  4446. #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
  4447. /******************************************************************************/
  4448. /* */
  4449. /* Real-Time Clock (RTC) */
  4450. /* */
  4451. /******************************************************************************/
  4452. /*
  4453. * @brief Specific device feature definitions
  4454. */
  4455. #define RTC_WAKEUP_SUPPORT
  4456. #define RTC_BACKUP_SUPPORT
  4457. /******************** Bits definition for RTC_TR register *******************/
  4458. #define RTC_TR_PM_Pos (22U)
  4459. #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
  4460. #define RTC_TR_PM RTC_TR_PM_Msk
  4461. #define RTC_TR_HT_Pos (20U)
  4462. #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
  4463. #define RTC_TR_HT RTC_TR_HT_Msk
  4464. #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
  4465. #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
  4466. #define RTC_TR_HU_Pos (16U)
  4467. #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
  4468. #define RTC_TR_HU RTC_TR_HU_Msk
  4469. #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
  4470. #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
  4471. #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
  4472. #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
  4473. #define RTC_TR_MNT_Pos (12U)
  4474. #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
  4475. #define RTC_TR_MNT RTC_TR_MNT_Msk
  4476. #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
  4477. #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
  4478. #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
  4479. #define RTC_TR_MNU_Pos (8U)
  4480. #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
  4481. #define RTC_TR_MNU RTC_TR_MNU_Msk
  4482. #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
  4483. #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
  4484. #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
  4485. #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
  4486. #define RTC_TR_ST_Pos (4U)
  4487. #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
  4488. #define RTC_TR_ST RTC_TR_ST_Msk
  4489. #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
  4490. #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
  4491. #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
  4492. #define RTC_TR_SU_Pos (0U)
  4493. #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
  4494. #define RTC_TR_SU RTC_TR_SU_Msk
  4495. #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
  4496. #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
  4497. #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
  4498. #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
  4499. /******************** Bits definition for RTC_DR register *******************/
  4500. #define RTC_DR_YT_Pos (20U)
  4501. #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
  4502. #define RTC_DR_YT RTC_DR_YT_Msk
  4503. #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
  4504. #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
  4505. #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
  4506. #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
  4507. #define RTC_DR_YU_Pos (16U)
  4508. #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
  4509. #define RTC_DR_YU RTC_DR_YU_Msk
  4510. #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
  4511. #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
  4512. #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
  4513. #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
  4514. #define RTC_DR_WDU_Pos (13U)
  4515. #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
  4516. #define RTC_DR_WDU RTC_DR_WDU_Msk
  4517. #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
  4518. #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
  4519. #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
  4520. #define RTC_DR_MT_Pos (12U)
  4521. #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
  4522. #define RTC_DR_MT RTC_DR_MT_Msk
  4523. #define RTC_DR_MU_Pos (8U)
  4524. #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
  4525. #define RTC_DR_MU RTC_DR_MU_Msk
  4526. #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
  4527. #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
  4528. #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
  4529. #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
  4530. #define RTC_DR_DT_Pos (4U)
  4531. #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
  4532. #define RTC_DR_DT RTC_DR_DT_Msk
  4533. #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
  4534. #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
  4535. #define RTC_DR_DU_Pos (0U)
  4536. #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
  4537. #define RTC_DR_DU RTC_DR_DU_Msk
  4538. #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
  4539. #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
  4540. #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
  4541. #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
  4542. /******************** Bits definition for RTC_SSR register ******************/
  4543. #define RTC_SSR_SS_Pos (0U)
  4544. #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
  4545. #define RTC_SSR_SS RTC_SSR_SS_Msk
  4546. /******************** Bits definition for RTC_ICSR register ******************/
  4547. #define RTC_ICSR_RECALPF_Pos (16U)
  4548. #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
  4549. #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
  4550. #define RTC_ICSR_INIT_Pos (7U)
  4551. #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
  4552. #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
  4553. #define RTC_ICSR_INITF_Pos (6U)
  4554. #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
  4555. #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
  4556. #define RTC_ICSR_RSF_Pos (5U)
  4557. #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
  4558. #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
  4559. #define RTC_ICSR_INITS_Pos (4U)
  4560. #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
  4561. #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
  4562. #define RTC_ICSR_SHPF_Pos (3U)
  4563. #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
  4564. #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
  4565. #define RTC_ICSR_WUTWF_Pos (2U)
  4566. #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
  4567. #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk /*!< Wakeup timer write flag > */
  4568. #define RTC_ICSR_ALRBWF_Pos (1U)
  4569. #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
  4570. #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
  4571. #define RTC_ICSR_ALRAWF_Pos (0U)
  4572. #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
  4573. #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
  4574. /******************** Bits definition for RTC_PRER register *****************/
  4575. #define RTC_PRER_PREDIV_A_Pos (16U)
  4576. #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
  4577. #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
  4578. #define RTC_PRER_PREDIV_S_Pos (0U)
  4579. #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
  4580. #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
  4581. /******************** Bits definition for RTC_WUTR register *****************/
  4582. #define RTC_WUTR_WUT_Pos (0U)
  4583. #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
  4584. #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /*!< Wakeup auto-reload value bits > */
  4585. /******************** Bits definition for RTC_CR register *******************/
  4586. #define RTC_CR_OUT2EN_Pos (31U)
  4587. #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
  4588. #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!< RTC_OUT2 output enable */
  4589. #define RTC_CR_TAMPALRM_TYPE_Pos (30U)
  4590. #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
  4591. #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!< TAMPALARM output type */
  4592. #define RTC_CR_TAMPALRM_PU_Pos (29U)
  4593. #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
  4594. #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!< TAMPALARM output pull-up config */
  4595. #define RTC_CR_TAMPOE_Pos (26U)
  4596. #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
  4597. #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!< Tamper detection output enable on TAMPALARM */
  4598. #define RTC_CR_TAMPTS_Pos (25U)
  4599. #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
  4600. #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!< Activate timestamp on tamper detection event */
  4601. #define RTC_CR_ITSE_Pos (24U)
  4602. #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
  4603. #define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!< Timestamp on internal event enable */
  4604. #define RTC_CR_COE_Pos (23U)
  4605. #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
  4606. #define RTC_CR_COE RTC_CR_COE_Msk
  4607. #define RTC_CR_OSEL_Pos (21U)
  4608. #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
  4609. #define RTC_CR_OSEL RTC_CR_OSEL_Msk
  4610. #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
  4611. #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
  4612. #define RTC_CR_POL_Pos (20U)
  4613. #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
  4614. #define RTC_CR_POL RTC_CR_POL_Msk
  4615. #define RTC_CR_COSEL_Pos (19U)
  4616. #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
  4617. #define RTC_CR_COSEL RTC_CR_COSEL_Msk
  4618. #define RTC_CR_BKP_Pos (18U)
  4619. #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
  4620. #define RTC_CR_BKP RTC_CR_BKP_Msk
  4621. #define RTC_CR_SUB1H_Pos (17U)
  4622. #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
  4623. #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
  4624. #define RTC_CR_ADD1H_Pos (16U)
  4625. #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
  4626. #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
  4627. #define RTC_CR_TSIE_Pos (15U)
  4628. #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
  4629. #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< Timestamp interrupt enable > */
  4630. #define RTC_CR_WUTIE_Pos (14U)
  4631. #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
  4632. #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< Wakeup timer interrupt enable > */
  4633. #define RTC_CR_ALRBIE_Pos (13U)
  4634. #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
  4635. #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
  4636. #define RTC_CR_ALRAIE_Pos (12U)
  4637. #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
  4638. #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
  4639. #define RTC_CR_TSE_Pos (11U)
  4640. #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
  4641. #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< timestamp enable > */
  4642. #define RTC_CR_WUTE_Pos (10U)
  4643. #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
  4644. #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< Wakeup timer enable > */
  4645. #define RTC_CR_ALRBE_Pos (9U)
  4646. #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
  4647. #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
  4648. #define RTC_CR_ALRAE_Pos (8U)
  4649. #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
  4650. #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
  4651. #define RTC_CR_FMT_Pos (6U)
  4652. #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
  4653. #define RTC_CR_FMT RTC_CR_FMT_Msk
  4654. #define RTC_CR_BYPSHAD_Pos (5U)
  4655. #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
  4656. #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
  4657. #define RTC_CR_REFCKON_Pos (4U)
  4658. #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
  4659. #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
  4660. #define RTC_CR_TSEDGE_Pos (3U)
  4661. #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
  4662. #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< Timestamp event active edge > */
  4663. #define RTC_CR_WUCKSEL_Pos (0U)
  4664. #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
  4665. #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< Wakeup clock selection > */
  4666. #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
  4667. #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
  4668. #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
  4669. /******************** Bits definition for RTC_WPR register ******************/
  4670. #define RTC_WPR_KEY_Pos (0U)
  4671. #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
  4672. #define RTC_WPR_KEY RTC_WPR_KEY_Msk
  4673. /******************** Bits definition for RTC_CALR register *****************/
  4674. #define RTC_CALR_CALP_Pos (15U)
  4675. #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
  4676. #define RTC_CALR_CALP RTC_CALR_CALP_Msk
  4677. #define RTC_CALR_CALW8_Pos (14U)
  4678. #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
  4679. #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
  4680. #define RTC_CALR_CALW16_Pos (13U)
  4681. #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
  4682. #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
  4683. #define RTC_CALR_CALM_Pos (0U)
  4684. #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
  4685. #define RTC_CALR_CALM RTC_CALR_CALM_Msk
  4686. #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
  4687. #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
  4688. #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
  4689. #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
  4690. #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
  4691. #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
  4692. #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
  4693. #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
  4694. #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
  4695. /******************** Bits definition for RTC_SHIFTR register ***************/
  4696. #define RTC_SHIFTR_SUBFS_Pos (0U)
  4697. #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
  4698. #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
  4699. #define RTC_SHIFTR_ADD1S_Pos (31U)
  4700. #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
  4701. #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
  4702. /******************** Bits definition for RTC_TSTR register *****************/
  4703. #define RTC_TSTR_PM_Pos (22U)
  4704. #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
  4705. #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< AM-PM notation > */
  4706. #define RTC_TSTR_HT_Pos (20U)
  4707. #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
  4708. #define RTC_TSTR_HT RTC_TSTR_HT_Msk
  4709. #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
  4710. #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
  4711. #define RTC_TSTR_HU_Pos (16U)
  4712. #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
  4713. #define RTC_TSTR_HU RTC_TSTR_HU_Msk
  4714. #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
  4715. #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
  4716. #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
  4717. #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
  4718. #define RTC_TSTR_MNT_Pos (12U)
  4719. #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
  4720. #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
  4721. #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
  4722. #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
  4723. #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
  4724. #define RTC_TSTR_MNU_Pos (8U)
  4725. #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
  4726. #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
  4727. #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
  4728. #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
  4729. #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
  4730. #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
  4731. #define RTC_TSTR_ST_Pos (4U)
  4732. #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
  4733. #define RTC_TSTR_ST RTC_TSTR_ST_Msk
  4734. #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
  4735. #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
  4736. #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
  4737. #define RTC_TSTR_SU_Pos (0U)
  4738. #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
  4739. #define RTC_TSTR_SU RTC_TSTR_SU_Msk
  4740. #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
  4741. #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
  4742. #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
  4743. #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
  4744. /******************** Bits definition for RTC_TSDR register *****************/
  4745. #define RTC_TSDR_WDU_Pos (13U)
  4746. #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
  4747. #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< Week day units > */
  4748. #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
  4749. #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
  4750. #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
  4751. #define RTC_TSDR_MT_Pos (12U)
  4752. #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
  4753. #define RTC_TSDR_MT RTC_TSDR_MT_Msk
  4754. #define RTC_TSDR_MU_Pos (8U)
  4755. #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
  4756. #define RTC_TSDR_MU RTC_TSDR_MU_Msk
  4757. #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
  4758. #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
  4759. #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
  4760. #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
  4761. #define RTC_TSDR_DT_Pos (4U)
  4762. #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
  4763. #define RTC_TSDR_DT RTC_TSDR_DT_Msk
  4764. #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
  4765. #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
  4766. #define RTC_TSDR_DU_Pos (0U)
  4767. #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
  4768. #define RTC_TSDR_DU RTC_TSDR_DU_Msk
  4769. #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
  4770. #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
  4771. #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
  4772. #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
  4773. /******************** Bits definition for RTC_TSSSR register ****************/
  4774. #define RTC_TSSSR_SS_Pos (0U)
  4775. #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
  4776. #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /*!< Sub second value > */
  4777. /******************** Bits definition for RTC_ALRMAR register ***************/
  4778. #define RTC_ALRMAR_MSK4_Pos (31U)
  4779. #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
  4780. #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
  4781. #define RTC_ALRMAR_WDSEL_Pos (30U)
  4782. #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
  4783. #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
  4784. #define RTC_ALRMAR_DT_Pos (28U)
  4785. #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
  4786. #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
  4787. #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
  4788. #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
  4789. #define RTC_ALRMAR_DU_Pos (24U)
  4790. #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
  4791. #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
  4792. #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
  4793. #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
  4794. #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
  4795. #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
  4796. #define RTC_ALRMAR_MSK3_Pos (23U)
  4797. #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
  4798. #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
  4799. #define RTC_ALRMAR_PM_Pos (22U)
  4800. #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
  4801. #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
  4802. #define RTC_ALRMAR_HT_Pos (20U)
  4803. #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
  4804. #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
  4805. #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
  4806. #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
  4807. #define RTC_ALRMAR_HU_Pos (16U)
  4808. #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
  4809. #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
  4810. #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
  4811. #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
  4812. #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
  4813. #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
  4814. #define RTC_ALRMAR_MSK2_Pos (15U)
  4815. #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
  4816. #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
  4817. #define RTC_ALRMAR_MNT_Pos (12U)
  4818. #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
  4819. #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
  4820. #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
  4821. #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
  4822. #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
  4823. #define RTC_ALRMAR_MNU_Pos (8U)
  4824. #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
  4825. #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
  4826. #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
  4827. #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
  4828. #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
  4829. #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
  4830. #define RTC_ALRMAR_MSK1_Pos (7U)
  4831. #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
  4832. #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
  4833. #define RTC_ALRMAR_ST_Pos (4U)
  4834. #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
  4835. #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
  4836. #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
  4837. #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
  4838. #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
  4839. #define RTC_ALRMAR_SU_Pos (0U)
  4840. #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
  4841. #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
  4842. #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
  4843. #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
  4844. #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
  4845. #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
  4846. /******************** Bits definition for RTC_ALRMASSR register *************/
  4847. #define RTC_ALRMASSR_MASKSS_Pos (24U)
  4848. #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
  4849. #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
  4850. #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
  4851. #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
  4852. #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
  4853. #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
  4854. #define RTC_ALRMASSR_SS_Pos (0U)
  4855. #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
  4856. #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
  4857. /******************** Bits definition for RTC_ALRMBR register ***************/
  4858. #define RTC_ALRMBR_MSK4_Pos (31U)
  4859. #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
  4860. #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
  4861. #define RTC_ALRMBR_WDSEL_Pos (30U)
  4862. #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
  4863. #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
  4864. #define RTC_ALRMBR_DT_Pos (28U)
  4865. #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
  4866. #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
  4867. #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
  4868. #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
  4869. #define RTC_ALRMBR_DU_Pos (24U)
  4870. #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
  4871. #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
  4872. #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
  4873. #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
  4874. #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
  4875. #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
  4876. #define RTC_ALRMBR_MSK3_Pos (23U)
  4877. #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
  4878. #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
  4879. #define RTC_ALRMBR_PM_Pos (22U)
  4880. #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
  4881. #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
  4882. #define RTC_ALRMBR_HT_Pos (20U)
  4883. #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
  4884. #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
  4885. #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
  4886. #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
  4887. #define RTC_ALRMBR_HU_Pos (16U)
  4888. #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
  4889. #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
  4890. #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
  4891. #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
  4892. #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
  4893. #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
  4894. #define RTC_ALRMBR_MSK2_Pos (15U)
  4895. #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
  4896. #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
  4897. #define RTC_ALRMBR_MNT_Pos (12U)
  4898. #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
  4899. #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
  4900. #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
  4901. #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
  4902. #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
  4903. #define RTC_ALRMBR_MNU_Pos (8U)
  4904. #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
  4905. #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
  4906. #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
  4907. #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
  4908. #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
  4909. #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
  4910. #define RTC_ALRMBR_MSK1_Pos (7U)
  4911. #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
  4912. #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
  4913. #define RTC_ALRMBR_ST_Pos (4U)
  4914. #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
  4915. #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
  4916. #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
  4917. #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
  4918. #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
  4919. #define RTC_ALRMBR_SU_Pos (0U)
  4920. #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
  4921. #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
  4922. #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
  4923. #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
  4924. #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
  4925. #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
  4926. /******************** Bits definition for RTC_ALRMASSR register *************/
  4927. #define RTC_ALRMBSSR_MASKSS_Pos (24U)
  4928. #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
  4929. #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
  4930. #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
  4931. #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
  4932. #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
  4933. #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
  4934. #define RTC_ALRMBSSR_SS_Pos (0U)
  4935. #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
  4936. #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
  4937. /******************** Bits definition for RTC_SR register *******************/
  4938. #define RTC_SR_ITSF_Pos (5U)
  4939. #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
  4940. #define RTC_SR_ITSF RTC_SR_ITSF_Msk
  4941. #define RTC_SR_TSOVF_Pos (4U)
  4942. #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
  4943. #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk /*!< Timestamp overflow flag > */
  4944. #define RTC_SR_TSF_Pos (3U)
  4945. #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
  4946. #define RTC_SR_TSF RTC_SR_TSF_Msk /*!< Timestamp flag > */
  4947. #define RTC_SR_WUTF_Pos (2U)
  4948. #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
  4949. #define RTC_SR_WUTF RTC_SR_WUTF_Msk /*!< Wakeup timer flag > */
  4950. #define RTC_SR_ALRBF_Pos (1U)
  4951. #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
  4952. #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
  4953. #define RTC_SR_ALRAF_Pos (0U)
  4954. #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
  4955. #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
  4956. /******************** Bits definition for RTC_MISR register *****************/
  4957. #define RTC_MISR_ITSMF_Pos (5U)
  4958. #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
  4959. #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
  4960. #define RTC_MISR_TSOVMF_Pos (4U)
  4961. #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
  4962. #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk /*!< Timestamp overflow masked flag > */
  4963. #define RTC_MISR_TSMF_Pos (3U)
  4964. #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
  4965. #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk /*!< Timestamp masked flag > */
  4966. #define RTC_MISR_WUTMF_Pos (2U)
  4967. #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
  4968. #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk /*!< Wakeup timer masked flag > */
  4969. #define RTC_MISR_ALRBMF_Pos (1U)
  4970. #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
  4971. #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
  4972. #define RTC_MISR_ALRAMF_Pos (0U)
  4973. #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
  4974. #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
  4975. /******************** Bits definition for RTC_SCR register ******************/
  4976. #define RTC_SCR_CITSF_Pos (5U)
  4977. #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
  4978. #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
  4979. #define RTC_SCR_CTSOVF_Pos (4U)
  4980. #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
  4981. #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk /*!< Clear timestamp overflow flag > */
  4982. #define RTC_SCR_CTSF_Pos (3U)
  4983. #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
  4984. #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk /*!< Clear timestamp flag > */
  4985. #define RTC_SCR_CWUTF_Pos (2U)
  4986. #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
  4987. #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk /*!< Clear wakeup timer flag > */
  4988. #define RTC_SCR_CALRBF_Pos (1U)
  4989. #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
  4990. #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
  4991. #define RTC_SCR_CALRAF_Pos (0U)
  4992. #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
  4993. #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
  4994. /******************************************************************************/
  4995. /* */
  4996. /* Tamper and backup register (TAMP) */
  4997. /* */
  4998. /******************************************************************************/
  4999. /******************** Bits definition for TAMP_CR1 register *****************/
  5000. #define TAMP_CR1_TAMP1E_Pos (0U)
  5001. #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
  5002. #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
  5003. #define TAMP_CR1_TAMP2E_Pos (1U)
  5004. #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
  5005. #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
  5006. #define TAMP_CR1_ITAMP3E_Pos (18U)
  5007. #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
  5008. #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
  5009. #define TAMP_CR1_ITAMP4E_Pos (19U)
  5010. #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
  5011. #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
  5012. #define TAMP_CR1_ITAMP5E_Pos (20U)
  5013. #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
  5014. #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
  5015. #define TAMP_CR1_ITAMP6E_Pos (21U)
  5016. #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
  5017. #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
  5018. /******************** Bits definition for TAMP_CR2 register *****************/
  5019. #define TAMP_CR2_TAMP1NOERASE_Pos (0U)
  5020. #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
  5021. #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
  5022. #define TAMP_CR2_TAMP2NOERASE_Pos (1U)
  5023. #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
  5024. #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
  5025. #define TAMP_CR2_TAMP1MSK_Pos (16U)
  5026. #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
  5027. #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
  5028. #define TAMP_CR2_TAMP2MSK_Pos (17U)
  5029. #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
  5030. #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
  5031. #define TAMP_CR2_TAMP1TRG_Pos (24U)
  5032. #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
  5033. #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
  5034. #define TAMP_CR2_TAMP2TRG_Pos (25U)
  5035. #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
  5036. #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
  5037. /******************** Bits definition for TAMP_FLTCR register ***************/
  5038. #define TAMP_FLTCR_TAMPFREQ_0 0x00000001U
  5039. #define TAMP_FLTCR_TAMPFREQ_1 0x00000002U
  5040. #define TAMP_FLTCR_TAMPFREQ_2 0x00000004U
  5041. #define TAMP_FLTCR_TAMPFREQ_Pos (0U)
  5042. #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
  5043. #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
  5044. #define TAMP_FLTCR_TAMPFLT_0 0x00000008U
  5045. #define TAMP_FLTCR_TAMPFLT_1 0x00000010U
  5046. #define TAMP_FLTCR_TAMPFLT_Pos (3U)
  5047. #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
  5048. #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
  5049. #define TAMP_FLTCR_TAMPPRCH_0 0x00000020U
  5050. #define TAMP_FLTCR_TAMPPRCH_1 0x00000040U
  5051. #define TAMP_FLTCR_TAMPPRCH_Pos (5U)
  5052. #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
  5053. #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
  5054. #define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
  5055. #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
  5056. #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
  5057. /******************** Bits definition for TAMP_IER register *****************/
  5058. #define TAMP_IER_TAMP1IE_Pos (0U)
  5059. #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
  5060. #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
  5061. #define TAMP_IER_TAMP2IE_Pos (1U)
  5062. #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
  5063. #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
  5064. #define TAMP_IER_ITAMP3IE_Pos (18U)
  5065. #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
  5066. #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
  5067. #define TAMP_IER_ITAMP4IE_Pos (19U)
  5068. #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
  5069. #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
  5070. #define TAMP_IER_ITAMP5IE_Pos (20U)
  5071. #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
  5072. #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
  5073. #define TAMP_IER_ITAMP6IE_Pos (21U)
  5074. #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
  5075. #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
  5076. /******************** Bits definition for TAMP_SR register ******************/
  5077. #define TAMP_SR_TAMP1F_Pos (0U)
  5078. #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
  5079. #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
  5080. #define TAMP_SR_TAMP2F_Pos (1U)
  5081. #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
  5082. #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
  5083. #define TAMP_SR_ITAMP3F_Pos (18U)
  5084. #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
  5085. #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
  5086. #define TAMP_SR_ITAMP4F_Pos (19U)
  5087. #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
  5088. #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
  5089. #define TAMP_SR_ITAMP5F_Pos (20U)
  5090. #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
  5091. #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
  5092. #define TAMP_SR_ITAMP6F_Pos (21U)
  5093. #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
  5094. #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
  5095. /******************** Bits definition for TAMP_MISR register ****************/
  5096. #define TAMP_MISR_TAMP1MF_Pos (0U)
  5097. #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
  5098. #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
  5099. #define TAMP_MISR_TAMP2MF_Pos (1U)
  5100. #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
  5101. #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
  5102. #define TAMP_MISR_ITAMP3MF_Pos (18U)
  5103. #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
  5104. #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
  5105. #define TAMP_MISR_ITAMP4MF_Pos (19U)
  5106. #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
  5107. #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
  5108. #define TAMP_MISR_ITAMP5MF_Pos (20U)
  5109. #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
  5110. #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
  5111. #define TAMP_MISR_ITAMP6MF_Pos (21U)
  5112. #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
  5113. #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
  5114. /******************** Bits definition for TAMP_SCR register *****************/
  5115. #define TAMP_SCR_CTAMP1F_Pos (0U)
  5116. #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
  5117. #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
  5118. #define TAMP_SCR_CTAMP2F_Pos (1U)
  5119. #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
  5120. #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
  5121. #define TAMP_SCR_CITAMP3F_Pos (18U)
  5122. #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
  5123. #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
  5124. #define TAMP_SCR_CITAMP4F_Pos (19U)
  5125. #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
  5126. #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
  5127. #define TAMP_SCR_CITAMP5F_Pos (20U)
  5128. #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
  5129. #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
  5130. #define TAMP_SCR_CITAMP6F_Pos (21U)
  5131. #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
  5132. #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
  5133. /******************** Bits definition for TAMP_BKP0R register ***************/
  5134. #define TAMP_BKP0R_Pos (0U)
  5135. #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
  5136. #define TAMP_BKP0R TAMP_BKP0R_Msk
  5137. /******************** Bits definition for TAMP_BKP1R register ***************/
  5138. #define TAMP_BKP1R_Pos (0U)
  5139. #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
  5140. #define TAMP_BKP1R TAMP_BKP1R_Msk
  5141. /******************** Bits definition for TAMP_BKP2R register ***************/
  5142. #define TAMP_BKP2R_Pos (0U)
  5143. #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
  5144. #define TAMP_BKP2R TAMP_BKP2R_Msk
  5145. /******************** Bits definition for TAMP_BKP3R register ***************/
  5146. #define TAMP_BKP3R_Pos (0U)
  5147. #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
  5148. #define TAMP_BKP3R TAMP_BKP3R_Msk
  5149. /******************** Bits definition for TAMP_BKP4R register ***************/
  5150. #define TAMP_BKP4R_Pos (0U)
  5151. #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
  5152. #define TAMP_BKP4R TAMP_BKP4R_Msk
  5153. /******************************************************************************/
  5154. /* */
  5155. /* Serial Peripheral Interface (SPI) */
  5156. /* */
  5157. /******************************************************************************/
  5158. /*
  5159. * @brief Specific device feature definitions (not present on all devices in the STM32G0 serie)
  5160. */
  5161. #define SPI_I2S_SUPPORT /*!< I2S support */
  5162. /******************* Bit definition for SPI_CR1 register ********************/
  5163. #define SPI_CR1_CPHA_Pos (0U)
  5164. #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
  5165. #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
  5166. #define SPI_CR1_CPOL_Pos (1U)
  5167. #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
  5168. #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
  5169. #define SPI_CR1_MSTR_Pos (2U)
  5170. #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
  5171. #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
  5172. #define SPI_CR1_BR_Pos (3U)
  5173. #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
  5174. #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
  5175. #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
  5176. #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
  5177. #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
  5178. #define SPI_CR1_SPE_Pos (6U)
  5179. #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
  5180. #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
  5181. #define SPI_CR1_LSBFIRST_Pos (7U)
  5182. #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
  5183. #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
  5184. #define SPI_CR1_SSI_Pos (8U)
  5185. #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
  5186. #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
  5187. #define SPI_CR1_SSM_Pos (9U)
  5188. #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
  5189. #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
  5190. #define SPI_CR1_RXONLY_Pos (10U)
  5191. #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
  5192. #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
  5193. #define SPI_CR1_CRCL_Pos (11U)
  5194. #define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
  5195. #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
  5196. #define SPI_CR1_CRCNEXT_Pos (12U)
  5197. #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
  5198. #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
  5199. #define SPI_CR1_CRCEN_Pos (13U)
  5200. #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
  5201. #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
  5202. #define SPI_CR1_BIDIOE_Pos (14U)
  5203. #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
  5204. #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
  5205. #define SPI_CR1_BIDIMODE_Pos (15U)
  5206. #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
  5207. #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
  5208. /******************* Bit definition for SPI_CR2 register ********************/
  5209. #define SPI_CR2_RXDMAEN_Pos (0U)
  5210. #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
  5211. #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
  5212. #define SPI_CR2_TXDMAEN_Pos (1U)
  5213. #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
  5214. #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
  5215. #define SPI_CR2_SSOE_Pos (2U)
  5216. #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
  5217. #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
  5218. #define SPI_CR2_NSSP_Pos (3U)
  5219. #define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
  5220. #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
  5221. #define SPI_CR2_FRF_Pos (4U)
  5222. #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
  5223. #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
  5224. #define SPI_CR2_ERRIE_Pos (5U)
  5225. #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
  5226. #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
  5227. #define SPI_CR2_RXNEIE_Pos (6U)
  5228. #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
  5229. #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
  5230. #define SPI_CR2_TXEIE_Pos (7U)
  5231. #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
  5232. #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
  5233. #define SPI_CR2_DS_Pos (8U)
  5234. #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
  5235. #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
  5236. #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
  5237. #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
  5238. #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
  5239. #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
  5240. #define SPI_CR2_FRXTH_Pos (12U)
  5241. #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
  5242. #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
  5243. #define SPI_CR2_LDMARX_Pos (13U)
  5244. #define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
  5245. #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
  5246. #define SPI_CR2_LDMATX_Pos (14U)
  5247. #define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
  5248. #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
  5249. /******************** Bit definition for SPI_SR register ********************/
  5250. #define SPI_SR_RXNE_Pos (0U)
  5251. #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
  5252. #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
  5253. #define SPI_SR_TXE_Pos (1U)
  5254. #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
  5255. #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
  5256. #define SPI_SR_CHSIDE_Pos (2U)
  5257. #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
  5258. #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
  5259. #define SPI_SR_UDR_Pos (3U)
  5260. #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
  5261. #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
  5262. #define SPI_SR_CRCERR_Pos (4U)
  5263. #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
  5264. #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
  5265. #define SPI_SR_MODF_Pos (5U)
  5266. #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
  5267. #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
  5268. #define SPI_SR_OVR_Pos (6U)
  5269. #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
  5270. #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
  5271. #define SPI_SR_BSY_Pos (7U)
  5272. #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
  5273. #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
  5274. #define SPI_SR_FRE_Pos (8U)
  5275. #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
  5276. #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
  5277. #define SPI_SR_FRLVL_Pos (9U)
  5278. #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
  5279. #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
  5280. #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
  5281. #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
  5282. #define SPI_SR_FTLVL_Pos (11U)
  5283. #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
  5284. #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
  5285. #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
  5286. #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
  5287. /******************** Bit definition for SPI_DR register ********************/
  5288. #define SPI_DR_DR_Pos (0U)
  5289. #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
  5290. #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
  5291. /******************* Bit definition for SPI_CRCPR register ******************/
  5292. #define SPI_CRCPR_CRCPOLY_Pos (0U)
  5293. #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
  5294. #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
  5295. /****************** Bit definition for SPI_RXCRCR register ******************/
  5296. #define SPI_RXCRCR_RXCRC_Pos (0U)
  5297. #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
  5298. #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
  5299. /****************** Bit definition for SPI_TXCRCR register ******************/
  5300. #define SPI_TXCRCR_TXCRC_Pos (0U)
  5301. #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
  5302. #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
  5303. /****************** Bit definition for SPI_I2SCFGR register *****************/
  5304. #define SPI_I2SCFGR_CHLEN_Pos (0U)
  5305. #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
  5306. #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
  5307. #define SPI_I2SCFGR_DATLEN_Pos (1U)
  5308. #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
  5309. #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
  5310. #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
  5311. #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
  5312. #define SPI_I2SCFGR_CKPOL_Pos (3U)
  5313. #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
  5314. #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
  5315. #define SPI_I2SCFGR_I2SSTD_Pos (4U)
  5316. #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
  5317. #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
  5318. #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
  5319. #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
  5320. #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
  5321. #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
  5322. #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
  5323. #define SPI_I2SCFGR_I2SCFG_Pos (8U)
  5324. #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
  5325. #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
  5326. #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
  5327. #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
  5328. #define SPI_I2SCFGR_I2SE_Pos (10U)
  5329. #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
  5330. #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
  5331. #define SPI_I2SCFGR_I2SMOD_Pos (11U)
  5332. #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
  5333. #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
  5334. #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
  5335. #define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
  5336. #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
  5337. /****************** Bit definition for SPI_I2SPR register *******************/
  5338. #define SPI_I2SPR_I2SDIV_Pos (0U)
  5339. #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
  5340. #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
  5341. #define SPI_I2SPR_ODD_Pos (8U)
  5342. #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
  5343. #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
  5344. #define SPI_I2SPR_MCKOE_Pos (9U)
  5345. #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
  5346. #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
  5347. /******************************************************************************/
  5348. /* */
  5349. /* SYSCFG */
  5350. /* */
  5351. /******************************************************************************/
  5352. /***************** Bit definition for SYSCFG_CFGR1 register ****************/
  5353. #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
  5354. #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
  5355. #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
  5356. #define SYSCFG_CFGR1_MEM_MODE_0 (0x1UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
  5357. #define SYSCFG_CFGR1_MEM_MODE_1 (0x2UL << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
  5358. #define SYSCFG_CFGR1_PA11_RMP_Pos (3U)
  5359. #define SYSCFG_CFGR1_PA11_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA11_RMP_Pos) /*!< 0x00000008 */
  5360. #define SYSCFG_CFGR1_PA11_RMP SYSCFG_CFGR1_PA11_RMP_Msk /*!< PA11 Remap */
  5361. #define SYSCFG_CFGR1_PA12_RMP_Pos (4U)
  5362. #define SYSCFG_CFGR1_PA12_RMP_Msk (0x1UL << SYSCFG_CFGR1_PA12_RMP_Pos) /*!< 0x00000010 */
  5363. #define SYSCFG_CFGR1_PA12_RMP SYSCFG_CFGR1_PA12_RMP_Msk /*!< PA12 Remap */
  5364. #define SYSCFG_CFGR1_IR_POL_Pos (5U)
  5365. #define SYSCFG_CFGR1_IR_POL_Msk (0x1UL << SYSCFG_CFGR1_IR_POL_Pos) /*!< 0x00000020 */
  5366. #define SYSCFG_CFGR1_IR_POL SYSCFG_CFGR1_IR_POL_Msk /*!< IROut Polarity Selection */
  5367. #define SYSCFG_CFGR1_IR_MOD_Pos (6U)
  5368. #define SYSCFG_CFGR1_IR_MOD_Msk (0x3UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x000000C0 */
  5369. #define SYSCFG_CFGR1_IR_MOD SYSCFG_CFGR1_IR_MOD_Msk /*!< IRDA Modulation Envelope signal source selection */
  5370. #define SYSCFG_CFGR1_IR_MOD_0 (0x1UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000040 */
  5371. #define SYSCFG_CFGR1_IR_MOD_1 (0x2UL << SYSCFG_CFGR1_IR_MOD_Pos) /*!< 0x00000080 */
  5372. #define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
  5373. #define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
  5374. #define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
  5375. #define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
  5376. #define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos) /*!< 0x00010000 */
  5377. #define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
  5378. #define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
  5379. #define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos) /*!< 0x00020000 */
  5380. #define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
  5381. #define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
  5382. #define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos) /*!< 0x00040000 */
  5383. #define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
  5384. #define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
  5385. #define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos) /*!< 0x00080000 */
  5386. #define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
  5387. #define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
  5388. #define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
  5389. #define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
  5390. #define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
  5391. #define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
  5392. #define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< Enable I2C2 Fast mode plus */
  5393. #define SYSCFG_CFGR1_I2C_PA9_FMP_Pos (22U)
  5394. #define SYSCFG_CFGR1_I2C_PA9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA9_FMP_Pos) /*!< 0x00400000 */
  5395. #define SYSCFG_CFGR1_I2C_PA9_FMP SYSCFG_CFGR1_I2C_PA9_FMP_Msk /*!< Enable Fast Mode Plus on PA9 */
  5396. #define SYSCFG_CFGR1_I2C_PA10_FMP_Pos (23U)
  5397. #define SYSCFG_CFGR1_I2C_PA10_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PA10_FMP_Pos) /*!< 0x00800000 */
  5398. #define SYSCFG_CFGR1_I2C_PA10_FMP SYSCFG_CFGR1_I2C_PA10_FMP_Msk /*!< Enable Fast Mode Plus on PA10 */
  5399. /****************** Bit definition for SYSCFG_CFGR2 register ****************/
  5400. #define SYSCFG_CFGR2_CLL_Pos (0U)
  5401. #define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
  5402. #define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
  5403. #define SYSCFG_CFGR2_SPL_Pos (1U)
  5404. #define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
  5405. #define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
  5406. #define SYSCFG_CFGR2_PVDL_Pos (2U)
  5407. #define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
  5408. #define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
  5409. #define SYSCFG_CFGR2_ECCL_Pos (3U)
  5410. #define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
  5411. #define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECCL */
  5412. #define SYSCFG_CFGR2_SPF_Pos (8U)
  5413. #define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
  5414. #define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity error flag */
  5415. #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
  5416. #define SYSCFG_CFGR2_PA1_CDEN_Pos (16U)
  5417. #define SYSCFG_CFGR2_PA1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA1_CDEN_Pos) /* 0x00010000 */
  5418. #define SYSCFG_CFGR2_PA1_CDEN SYSCFG_CFGR2_PA1_CDEN_Msk /*!< PA[1] Clamping Diode Enable */
  5419. #define SYSCFG_CFGR2_PA3_CDEN_Pos (17U)
  5420. #define SYSCFG_CFGR2_PA3_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA3_CDEN_Pos) /* 0x00020000 */
  5421. #define SYSCFG_CFGR2_PA3_CDEN SYSCFG_CFGR2_PA3_CDEN_Msk /*!< PA[3] Clamping Diode Enable */
  5422. #define SYSCFG_CFGR2_PA5_CDEN_Pos (18U)
  5423. #define SYSCFG_CFGR2_PA5_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA5_CDEN_Pos) /* 0x00040000 */
  5424. #define SYSCFG_CFGR2_PA5_CDEN SYSCFG_CFGR2_PA5_CDEN_Msk /*!< PA[5] Clamping Diode Enable */
  5425. #define SYSCFG_CFGR2_PA6_CDEN_Pos (19U)
  5426. #define SYSCFG_CFGR2_PA6_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA6_CDEN_Pos) /* 0x00080000 */
  5427. #define SYSCFG_CFGR2_PA6_CDEN SYSCFG_CFGR2_PA6_CDEN_Msk /*!< PA[6] Clamping Diode Enable */
  5428. #define SYSCFG_CFGR2_PA13_CDEN_Pos (20U)
  5429. #define SYSCFG_CFGR2_PA13_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PA13_CDEN_Pos) /* 0x00100000 */
  5430. #define SYSCFG_CFGR2_PA13_CDEN SYSCFG_CFGR2_PA13_CDEN_Msk /*!< PA[13] Clamping Diode Enable */
  5431. #define SYSCFG_CFGR2_PB0_CDEN_Pos (21U)
  5432. #define SYSCFG_CFGR2_PB0_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB0_CDEN_Pos) /* 0x00200000 */
  5433. #define SYSCFG_CFGR2_PB0_CDEN SYSCFG_CFGR2_PB0_CDEN_Msk /*!< PB[0] Clamping Diode Enable */
  5434. #define SYSCFG_CFGR2_PB1_CDEN_Pos (22U)
  5435. #define SYSCFG_CFGR2_PB1_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB1_CDEN_Pos) /* 0x00400000 */
  5436. #define SYSCFG_CFGR2_PB1_CDEN SYSCFG_CFGR2_PB1_CDEN_Msk /*!< PB[1] Clamping Diode Enable */
  5437. #define SYSCFG_CFGR2_PB2_CDEN_Pos (23U)
  5438. #define SYSCFG_CFGR2_PB2_CDEN_Msk (0x1UL << SYSCFG_CFGR2_PB2_CDEN_Pos) /* 0x00800000 */
  5439. #define SYSCFG_CFGR2_PB2_CDEN SYSCFG_CFGR2_PB2_CDEN_Msk /*!< PB[2] Clamping Diode Enable */
  5440. /***************** Bit definition for SYSCFG_ITLINEx ISR Wrapper register ****************/
  5441. #define SYSCFG_ITLINE0_SR_EWDG_Pos (0U)
  5442. #define SYSCFG_ITLINE0_SR_EWDG_Msk (0x1UL << SYSCFG_ITLINE0_SR_EWDG_Pos) /*!< 0x00000001 */
  5443. #define SYSCFG_ITLINE0_SR_EWDG SYSCFG_ITLINE0_SR_EWDG_Msk /*!< EWDG interrupt */
  5444. #define SYSCFG_ITLINE1_SR_PVDOUT_Pos (0U)
  5445. #define SYSCFG_ITLINE1_SR_PVDOUT_Msk (0x1UL << SYSCFG_ITLINE1_SR_PVDOUT_Pos) /*!< 0x00000001 */
  5446. #define SYSCFG_ITLINE1_SR_PVDOUT SYSCFG_ITLINE1_SR_PVDOUT_Msk /*!< Power voltage detection -> exti[16] Interrupt */
  5447. #define SYSCFG_ITLINE2_SR_TAMPER_Pos (0U)
  5448. #define SYSCFG_ITLINE2_SR_TAMPER_Msk (0x1UL << SYSCFG_ITLINE2_SR_TAMPER_Pos) /*!< 0x00000001 */
  5449. #define SYSCFG_ITLINE2_SR_TAMPER SYSCFG_ITLINE2_SR_TAMPER_Msk /*!< TAMPER -> exti[21] interrupt */
  5450. #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos (1U)
  5451. #define SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk (0x1UL << SYSCFG_ITLINE2_SR_RTC_WAKEUP_Pos) /*!< 0x00000002 */
  5452. #define SYSCFG_ITLINE2_SR_RTC_WAKEUP SYSCFG_ITLINE2_SR_RTC_WAKEUP_Msk /*!< RTC_WAKEUP -> exti[19] interrupt .... */
  5453. #define SYSCFG_ITLINE3_SR_FLASH_ECC_Pos (0U)
  5454. #define SYSCFG_ITLINE3_SR_FLASH_ECC_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ECC_Pos) /*!< 0x00000001 */
  5455. #define SYSCFG_ITLINE3_SR_FLASH_ECC SYSCFG_ITLINE3_SR_FLASH_ECC_Msk /*!< Flash ITF ECC interrupt */
  5456. #define SYSCFG_ITLINE3_SR_FLASH_ITF_Pos (1U)
  5457. #define SYSCFG_ITLINE3_SR_FLASH_ITF_Msk (0x1UL << SYSCFG_ITLINE3_SR_FLASH_ITF_Pos) /*!< 0x00000002 */
  5458. #define SYSCFG_ITLINE3_SR_FLASH_ITF SYSCFG_ITLINE3_SR_FLASH_ITF_Msk /*!< FLASH ITF interrupt */
  5459. #define SYSCFG_ITLINE4_SR_CLK_CTRL_Pos (0U)
  5460. #define SYSCFG_ITLINE4_SR_CLK_CTRL_Msk (0x1UL << SYSCFG_ITLINE4_SR_CLK_CTRL_Pos) /*!< 0x00000001 */
  5461. #define SYSCFG_ITLINE4_SR_CLK_CTRL SYSCFG_ITLINE4_SR_CLK_CTRL_Msk /*!< RCC interrupt */
  5462. #define SYSCFG_ITLINE5_SR_EXTI0_Pos (0U)
  5463. #define SYSCFG_ITLINE5_SR_EXTI0_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI0_Pos) /*!< 0x00000001 */
  5464. #define SYSCFG_ITLINE5_SR_EXTI0 SYSCFG_ITLINE5_SR_EXTI0_Msk /*!< External Interrupt 0 */
  5465. #define SYSCFG_ITLINE5_SR_EXTI1_Pos (1U)
  5466. #define SYSCFG_ITLINE5_SR_EXTI1_Msk (0x1UL << SYSCFG_ITLINE5_SR_EXTI1_Pos) /*!< 0x00000002 */
  5467. #define SYSCFG_ITLINE5_SR_EXTI1 SYSCFG_ITLINE5_SR_EXTI1_Msk /*!< External Interrupt 1 */
  5468. #define SYSCFG_ITLINE6_SR_EXTI2_Pos (0U)
  5469. #define SYSCFG_ITLINE6_SR_EXTI2_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI2_Pos) /*!< 0x00000001 */
  5470. #define SYSCFG_ITLINE6_SR_EXTI2 SYSCFG_ITLINE6_SR_EXTI2_Msk /*!< External Interrupt 2 */
  5471. #define SYSCFG_ITLINE6_SR_EXTI3_Pos (1U)
  5472. #define SYSCFG_ITLINE6_SR_EXTI3_Msk (0x1UL << SYSCFG_ITLINE6_SR_EXTI3_Pos) /*!< 0x00000002 */
  5473. #define SYSCFG_ITLINE6_SR_EXTI3 SYSCFG_ITLINE6_SR_EXTI3_Msk /*!< External Interrupt 3 */
  5474. #define SYSCFG_ITLINE7_SR_EXTI4_Pos (0U)
  5475. #define SYSCFG_ITLINE7_SR_EXTI4_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI4_Pos) /*!< 0x00000001 */
  5476. #define SYSCFG_ITLINE7_SR_EXTI4 SYSCFG_ITLINE7_SR_EXTI4_Msk /*!< External Interrupt 4 */
  5477. #define SYSCFG_ITLINE7_SR_EXTI5_Pos (1U)
  5478. #define SYSCFG_ITLINE7_SR_EXTI5_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI5_Pos) /*!< 0x00000002 */
  5479. #define SYSCFG_ITLINE7_SR_EXTI5 SYSCFG_ITLINE7_SR_EXTI5_Msk /*!< External Interrupt 5 */
  5480. #define SYSCFG_ITLINE7_SR_EXTI6_Pos (2U)
  5481. #define SYSCFG_ITLINE7_SR_EXTI6_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI6_Pos) /*!< 0x00000004 */
  5482. #define SYSCFG_ITLINE7_SR_EXTI6 SYSCFG_ITLINE7_SR_EXTI6_Msk /*!< External Interrupt 6 */
  5483. #define SYSCFG_ITLINE7_SR_EXTI7_Pos (3U)
  5484. #define SYSCFG_ITLINE7_SR_EXTI7_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI7_Pos) /*!< 0x00000008 */
  5485. #define SYSCFG_ITLINE7_SR_EXTI7 SYSCFG_ITLINE7_SR_EXTI7_Msk /*!< External Interrupt 7 */
  5486. #define SYSCFG_ITLINE7_SR_EXTI8_Pos (4U)
  5487. #define SYSCFG_ITLINE7_SR_EXTI8_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI8_Pos) /*!< 0x00000010 */
  5488. #define SYSCFG_ITLINE7_SR_EXTI8 SYSCFG_ITLINE7_SR_EXTI8_Msk /*!< External Interrupt 8 */
  5489. #define SYSCFG_ITLINE7_SR_EXTI9_Pos (5U)
  5490. #define SYSCFG_ITLINE7_SR_EXTI9_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI9_Pos) /*!< 0x00000020 */
  5491. #define SYSCFG_ITLINE7_SR_EXTI9 SYSCFG_ITLINE7_SR_EXTI9_Msk /*!< External Interrupt 9 */
  5492. #define SYSCFG_ITLINE7_SR_EXTI10_Pos (6U)
  5493. #define SYSCFG_ITLINE7_SR_EXTI10_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI10_Pos) /*!< 0x00000040 */
  5494. #define SYSCFG_ITLINE7_SR_EXTI10 SYSCFG_ITLINE7_SR_EXTI10_Msk /*!< External Interrupt 10 */
  5495. #define SYSCFG_ITLINE7_SR_EXTI11_Pos (7U)
  5496. #define SYSCFG_ITLINE7_SR_EXTI11_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI11_Pos) /*!< 0x00000080 */
  5497. #define SYSCFG_ITLINE7_SR_EXTI11 SYSCFG_ITLINE7_SR_EXTI11_Msk /*!< External Interrupt 11 */
  5498. #define SYSCFG_ITLINE7_SR_EXTI12_Pos (8U)
  5499. #define SYSCFG_ITLINE7_SR_EXTI12_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI12_Pos) /*!< 0x00000100 */
  5500. #define SYSCFG_ITLINE7_SR_EXTI12 SYSCFG_ITLINE7_SR_EXTI12_Msk /*!< External Interrupt 12 */
  5501. #define SYSCFG_ITLINE7_SR_EXTI13_Pos (9U)
  5502. #define SYSCFG_ITLINE7_SR_EXTI13_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI13_Pos) /*!< 0x00000200 */
  5503. #define SYSCFG_ITLINE7_SR_EXTI13 SYSCFG_ITLINE7_SR_EXTI13_Msk /*!< External Interrupt 13 */
  5504. #define SYSCFG_ITLINE7_SR_EXTI14_Pos (10U)
  5505. #define SYSCFG_ITLINE7_SR_EXTI14_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI14_Pos) /*!< 0x00000400 */
  5506. #define SYSCFG_ITLINE7_SR_EXTI14 SYSCFG_ITLINE7_SR_EXTI14_Msk /*!< External Interrupt 14 */
  5507. #define SYSCFG_ITLINE7_SR_EXTI15_Pos (11U)
  5508. #define SYSCFG_ITLINE7_SR_EXTI15_Msk (0x1UL << SYSCFG_ITLINE7_SR_EXTI15_Pos) /*!< 0x00000800 */
  5509. #define SYSCFG_ITLINE7_SR_EXTI15 SYSCFG_ITLINE7_SR_EXTI15_Msk /*!< External Interrupt 15 */
  5510. #define SYSCFG_ITLINE9_SR_DMA1_CH1_Pos (0U)
  5511. #define SYSCFG_ITLINE9_SR_DMA1_CH1_Msk (0x1UL << SYSCFG_ITLINE9_SR_DMA1_CH1_Pos) /*!< 0x00000001 */
  5512. #define SYSCFG_ITLINE9_SR_DMA1_CH1 SYSCFG_ITLINE9_SR_DMA1_CH1_Msk /*!< DMA1 Channel 1 Interrupt */
  5513. #define SYSCFG_ITLINE10_SR_DMA1_CH2_Pos (0U)
  5514. #define SYSCFG_ITLINE10_SR_DMA1_CH2_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH2_Pos) /*!< 0x00000001 */
  5515. #define SYSCFG_ITLINE10_SR_DMA1_CH2 SYSCFG_ITLINE10_SR_DMA1_CH2_Msk /*!< DMA1 Channel 2 Interrupt */
  5516. #define SYSCFG_ITLINE10_SR_DMA1_CH3_Pos (1U)
  5517. #define SYSCFG_ITLINE10_SR_DMA1_CH3_Msk (0x1UL << SYSCFG_ITLINE10_SR_DMA1_CH3_Pos) /*!< 0x00000002 */
  5518. #define SYSCFG_ITLINE10_SR_DMA1_CH3 SYSCFG_ITLINE10_SR_DMA1_CH3_Msk /*!< DMA2 Channel 3 Interrupt */
  5519. #define SYSCFG_ITLINE11_SR_DMAMUX1_Pos (0U)
  5520. #define SYSCFG_ITLINE11_SR_DMAMUX1_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMAMUX1_Pos) /*!< 0x00000001 */
  5521. #define SYSCFG_ITLINE11_SR_DMAMUX1 SYSCFG_ITLINE11_SR_DMAMUX1_Msk /*!< DMAMUX Interrupt */
  5522. #define SYSCFG_ITLINE11_SR_DMA1_CH4_Pos (1U)
  5523. #define SYSCFG_ITLINE11_SR_DMA1_CH4_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH4_Pos) /*!< 0x00000002 */
  5524. #define SYSCFG_ITLINE11_SR_DMA1_CH4 SYSCFG_ITLINE11_SR_DMA1_CH4_Msk /*!< DMA1 Channel 4 Interrupt */
  5525. #define SYSCFG_ITLINE11_SR_DMA1_CH5_Pos (2U)
  5526. #define SYSCFG_ITLINE11_SR_DMA1_CH5_Msk (0x1UL << SYSCFG_ITLINE11_SR_DMA1_CH5_Pos) /*!< 0x00000004 */
  5527. #define SYSCFG_ITLINE11_SR_DMA1_CH5 SYSCFG_ITLINE11_SR_DMA1_CH5_Msk /*!< DMA1 Channel 5 Interrupt */
  5528. #define SYSCFG_ITLINE12_SR_ADC_Pos (0U)
  5529. #define SYSCFG_ITLINE12_SR_ADC_Msk (0x1UL << SYSCFG_ITLINE12_SR_ADC_Pos) /*!< 0x00000001 */
  5530. #define SYSCFG_ITLINE12_SR_ADC SYSCFG_ITLINE12_SR_ADC_Msk /*!< ADC Interrupt */
  5531. #define SYSCFG_ITLINE13_SR_TIM1_CCU_Pos (0U)
  5532. #define SYSCFG_ITLINE13_SR_TIM1_CCU_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_CCU_Pos) /*!< 0x00000001 */
  5533. #define SYSCFG_ITLINE13_SR_TIM1_CCU SYSCFG_ITLINE13_SR_TIM1_CCU_Msk /*!< TIM1 CCU Interrupt */
  5534. #define SYSCFG_ITLINE13_SR_TIM1_TRG_Pos (1U)
  5535. #define SYSCFG_ITLINE13_SR_TIM1_TRG_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_TRG_Pos) /*!< 0x00000002 */
  5536. #define SYSCFG_ITLINE13_SR_TIM1_TRG SYSCFG_ITLINE13_SR_TIM1_TRG_Msk /*!< TIM1 TRG Interrupt */
  5537. #define SYSCFG_ITLINE13_SR_TIM1_UPD_Pos (2U)
  5538. #define SYSCFG_ITLINE13_SR_TIM1_UPD_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_UPD_Pos) /*!< 0x00000004 */
  5539. #define SYSCFG_ITLINE13_SR_TIM1_UPD SYSCFG_ITLINE13_SR_TIM1_UPD_Msk /*!< TIM1 UPD Interrupt */
  5540. #define SYSCFG_ITLINE13_SR_TIM1_BRK_Pos (3U)
  5541. #define SYSCFG_ITLINE13_SR_TIM1_BRK_Msk (0x1UL << SYSCFG_ITLINE13_SR_TIM1_BRK_Pos) /*!< 0x00000008 */
  5542. #define SYSCFG_ITLINE13_SR_TIM1_BRK SYSCFG_ITLINE13_SR_TIM1_BRK_Msk /*!< TIM1 BRK Interrupt */
  5543. #define SYSCFG_ITLINE14_SR_TIM1_CC_Pos (0U)
  5544. #define SYSCFG_ITLINE14_SR_TIM1_CC_Msk (0x1UL << SYSCFG_ITLINE14_SR_TIM1_CC_Pos) /*!< 0x00000001 */
  5545. #define SYSCFG_ITLINE14_SR_TIM1_CC SYSCFG_ITLINE14_SR_TIM1_CC_Msk /*!< TIM1 CC Interrupt */
  5546. #define SYSCFG_ITLINE15_SR_TIM2_GLB_Pos (0U)
  5547. #define SYSCFG_ITLINE15_SR_TIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE15_SR_TIM2_GLB_Pos) /*!< 0x00000001 */
  5548. #define SYSCFG_ITLINE15_SR_TIM2_GLB SYSCFG_ITLINE15_SR_TIM2_GLB_Msk /*!< TIM2 GLB Interrupt */
  5549. #define SYSCFG_ITLINE16_SR_TIM3_GLB_Pos (0U)
  5550. #define SYSCFG_ITLINE16_SR_TIM3_GLB_Msk (0x1UL << SYSCFG_ITLINE16_SR_TIM3_GLB_Pos) /*!< 0x00000001 */
  5551. #define SYSCFG_ITLINE16_SR_TIM3_GLB SYSCFG_ITLINE16_SR_TIM3_GLB_Msk /*!< TIM3 GLB Interrupt */
  5552. #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos (2U)
  5553. #define SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk (0x1UL << SYSCFG_ITLINE17_SR_LPTIM1_GLB_Pos) /*!< 0x00000004 */
  5554. #define SYSCFG_ITLINE17_SR_LPTIM1_GLB SYSCFG_ITLINE17_SR_LPTIM1_GLB_Msk /*!< LPTIM1 -> exti[29] Interrupt */
  5555. #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos (1U)
  5556. #define SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk (0x1UL << SYSCFG_ITLINE18_SR_LPTIM2_GLB_Pos) /*!< 0x00000002 */
  5557. #define SYSCFG_ITLINE18_SR_LPTIM2_GLB SYSCFG_ITLINE18_SR_LPTIM2_GLB_Msk /*!< LPTIM2 -> exti[30] Interrupt */
  5558. #define SYSCFG_ITLINE19_SR_TIM14_GLB_Pos (0U)
  5559. #define SYSCFG_ITLINE19_SR_TIM14_GLB_Msk (0x1UL << SYSCFG_ITLINE19_SR_TIM14_GLB_Pos) /*!< 0x00000001 */
  5560. #define SYSCFG_ITLINE19_SR_TIM14_GLB SYSCFG_ITLINE19_SR_TIM14_GLB_Msk /*!< TIM14 GLB Interrupt */
  5561. #define SYSCFG_ITLINE21_SR_TIM16_GLB_Pos (0U)
  5562. #define SYSCFG_ITLINE21_SR_TIM16_GLB_Msk (0x1UL << SYSCFG_ITLINE21_SR_TIM16_GLB_Pos) /*!< 0x00000001 */
  5563. #define SYSCFG_ITLINE21_SR_TIM16_GLB SYSCFG_ITLINE21_SR_TIM16_GLB_Msk /*!< TIM16 GLB Interrupt */
  5564. #define SYSCFG_ITLINE22_SR_TIM17_GLB_Pos (0U)
  5565. #define SYSCFG_ITLINE22_SR_TIM17_GLB_Msk (0x1UL << SYSCFG_ITLINE22_SR_TIM17_GLB_Pos) /*!< 0x00000001 */
  5566. #define SYSCFG_ITLINE22_SR_TIM17_GLB SYSCFG_ITLINE22_SR_TIM17_GLB_Msk /*!< TIM17 GLB Interrupt */
  5567. #define SYSCFG_ITLINE23_SR_I2C1_GLB_Pos (0U)
  5568. #define SYSCFG_ITLINE23_SR_I2C1_GLB_Msk (0x1UL << SYSCFG_ITLINE23_SR_I2C1_GLB_Pos) /*!< 0x00000001 */
  5569. #define SYSCFG_ITLINE23_SR_I2C1_GLB SYSCFG_ITLINE23_SR_I2C1_GLB_Msk /*!< I2C1 GLB Interrupt -> exti[23] */
  5570. #define SYSCFG_ITLINE24_SR_I2C2_GLB_Pos (0U)
  5571. #define SYSCFG_ITLINE24_SR_I2C2_GLB_Msk (0x1UL << SYSCFG_ITLINE24_SR_I2C2_GLB_Pos) /*!< 0x00000001 */
  5572. #define SYSCFG_ITLINE24_SR_I2C2_GLB SYSCFG_ITLINE24_SR_I2C2_GLB_Msk /*!< I2C2 GLB Interrupt */
  5573. #define SYSCFG_ITLINE25_SR_SPI1_Pos (0U)
  5574. #define SYSCFG_ITLINE25_SR_SPI1_Msk (0x1UL << SYSCFG_ITLINE25_SR_SPI1_Pos) /*!< 0x00000001 */
  5575. #define SYSCFG_ITLINE25_SR_SPI1 SYSCFG_ITLINE25_SR_SPI1_Msk /*!< SPI1 Interrupt */
  5576. #define SYSCFG_ITLINE26_SR_SPI2_Pos (0U)
  5577. #define SYSCFG_ITLINE26_SR_SPI2_Msk (0x1UL << SYSCFG_ITLINE26_SR_SPI2_Pos) /*!< 0x00000001 */
  5578. #define SYSCFG_ITLINE26_SR_SPI2 SYSCFG_ITLINE26_SR_SPI2_Msk /*!< SPI2 Interrupt */
  5579. #define SYSCFG_ITLINE27_SR_USART1_GLB_Pos (0U)
  5580. #define SYSCFG_ITLINE27_SR_USART1_GLB_Msk (0x1UL << SYSCFG_ITLINE27_SR_USART1_GLB_Pos) /*!< 0x00000001 */
  5581. #define SYSCFG_ITLINE27_SR_USART1_GLB SYSCFG_ITLINE27_SR_USART1_GLB_Msk /*!< USART1 GLB Interrupt -> exti[25] */
  5582. #define SYSCFG_ITLINE28_SR_USART2_GLB_Pos (0U)
  5583. #define SYSCFG_ITLINE28_SR_USART2_GLB_Msk (0x1UL << SYSCFG_ITLINE28_SR_USART2_GLB_Pos) /*!< 0x00000001 */
  5584. #define SYSCFG_ITLINE28_SR_USART2_GLB SYSCFG_ITLINE28_SR_USART2_GLB_Msk /*!< USART2 GLB Interrupt -> exti[26] */
  5585. #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos (2U)
  5586. #define SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk (0x1UL << SYSCFG_ITLINE29_SR_LPUART1_GLB_Pos) /*!< 0x00000004 */
  5587. #define SYSCFG_ITLINE29_SR_LPUART1_GLB SYSCFG_ITLINE29_SR_LPUART1_GLB_Msk /*!< LPUART1 GLB Interrupt -> exti[28] */
  5588. /******************************************************************************/
  5589. /* */
  5590. /* TIM */
  5591. /* */
  5592. /******************************************************************************/
  5593. /******************* Bit definition for TIM_CR1 register ********************/
  5594. #define TIM_CR1_CEN_Pos (0U)
  5595. #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
  5596. #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
  5597. #define TIM_CR1_UDIS_Pos (1U)
  5598. #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
  5599. #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
  5600. #define TIM_CR1_URS_Pos (2U)
  5601. #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
  5602. #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
  5603. #define TIM_CR1_OPM_Pos (3U)
  5604. #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
  5605. #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
  5606. #define TIM_CR1_DIR_Pos (4U)
  5607. #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
  5608. #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
  5609. #define TIM_CR1_CMS_Pos (5U)
  5610. #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
  5611. #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
  5612. #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
  5613. #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
  5614. #define TIM_CR1_ARPE_Pos (7U)
  5615. #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
  5616. #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
  5617. #define TIM_CR1_CKD_Pos (8U)
  5618. #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
  5619. #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
  5620. #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
  5621. #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
  5622. #define TIM_CR1_UIFREMAP_Pos (11U)
  5623. #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
  5624. #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
  5625. /******************* Bit definition for TIM_CR2 register ********************/
  5626. #define TIM_CR2_CCPC_Pos (0U)
  5627. #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
  5628. #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
  5629. #define TIM_CR2_CCUS_Pos (2U)
  5630. #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
  5631. #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
  5632. #define TIM_CR2_CCDS_Pos (3U)
  5633. #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
  5634. #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
  5635. #define TIM_CR2_MMS_Pos (4U)
  5636. #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
  5637. #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  5638. #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
  5639. #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
  5640. #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
  5641. #define TIM_CR2_TI1S_Pos (7U)
  5642. #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
  5643. #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
  5644. #define TIM_CR2_OIS1_Pos (8U)
  5645. #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
  5646. #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
  5647. #define TIM_CR2_OIS1N_Pos (9U)
  5648. #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
  5649. #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
  5650. #define TIM_CR2_OIS2_Pos (10U)
  5651. #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
  5652. #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
  5653. #define TIM_CR2_OIS2N_Pos (11U)
  5654. #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
  5655. #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
  5656. #define TIM_CR2_OIS3_Pos (12U)
  5657. #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
  5658. #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
  5659. #define TIM_CR2_OIS3N_Pos (13U)
  5660. #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
  5661. #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
  5662. #define TIM_CR2_OIS4_Pos (14U)
  5663. #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
  5664. #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
  5665. #define TIM_CR2_OIS5_Pos (16U)
  5666. #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
  5667. #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
  5668. #define TIM_CR2_OIS6_Pos (18U)
  5669. #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
  5670. #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
  5671. #define TIM_CR2_MMS2_Pos (20U)
  5672. #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
  5673. #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
  5674. #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
  5675. #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
  5676. #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
  5677. #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
  5678. /******************* Bit definition for TIM_SMCR register *******************/
  5679. #define TIM_SMCR_SMS_Pos (0U)
  5680. #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
  5681. #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
  5682. #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
  5683. #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
  5684. #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
  5685. #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
  5686. #define TIM_SMCR_OCCS_Pos (3U)
  5687. #define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
  5688. #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
  5689. #define TIM_SMCR_TS_Pos (4U)
  5690. #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
  5691. #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
  5692. #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
  5693. #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
  5694. #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
  5695. #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
  5696. #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
  5697. #define TIM_SMCR_MSM_Pos (7U)
  5698. #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
  5699. #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
  5700. #define TIM_SMCR_ETF_Pos (8U)
  5701. #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
  5702. #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
  5703. #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
  5704. #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
  5705. #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
  5706. #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
  5707. #define TIM_SMCR_ETPS_Pos (12U)
  5708. #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
  5709. #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
  5710. #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
  5711. #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
  5712. #define TIM_SMCR_ECE_Pos (14U)
  5713. #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
  5714. #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
  5715. #define TIM_SMCR_ETP_Pos (15U)
  5716. #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
  5717. #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
  5718. /******************* Bit definition for TIM_DIER register *******************/
  5719. #define TIM_DIER_UIE_Pos (0U)
  5720. #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
  5721. #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
  5722. #define TIM_DIER_CC1IE_Pos (1U)
  5723. #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
  5724. #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
  5725. #define TIM_DIER_CC2IE_Pos (2U)
  5726. #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
  5727. #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
  5728. #define TIM_DIER_CC3IE_Pos (3U)
  5729. #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
  5730. #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
  5731. #define TIM_DIER_CC4IE_Pos (4U)
  5732. #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
  5733. #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
  5734. #define TIM_DIER_COMIE_Pos (5U)
  5735. #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
  5736. #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
  5737. #define TIM_DIER_TIE_Pos (6U)
  5738. #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
  5739. #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
  5740. #define TIM_DIER_BIE_Pos (7U)
  5741. #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
  5742. #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
  5743. #define TIM_DIER_UDE_Pos (8U)
  5744. #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
  5745. #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
  5746. #define TIM_DIER_CC1DE_Pos (9U)
  5747. #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
  5748. #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
  5749. #define TIM_DIER_CC2DE_Pos (10U)
  5750. #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
  5751. #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
  5752. #define TIM_DIER_CC3DE_Pos (11U)
  5753. #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
  5754. #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
  5755. #define TIM_DIER_CC4DE_Pos (12U)
  5756. #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
  5757. #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
  5758. #define TIM_DIER_COMDE_Pos (13U)
  5759. #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
  5760. #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
  5761. #define TIM_DIER_TDE_Pos (14U)
  5762. #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
  5763. #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
  5764. /******************** Bit definition for TIM_SR register ********************/
  5765. #define TIM_SR_UIF_Pos (0U)
  5766. #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
  5767. #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
  5768. #define TIM_SR_CC1IF_Pos (1U)
  5769. #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
  5770. #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
  5771. #define TIM_SR_CC2IF_Pos (2U)
  5772. #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
  5773. #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
  5774. #define TIM_SR_CC3IF_Pos (3U)
  5775. #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
  5776. #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
  5777. #define TIM_SR_CC4IF_Pos (4U)
  5778. #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
  5779. #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
  5780. #define TIM_SR_COMIF_Pos (5U)
  5781. #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
  5782. #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
  5783. #define TIM_SR_TIF_Pos (6U)
  5784. #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
  5785. #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
  5786. #define TIM_SR_BIF_Pos (7U)
  5787. #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
  5788. #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
  5789. #define TIM_SR_B2IF_Pos (8U)
  5790. #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
  5791. #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
  5792. #define TIM_SR_CC1OF_Pos (9U)
  5793. #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
  5794. #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
  5795. #define TIM_SR_CC2OF_Pos (10U)
  5796. #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
  5797. #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
  5798. #define TIM_SR_CC3OF_Pos (11U)
  5799. #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
  5800. #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
  5801. #define TIM_SR_CC4OF_Pos (12U)
  5802. #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
  5803. #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
  5804. #define TIM_SR_SBIF_Pos (13U)
  5805. #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
  5806. #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
  5807. #define TIM_SR_CC5IF_Pos (16U)
  5808. #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
  5809. #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
  5810. #define TIM_SR_CC6IF_Pos (17U)
  5811. #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
  5812. #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
  5813. /******************* Bit definition for TIM_EGR register ********************/
  5814. #define TIM_EGR_UG_Pos (0U)
  5815. #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
  5816. #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
  5817. #define TIM_EGR_CC1G_Pos (1U)
  5818. #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
  5819. #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
  5820. #define TIM_EGR_CC2G_Pos (2U)
  5821. #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
  5822. #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
  5823. #define TIM_EGR_CC3G_Pos (3U)
  5824. #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
  5825. #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
  5826. #define TIM_EGR_CC4G_Pos (4U)
  5827. #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
  5828. #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
  5829. #define TIM_EGR_COMG_Pos (5U)
  5830. #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
  5831. #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
  5832. #define TIM_EGR_TG_Pos (6U)
  5833. #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
  5834. #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
  5835. #define TIM_EGR_BG_Pos (7U)
  5836. #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
  5837. #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
  5838. #define TIM_EGR_B2G_Pos (8U)
  5839. #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
  5840. #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
  5841. /****************** Bit definition for TIM_CCMR1 register *******************/
  5842. #define TIM_CCMR1_CC1S_Pos (0U)
  5843. #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
  5844. #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
  5845. #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
  5846. #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
  5847. #define TIM_CCMR1_OC1FE_Pos (2U)
  5848. #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
  5849. #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
  5850. #define TIM_CCMR1_OC1PE_Pos (3U)
  5851. #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
  5852. #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
  5853. #define TIM_CCMR1_OC1M_Pos (4U)
  5854. #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
  5855. #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
  5856. #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
  5857. #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
  5858. #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
  5859. #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
  5860. #define TIM_CCMR1_OC1CE_Pos (7U)
  5861. #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
  5862. #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
  5863. #define TIM_CCMR1_CC2S_Pos (8U)
  5864. #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
  5865. #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
  5866. #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
  5867. #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
  5868. #define TIM_CCMR1_OC2FE_Pos (10U)
  5869. #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
  5870. #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
  5871. #define TIM_CCMR1_OC2PE_Pos (11U)
  5872. #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
  5873. #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
  5874. #define TIM_CCMR1_OC2M_Pos (12U)
  5875. #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
  5876. #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
  5877. #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
  5878. #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
  5879. #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
  5880. #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
  5881. #define TIM_CCMR1_OC2CE_Pos (15U)
  5882. #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
  5883. #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
  5884. /*----------------------------------------------------------------------------*/
  5885. #define TIM_CCMR1_IC1PSC_Pos (2U)
  5886. #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
  5887. #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
  5888. #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
  5889. #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
  5890. #define TIM_CCMR1_IC1F_Pos (4U)
  5891. #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
  5892. #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
  5893. #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
  5894. #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
  5895. #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
  5896. #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
  5897. #define TIM_CCMR1_IC2PSC_Pos (10U)
  5898. #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
  5899. #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
  5900. #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
  5901. #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
  5902. #define TIM_CCMR1_IC2F_Pos (12U)
  5903. #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
  5904. #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
  5905. #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
  5906. #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
  5907. #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
  5908. #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
  5909. /****************** Bit definition for TIM_CCMR2 register *******************/
  5910. #define TIM_CCMR2_CC3S_Pos (0U)
  5911. #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
  5912. #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
  5913. #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
  5914. #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
  5915. #define TIM_CCMR2_OC3FE_Pos (2U)
  5916. #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
  5917. #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
  5918. #define TIM_CCMR2_OC3PE_Pos (3U)
  5919. #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
  5920. #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
  5921. #define TIM_CCMR2_OC3M_Pos (4U)
  5922. #define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
  5923. #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
  5924. #define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
  5925. #define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
  5926. #define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
  5927. #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
  5928. #define TIM_CCMR2_OC3CE_Pos (7U)
  5929. #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
  5930. #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
  5931. #define TIM_CCMR2_CC4S_Pos (8U)
  5932. #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
  5933. #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
  5934. #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
  5935. #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
  5936. #define TIM_CCMR2_OC4FE_Pos (10U)
  5937. #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
  5938. #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
  5939. #define TIM_CCMR2_OC4PE_Pos (11U)
  5940. #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
  5941. #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
  5942. #define TIM_CCMR2_OC4M_Pos (12U)
  5943. #define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
  5944. #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
  5945. #define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
  5946. #define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
  5947. #define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
  5948. #define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
  5949. #define TIM_CCMR2_OC4CE_Pos (15U)
  5950. #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
  5951. #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
  5952. /*----------------------------------------------------------------------------*/
  5953. #define TIM_CCMR2_IC3PSC_Pos (2U)
  5954. #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
  5955. #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
  5956. #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
  5957. #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
  5958. #define TIM_CCMR2_IC3F_Pos (4U)
  5959. #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
  5960. #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
  5961. #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
  5962. #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
  5963. #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
  5964. #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
  5965. #define TIM_CCMR2_IC4PSC_Pos (10U)
  5966. #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
  5967. #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
  5968. #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
  5969. #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
  5970. #define TIM_CCMR2_IC4F_Pos (12U)
  5971. #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
  5972. #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
  5973. #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
  5974. #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
  5975. #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
  5976. #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
  5977. /****************** Bit definition for TIM_CCMR3 register *******************/
  5978. #define TIM_CCMR3_OC5FE_Pos (2U)
  5979. #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
  5980. #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
  5981. #define TIM_CCMR3_OC5PE_Pos (3U)
  5982. #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
  5983. #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
  5984. #define TIM_CCMR3_OC5M_Pos (4U)
  5985. #define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
  5986. #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
  5987. #define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
  5988. #define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
  5989. #define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
  5990. #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
  5991. #define TIM_CCMR3_OC5CE_Pos (7U)
  5992. #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
  5993. #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
  5994. #define TIM_CCMR3_OC6FE_Pos (10U)
  5995. #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
  5996. #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
  5997. #define TIM_CCMR3_OC6PE_Pos (11U)
  5998. #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
  5999. #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
  6000. #define TIM_CCMR3_OC6M_Pos (12U)
  6001. #define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
  6002. #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
  6003. #define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
  6004. #define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
  6005. #define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
  6006. #define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
  6007. #define TIM_CCMR3_OC6CE_Pos (15U)
  6008. #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
  6009. #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
  6010. /******************* Bit definition for TIM_CCER register *******************/
  6011. #define TIM_CCER_CC1E_Pos (0U)
  6012. #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
  6013. #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
  6014. #define TIM_CCER_CC1P_Pos (1U)
  6015. #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
  6016. #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
  6017. #define TIM_CCER_CC1NE_Pos (2U)
  6018. #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
  6019. #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
  6020. #define TIM_CCER_CC1NP_Pos (3U)
  6021. #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
  6022. #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
  6023. #define TIM_CCER_CC2E_Pos (4U)
  6024. #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
  6025. #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
  6026. #define TIM_CCER_CC2P_Pos (5U)
  6027. #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
  6028. #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
  6029. #define TIM_CCER_CC2NE_Pos (6U)
  6030. #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
  6031. #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
  6032. #define TIM_CCER_CC2NP_Pos (7U)
  6033. #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
  6034. #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
  6035. #define TIM_CCER_CC3E_Pos (8U)
  6036. #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
  6037. #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
  6038. #define TIM_CCER_CC3P_Pos (9U)
  6039. #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
  6040. #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
  6041. #define TIM_CCER_CC3NE_Pos (10U)
  6042. #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
  6043. #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
  6044. #define TIM_CCER_CC3NP_Pos (11U)
  6045. #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
  6046. #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
  6047. #define TIM_CCER_CC4E_Pos (12U)
  6048. #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
  6049. #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
  6050. #define TIM_CCER_CC4P_Pos (13U)
  6051. #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
  6052. #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
  6053. #define TIM_CCER_CC4NP_Pos (15U)
  6054. #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
  6055. #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
  6056. #define TIM_CCER_CC5E_Pos (16U)
  6057. #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
  6058. #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
  6059. #define TIM_CCER_CC5P_Pos (17U)
  6060. #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
  6061. #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
  6062. #define TIM_CCER_CC6E_Pos (20U)
  6063. #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
  6064. #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
  6065. #define TIM_CCER_CC6P_Pos (21U)
  6066. #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
  6067. #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
  6068. /******************* Bit definition for TIM_CNT register ********************/
  6069. #define TIM_CNT_CNT_Pos (0U)
  6070. #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
  6071. #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
  6072. #define TIM_CNT_UIFCPY_Pos (31U)
  6073. #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
  6074. #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
  6075. /******************* Bit definition for TIM_PSC register ********************/
  6076. #define TIM_PSC_PSC_Pos (0U)
  6077. #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
  6078. #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
  6079. /******************* Bit definition for TIM_ARR register ********************/
  6080. #define TIM_ARR_ARR_Pos (0U)
  6081. #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
  6082. #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
  6083. /******************* Bit definition for TIM_RCR register ********************/
  6084. #define TIM_RCR_REP_Pos (0U)
  6085. #define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
  6086. #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
  6087. /******************* Bit definition for TIM_CCR1 register *******************/
  6088. #define TIM_CCR1_CCR1_Pos (0U)
  6089. #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
  6090. #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
  6091. /******************* Bit definition for TIM_CCR2 register *******************/
  6092. #define TIM_CCR2_CCR2_Pos (0U)
  6093. #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
  6094. #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
  6095. /******************* Bit definition for TIM_CCR3 register *******************/
  6096. #define TIM_CCR3_CCR3_Pos (0U)
  6097. #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
  6098. #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
  6099. /******************* Bit definition for TIM_CCR4 register *******************/
  6100. #define TIM_CCR4_CCR4_Pos (0U)
  6101. #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
  6102. #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
  6103. /******************* Bit definition for TIM_CCR5 register *******************/
  6104. #define TIM_CCR5_CCR5_Pos (0U)
  6105. #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
  6106. #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
  6107. #define TIM_CCR5_GC5C1_Pos (29U)
  6108. #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
  6109. #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
  6110. #define TIM_CCR5_GC5C2_Pos (30U)
  6111. #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
  6112. #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
  6113. #define TIM_CCR5_GC5C3_Pos (31U)
  6114. #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
  6115. #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
  6116. /******************* Bit definition for TIM_CCR6 register *******************/
  6117. #define TIM_CCR6_CCR6_Pos (0U)
  6118. #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
  6119. #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
  6120. /******************* Bit definition for TIM_BDTR register *******************/
  6121. #define TIM_BDTR_DTG_Pos (0U)
  6122. #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
  6123. #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
  6124. #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
  6125. #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
  6126. #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
  6127. #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
  6128. #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
  6129. #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
  6130. #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
  6131. #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
  6132. #define TIM_BDTR_LOCK_Pos (8U)
  6133. #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
  6134. #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
  6135. #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
  6136. #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
  6137. #define TIM_BDTR_OSSI_Pos (10U)
  6138. #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
  6139. #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
  6140. #define TIM_BDTR_OSSR_Pos (11U)
  6141. #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
  6142. #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
  6143. #define TIM_BDTR_BKE_Pos (12U)
  6144. #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
  6145. #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
  6146. #define TIM_BDTR_BKP_Pos (13U)
  6147. #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
  6148. #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
  6149. #define TIM_BDTR_AOE_Pos (14U)
  6150. #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
  6151. #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
  6152. #define TIM_BDTR_MOE_Pos (15U)
  6153. #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
  6154. #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
  6155. #define TIM_BDTR_BKF_Pos (16U)
  6156. #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
  6157. #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
  6158. #define TIM_BDTR_BK2F_Pos (20U)
  6159. #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
  6160. #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
  6161. #define TIM_BDTR_BK2E_Pos (24U)
  6162. #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
  6163. #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
  6164. #define TIM_BDTR_BK2P_Pos (25U)
  6165. #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
  6166. #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
  6167. #define TIM_BDTR_BKDSRM_Pos (26U)
  6168. #define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
  6169. #define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
  6170. #define TIM_BDTR_BK2DSRM_Pos (27U)
  6171. #define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
  6172. #define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
  6173. #define TIM_BDTR_BKBID_Pos (28U)
  6174. #define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
  6175. #define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
  6176. #define TIM_BDTR_BK2BID_Pos (29U)
  6177. #define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
  6178. #define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
  6179. /******************* Bit definition for TIM_DCR register ********************/
  6180. #define TIM_DCR_DBA_Pos (0U)
  6181. #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
  6182. #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
  6183. #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
  6184. #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
  6185. #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
  6186. #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
  6187. #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
  6188. #define TIM_DCR_DBL_Pos (8U)
  6189. #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
  6190. #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
  6191. #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
  6192. #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
  6193. #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
  6194. #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
  6195. #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
  6196. /******************* Bit definition for TIM_DMAR register *******************/
  6197. #define TIM_DMAR_DMAB_Pos (0U)
  6198. #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
  6199. #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
  6200. /******************* Bit definition for TIM1_OR1 register *******************/
  6201. #define TIM1_OR1_OCREF_CLR_Pos (0U)
  6202. #define TIM1_OR1_OCREF_CLR_Msk (0x1UL << TIM1_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
  6203. #define TIM1_OR1_OCREF_CLR TIM1_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
  6204. /******************* Bit definition for TIM1_AF1 register *******************/
  6205. #define TIM1_AF1_BKINE_Pos (0U)
  6206. #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
  6207. #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
  6208. #define TIM1_AF1_BKCMP1E_Pos (1U)
  6209. #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
  6210. #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
  6211. #define TIM1_AF1_BKCMP2E_Pos (2U)
  6212. #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
  6213. #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
  6214. #define TIM1_AF1_BKINP_Pos (9U)
  6215. #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
  6216. #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
  6217. #define TIM1_AF1_BKCMP1P_Pos (10U)
  6218. #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
  6219. #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  6220. #define TIM1_AF1_BKCMP2P_Pos (11U)
  6221. #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
  6222. #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  6223. #define TIM1_AF1_ETRSEL_Pos (14U)
  6224. #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
  6225. #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
  6226. #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
  6227. #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
  6228. #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
  6229. #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
  6230. /******************* Bit definition for TIM1_AF2 register *******************/
  6231. #define TIM1_AF2_BK2INE_Pos (0U)
  6232. #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
  6233. #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN2 input enable */
  6234. #define TIM1_AF2_BK2CMP1E_Pos (1U)
  6235. #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
  6236. #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
  6237. #define TIM1_AF2_BK2CMP2E_Pos (2U)
  6238. #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
  6239. #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
  6240. #define TIM1_AF2_BK2INP_Pos (9U)
  6241. #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
  6242. #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN2 input polarity */
  6243. #define TIM1_AF2_BK2CMP1P_Pos (10U)
  6244. #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
  6245. #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
  6246. #define TIM1_AF2_BK2CMP2P_Pos (11U)
  6247. #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
  6248. #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
  6249. /******************* Bit definition for TIM2_OR1 register *******************/
  6250. #define TIM2_OR1_OCREF_CLR_Pos (0U)
  6251. #define TIM2_OR1_OCREF_CLR_Msk (0x1UL << TIM2_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
  6252. #define TIM2_OR1_OCREF_CLR TIM2_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
  6253. /******************* Bit definition for TIM2_AF1 register *******************/
  6254. #define TIM2_AF1_ETRSEL_Pos (14U)
  6255. #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
  6256. #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETR source selection) */
  6257. #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
  6258. #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
  6259. #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
  6260. #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
  6261. /******************* Bit definition for TIM3_OR1 register *******************/
  6262. #define TIM3_OR1_OCREF_CLR_Pos (0U)
  6263. #define TIM3_OR1_OCREF_CLR_Msk (0x1UL << TIM3_OR1_OCREF_CLR_Pos) /*!< 0x00000001 */
  6264. #define TIM3_OR1_OCREF_CLR TIM3_OR1_OCREF_CLR_Msk /*!<OCREF clear input selection */
  6265. /******************* Bit definition for TIM3_AF1 register *******************/
  6266. #define TIM3_AF1_ETRSEL_Pos (14U)
  6267. #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
  6268. #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
  6269. #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
  6270. #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
  6271. #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
  6272. #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
  6273. /******************* Bit definition for TIM14_AF1 register *******************/
  6274. #define TIM14_AF1_ETRSEL_Pos (14U)
  6275. #define TIM14_AF1_ETRSEL_Msk (0xFUL << TIM14_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
  6276. #define TIM14_AF1_ETRSEL TIM14_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETR source selection) */
  6277. #define TIM14_AF1_ETRSEL_0 (0x1UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00004000 */
  6278. #define TIM14_AF1_ETRSEL_1 (0x2UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00008000 */
  6279. #define TIM14_AF1_ETRSEL_2 (0x4UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00010000 */
  6280. #define TIM14_AF1_ETRSEL_3 (0x8UL << TIM14_AF1_ETRSEL_Pos) /*!< 0x00020000 */
  6281. /******************* Bit definition for TIM16_AF1 register ******************/
  6282. #define TIM16_AF1_BKINE_Pos (0U)
  6283. #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
  6284. #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BRK BKIN input enable */
  6285. #define TIM16_AF1_BKCMP1E_Pos (1U)
  6286. #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
  6287. #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
  6288. #define TIM16_AF1_BKCMP2E_Pos (2U)
  6289. #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
  6290. #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
  6291. #define TIM16_AF1_BKINP_Pos (9U)
  6292. #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
  6293. #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
  6294. #define TIM16_AF1_BKCMP1P_Pos (10U)
  6295. #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
  6296. #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  6297. #define TIM16_AF1_BKCMP2P_Pos (11U)
  6298. #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
  6299. #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  6300. /******************* Bit definition for TIM17_AF1 register ******************/
  6301. #define TIM17_AF1_BKINE_Pos (0U)
  6302. #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
  6303. #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BRK BKIN input enable */
  6304. #define TIM17_AF1_BKCMP1E_Pos (1U)
  6305. #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
  6306. #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
  6307. #define TIM17_AF1_BKCMP2E_Pos (2U)
  6308. #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
  6309. #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
  6310. #define TIM17_AF1_BKINP_Pos (9U)
  6311. #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
  6312. #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
  6313. #define TIM17_AF1_BKCMP1P_Pos (10U)
  6314. #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
  6315. #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
  6316. #define TIM17_AF1_BKCMP2P_Pos (11U)
  6317. #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
  6318. #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
  6319. /******************* Bit definition for TIM_TISEL register *********************/
  6320. #define TIM_TISEL_TI1SEL_Pos (0U)
  6321. #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
  6322. #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
  6323. #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
  6324. #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
  6325. #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
  6326. #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
  6327. #define TIM_TISEL_TI2SEL_Pos (8U)
  6328. #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
  6329. #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
  6330. #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
  6331. #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
  6332. #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
  6333. #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
  6334. #define TIM_TISEL_TI3SEL_Pos (16U)
  6335. #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
  6336. #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
  6337. #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
  6338. #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
  6339. #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
  6340. #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
  6341. #define TIM_TISEL_TI4SEL_Pos (24U)
  6342. #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
  6343. #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
  6344. #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
  6345. #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
  6346. #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
  6347. #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
  6348. /******************************************************************************/
  6349. /* */
  6350. /* Low Power Timer (LPTIM) */
  6351. /* */
  6352. /******************************************************************************/
  6353. /****************** Bit definition for LPTIM_ISR register *******************/
  6354. #define LPTIM_ISR_CMPM_Pos (0U)
  6355. #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
  6356. #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
  6357. #define LPTIM_ISR_ARRM_Pos (1U)
  6358. #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
  6359. #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
  6360. #define LPTIM_ISR_EXTTRIG_Pos (2U)
  6361. #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
  6362. #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
  6363. #define LPTIM_ISR_CMPOK_Pos (3U)
  6364. #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
  6365. #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
  6366. #define LPTIM_ISR_ARROK_Pos (4U)
  6367. #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
  6368. #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
  6369. #define LPTIM_ISR_UP_Pos (5U)
  6370. #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
  6371. #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
  6372. #define LPTIM_ISR_DOWN_Pos (6U)
  6373. #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
  6374. #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
  6375. /****************** Bit definition for LPTIM_ICR register *******************/
  6376. #define LPTIM_ICR_CMPMCF_Pos (0U)
  6377. #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
  6378. #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
  6379. #define LPTIM_ICR_ARRMCF_Pos (1U)
  6380. #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
  6381. #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
  6382. #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
  6383. #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
  6384. #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
  6385. #define LPTIM_ICR_CMPOKCF_Pos (3U)
  6386. #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
  6387. #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
  6388. #define LPTIM_ICR_ARROKCF_Pos (4U)
  6389. #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
  6390. #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
  6391. #define LPTIM_ICR_UPCF_Pos (5U)
  6392. #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
  6393. #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
  6394. #define LPTIM_ICR_DOWNCF_Pos (6U)
  6395. #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
  6396. #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
  6397. /****************** Bit definition for LPTIM_IER register ********************/
  6398. #define LPTIM_IER_CMPMIE_Pos (0U)
  6399. #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
  6400. #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
  6401. #define LPTIM_IER_ARRMIE_Pos (1U)
  6402. #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
  6403. #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
  6404. #define LPTIM_IER_EXTTRIGIE_Pos (2U)
  6405. #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
  6406. #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
  6407. #define LPTIM_IER_CMPOKIE_Pos (3U)
  6408. #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
  6409. #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
  6410. #define LPTIM_IER_ARROKIE_Pos (4U)
  6411. #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
  6412. #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
  6413. #define LPTIM_IER_UPIE_Pos (5U)
  6414. #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
  6415. #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
  6416. #define LPTIM_IER_DOWNIE_Pos (6U)
  6417. #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
  6418. #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
  6419. /****************** Bit definition for LPTIM_CFGR register *******************/
  6420. #define LPTIM_CFGR_CKSEL_Pos (0U)
  6421. #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
  6422. #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
  6423. #define LPTIM_CFGR_CKPOL_Pos (1U)
  6424. #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
  6425. #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
  6426. #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
  6427. #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
  6428. #define LPTIM_CFGR_CKFLT_Pos (3U)
  6429. #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
  6430. #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
  6431. #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
  6432. #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
  6433. #define LPTIM_CFGR_TRGFLT_Pos (6U)
  6434. #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
  6435. #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
  6436. #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
  6437. #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
  6438. #define LPTIM_CFGR_PRESC_Pos (9U)
  6439. #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
  6440. #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
  6441. #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
  6442. #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
  6443. #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
  6444. #define LPTIM_CFGR_TRIGSEL_Pos (13U)
  6445. #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
  6446. #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
  6447. #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
  6448. #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
  6449. #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
  6450. #define LPTIM_CFGR_TRIGEN_Pos (17U)
  6451. #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
  6452. #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
  6453. #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
  6454. #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
  6455. #define LPTIM_CFGR_TIMOUT_Pos (19U)
  6456. #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
  6457. #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
  6458. #define LPTIM_CFGR_WAVE_Pos (20U)
  6459. #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
  6460. #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
  6461. #define LPTIM_CFGR_WAVPOL_Pos (21U)
  6462. #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
  6463. #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
  6464. #define LPTIM_CFGR_PRELOAD_Pos (22U)
  6465. #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
  6466. #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
  6467. #define LPTIM_CFGR_COUNTMODE_Pos (23U)
  6468. #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
  6469. #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
  6470. #define LPTIM_CFGR_ENC_Pos (24U)
  6471. #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
  6472. #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
  6473. /****************** Bit definition for LPTIM_CR register ********************/
  6474. #define LPTIM_CR_ENABLE_Pos (0U)
  6475. #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
  6476. #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
  6477. #define LPTIM_CR_SNGSTRT_Pos (1U)
  6478. #define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
  6479. #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
  6480. #define LPTIM_CR_CNTSTRT_Pos (2U)
  6481. #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
  6482. #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
  6483. #define LPTIM_CR_COUNTRST_Pos (3U)
  6484. #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
  6485. #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
  6486. #define LPTIM_CR_RSTARE_Pos (4U)
  6487. #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
  6488. #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
  6489. /****************** Bit definition for LPTIM_CMP register *******************/
  6490. #define LPTIM_CMP_CMP_Pos (0U)
  6491. #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
  6492. #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
  6493. /****************** Bit definition for LPTIM_ARR register *******************/
  6494. #define LPTIM_ARR_ARR_Pos (0U)
  6495. #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
  6496. #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
  6497. /****************** Bit definition for LPTIM_CNT register *******************/
  6498. #define LPTIM_CNT_CNT_Pos (0U)
  6499. #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
  6500. #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
  6501. /****************** Bit definition for LPTIM_CFGR2 register *******************/
  6502. #define LPTIM_CFGR2_IN1SEL_Pos (0U)
  6503. #define LPTIM_CFGR2_IN1SEL_Msk (0xFUL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x0000000F */
  6504. #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< CFGR2[3:0] bits (INPUT1 selection) */
  6505. #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
  6506. #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
  6507. #define LPTIM_CFGR2_IN1SEL_2 (0x4UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000004 */
  6508. #define LPTIM_CFGR2_IN1SEL_3 (0x8UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000008 */
  6509. #define LPTIM_CFGR2_IN2SEL_Pos (4U)
  6510. #define LPTIM_CFGR2_IN2SEL_Msk (0xFUL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x000000F0 */
  6511. #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< CFGR2[7:4] bits (INPUT2 selection) */
  6512. #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
  6513. #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
  6514. #define LPTIM_CFGR2_IN2SEL_2 (0x4UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000040 */
  6515. #define LPTIM_CFGR2_IN2SEL_3 (0x8UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000080 */
  6516. /******************************************************************************/
  6517. /* */
  6518. /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
  6519. /* */
  6520. /******************************************************************************/
  6521. /****************** Bit definition for USART_CR1 register *******************/
  6522. #define USART_CR1_UE_Pos (0U)
  6523. #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
  6524. #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
  6525. #define USART_CR1_UESM_Pos (1U)
  6526. #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
  6527. #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
  6528. #define USART_CR1_RE_Pos (2U)
  6529. #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
  6530. #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
  6531. #define USART_CR1_TE_Pos (3U)
  6532. #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
  6533. #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
  6534. #define USART_CR1_IDLEIE_Pos (4U)
  6535. #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
  6536. #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
  6537. #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
  6538. #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
  6539. #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE/RXFIFO not empty Interrupt Enable */
  6540. #define USART_CR1_TCIE_Pos (6U)
  6541. #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
  6542. #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
  6543. #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
  6544. #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
  6545. #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE/TXFIFO not full Interrupt Enable */
  6546. #define USART_CR1_PEIE_Pos (8U)
  6547. #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
  6548. #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
  6549. #define USART_CR1_PS_Pos (9U)
  6550. #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
  6551. #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
  6552. #define USART_CR1_PCE_Pos (10U)
  6553. #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
  6554. #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
  6555. #define USART_CR1_WAKE_Pos (11U)
  6556. #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
  6557. #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
  6558. #define USART_CR1_M_Pos (12U)
  6559. #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
  6560. #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
  6561. #define USART_CR1_M0_Pos (12U)
  6562. #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
  6563. #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
  6564. #define USART_CR1_MME_Pos (13U)
  6565. #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
  6566. #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
  6567. #define USART_CR1_CMIE_Pos (14U)
  6568. #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
  6569. #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
  6570. #define USART_CR1_OVER8_Pos (15U)
  6571. #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
  6572. #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
  6573. #define USART_CR1_DEDT_Pos (16U)
  6574. #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
  6575. #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
  6576. #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
  6577. #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
  6578. #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
  6579. #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
  6580. #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
  6581. #define USART_CR1_DEAT_Pos (21U)
  6582. #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
  6583. #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
  6584. #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
  6585. #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
  6586. #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
  6587. #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
  6588. #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
  6589. #define USART_CR1_RTOIE_Pos (26U)
  6590. #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
  6591. #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
  6592. #define USART_CR1_EOBIE_Pos (27U)
  6593. #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
  6594. #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
  6595. #define USART_CR1_M1_Pos (28U)
  6596. #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
  6597. #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
  6598. #define USART_CR1_FIFOEN_Pos (29U)
  6599. #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
  6600. #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
  6601. #define USART_CR1_TXFEIE_Pos (30U)
  6602. #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
  6603. #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
  6604. #define USART_CR1_RXFFIE_Pos (31U)
  6605. #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
  6606. #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
  6607. /****************** Bit definition for USART_CR2 register *******************/
  6608. #define USART_CR2_SLVEN_Pos (0U)
  6609. #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
  6610. #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
  6611. #define USART_CR2_DIS_NSS_Pos (3U)
  6612. #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
  6613. #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< NSS input pin disable for SPI slave selection */
  6614. #define USART_CR2_ADDM7_Pos (4U)
  6615. #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
  6616. #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
  6617. #define USART_CR2_LBDL_Pos (5U)
  6618. #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
  6619. #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
  6620. #define USART_CR2_LBDIE_Pos (6U)
  6621. #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
  6622. #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
  6623. #define USART_CR2_LBCL_Pos (8U)
  6624. #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
  6625. #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
  6626. #define USART_CR2_CPHA_Pos (9U)
  6627. #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
  6628. #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
  6629. #define USART_CR2_CPOL_Pos (10U)
  6630. #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
  6631. #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
  6632. #define USART_CR2_CLKEN_Pos (11U)
  6633. #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
  6634. #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
  6635. #define USART_CR2_STOP_Pos (12U)
  6636. #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
  6637. #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
  6638. #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
  6639. #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
  6640. #define USART_CR2_LINEN_Pos (14U)
  6641. #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
  6642. #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
  6643. #define USART_CR2_SWAP_Pos (15U)
  6644. #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
  6645. #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
  6646. #define USART_CR2_RXINV_Pos (16U)
  6647. #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
  6648. #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
  6649. #define USART_CR2_TXINV_Pos (17U)
  6650. #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
  6651. #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
  6652. #define USART_CR2_DATAINV_Pos (18U)
  6653. #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
  6654. #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
  6655. #define USART_CR2_MSBFIRST_Pos (19U)
  6656. #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
  6657. #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
  6658. #define USART_CR2_ABREN_Pos (20U)
  6659. #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
  6660. #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
  6661. #define USART_CR2_ABRMODE_Pos (21U)
  6662. #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
  6663. #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
  6664. #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
  6665. #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
  6666. #define USART_CR2_RTOEN_Pos (23U)
  6667. #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
  6668. #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
  6669. #define USART_CR2_ADD_Pos (24U)
  6670. #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
  6671. #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
  6672. /****************** Bit definition for USART_CR3 register *******************/
  6673. #define USART_CR3_EIE_Pos (0U)
  6674. #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
  6675. #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
  6676. #define USART_CR3_IREN_Pos (1U)
  6677. #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
  6678. #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
  6679. #define USART_CR3_IRLP_Pos (2U)
  6680. #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
  6681. #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
  6682. #define USART_CR3_HDSEL_Pos (3U)
  6683. #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
  6684. #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
  6685. #define USART_CR3_NACK_Pos (4U)
  6686. #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
  6687. #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
  6688. #define USART_CR3_SCEN_Pos (5U)
  6689. #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
  6690. #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
  6691. #define USART_CR3_DMAR_Pos (6U)
  6692. #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
  6693. #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
  6694. #define USART_CR3_DMAT_Pos (7U)
  6695. #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
  6696. #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
  6697. #define USART_CR3_RTSE_Pos (8U)
  6698. #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
  6699. #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
  6700. #define USART_CR3_CTSE_Pos (9U)
  6701. #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
  6702. #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
  6703. #define USART_CR3_CTSIE_Pos (10U)
  6704. #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
  6705. #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
  6706. #define USART_CR3_ONEBIT_Pos (11U)
  6707. #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
  6708. #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
  6709. #define USART_CR3_OVRDIS_Pos (12U)
  6710. #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
  6711. #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
  6712. #define USART_CR3_DDRE_Pos (13U)
  6713. #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
  6714. #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
  6715. #define USART_CR3_DEM_Pos (14U)
  6716. #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
  6717. #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
  6718. #define USART_CR3_DEP_Pos (15U)
  6719. #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
  6720. #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
  6721. #define USART_CR3_SCARCNT_Pos (17U)
  6722. #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
  6723. #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
  6724. #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
  6725. #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
  6726. #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
  6727. #define USART_CR3_WUS_Pos (20U)
  6728. #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
  6729. #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
  6730. #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
  6731. #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
  6732. #define USART_CR3_WUFIE_Pos (22U)
  6733. #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
  6734. #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
  6735. #define USART_CR3_TXFTIE_Pos (23U)
  6736. #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
  6737. #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
  6738. #define USART_CR3_TCBGTIE_Pos (24U)
  6739. #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
  6740. #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
  6741. #define USART_CR3_RXFTCFG_Pos (25U)
  6742. #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
  6743. #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
  6744. #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
  6745. #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
  6746. #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
  6747. #define USART_CR3_RXFTIE_Pos (28U)
  6748. #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
  6749. #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
  6750. #define USART_CR3_TXFTCFG_Pos (29U)
  6751. #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
  6752. #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
  6753. #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
  6754. #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
  6755. #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
  6756. /****************** Bit definition for USART_BRR register *******************/
  6757. #define USART_BRR_LPUART_Pos (0U)
  6758. #define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
  6759. #define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
  6760. #define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */
  6761. /****************** Bit definition for USART_GTPR register ******************/
  6762. #define USART_GTPR_PSC_Pos (0U)
  6763. #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
  6764. #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
  6765. #define USART_GTPR_GT_Pos (8U)
  6766. #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
  6767. #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
  6768. /******************* Bit definition for USART_RTOR register *****************/
  6769. #define USART_RTOR_RTO_Pos (0U)
  6770. #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
  6771. #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
  6772. #define USART_RTOR_BLEN_Pos (24U)
  6773. #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
  6774. #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
  6775. /******************* Bit definition for USART_RQR register ******************/
  6776. #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
  6777. #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
  6778. #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
  6779. #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
  6780. #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
  6781. /******************* Bit definition for USART_ISR register ******************/
  6782. #define USART_ISR_PE_Pos (0U)
  6783. #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
  6784. #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
  6785. #define USART_ISR_FE_Pos (1U)
  6786. #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
  6787. #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
  6788. #define USART_ISR_NE_Pos (2U)
  6789. #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
  6790. #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
  6791. #define USART_ISR_ORE_Pos (3U)
  6792. #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
  6793. #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
  6794. #define USART_ISR_IDLE_Pos (4U)
  6795. #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
  6796. #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
  6797. #define USART_ISR_RXNE_RXFNE_Pos (5U)
  6798. #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
  6799. #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register Not Empty/RXFIFO Not Empty */
  6800. #define USART_ISR_TC_Pos (6U)
  6801. #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
  6802. #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
  6803. #define USART_ISR_TXE_TXFNF_Pos (7U)
  6804. #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
  6805. #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty/TXFIFO Not Full */
  6806. #define USART_ISR_LBDF_Pos (8U)
  6807. #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
  6808. #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
  6809. #define USART_ISR_CTSIF_Pos (9U)
  6810. #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
  6811. #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
  6812. #define USART_ISR_CTS_Pos (10U)
  6813. #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
  6814. #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
  6815. #define USART_ISR_RTOF_Pos (11U)
  6816. #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
  6817. #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
  6818. #define USART_ISR_EOBF_Pos (12U)
  6819. #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
  6820. #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
  6821. #define USART_ISR_UDR_Pos (13U)
  6822. #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
  6823. #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI Slave Underrun Error Flag */
  6824. #define USART_ISR_ABRE_Pos (14U)
  6825. #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
  6826. #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
  6827. #define USART_ISR_ABRF_Pos (15U)
  6828. #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
  6829. #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
  6830. #define USART_ISR_BUSY_Pos (16U)
  6831. #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
  6832. #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
  6833. #define USART_ISR_CMF_Pos (17U)
  6834. #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
  6835. #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
  6836. #define USART_ISR_SBKF_Pos (18U)
  6837. #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
  6838. #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
  6839. #define USART_ISR_RWU_Pos (19U)
  6840. #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
  6841. #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
  6842. #define USART_ISR_WUF_Pos (20U)
  6843. #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
  6844. #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
  6845. #define USART_ISR_TEACK_Pos (21U)
  6846. #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
  6847. #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
  6848. #define USART_ISR_REACK_Pos (22U)
  6849. #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
  6850. #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
  6851. #define USART_ISR_TXFE_Pos (23U)
  6852. #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
  6853. #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty Flag */
  6854. #define USART_ISR_RXFF_Pos (24U)
  6855. #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
  6856. #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
  6857. #define USART_ISR_TCBGT_Pos (25U)
  6858. #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
  6859. #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
  6860. #define USART_ISR_RXFT_Pos (26U)
  6861. #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
  6862. #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO Threshold Flag */
  6863. #define USART_ISR_TXFT_Pos (27U)
  6864. #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
  6865. #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO Threshold Flag */
  6866. /******************* Bit definition for USART_ICR register ******************/
  6867. #define USART_ICR_PECF_Pos (0U)
  6868. #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
  6869. #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
  6870. #define USART_ICR_FECF_Pos (1U)
  6871. #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
  6872. #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
  6873. #define USART_ICR_NECF_Pos (2U)
  6874. #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
  6875. #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise Error detected Clear Flag */
  6876. #define USART_ICR_ORECF_Pos (3U)
  6877. #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
  6878. #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
  6879. #define USART_ICR_IDLECF_Pos (4U)
  6880. #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
  6881. #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
  6882. #define USART_ICR_TXFECF_Pos (5U)
  6883. #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
  6884. #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO Empty Clear Flag */
  6885. #define USART_ICR_TCCF_Pos (6U)
  6886. #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
  6887. #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
  6888. #define USART_ICR_TCBGTCF_Pos (7U)
  6889. #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
  6890. #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
  6891. #define USART_ICR_LBDCF_Pos (8U)
  6892. #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
  6893. #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
  6894. #define USART_ICR_CTSCF_Pos (9U)
  6895. #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
  6896. #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
  6897. #define USART_ICR_RTOCF_Pos (11U)
  6898. #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
  6899. #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
  6900. #define USART_ICR_EOBCF_Pos (12U)
  6901. #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
  6902. #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
  6903. #define USART_ICR_UDRCF_Pos (13U)
  6904. #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
  6905. #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
  6906. #define USART_ICR_CMCF_Pos (17U)
  6907. #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
  6908. #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
  6909. #define USART_ICR_WUCF_Pos (20U)
  6910. #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
  6911. #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
  6912. /******************* Bit definition for USART_RDR register ******************/
  6913. #define USART_RDR_RDR_Pos (0U)
  6914. #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
  6915. #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
  6916. /******************* Bit definition for USART_TDR register ******************/
  6917. #define USART_TDR_TDR_Pos (0U)
  6918. #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
  6919. #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
  6920. /******************* Bit definition for USART_PRESC register ****************/
  6921. #define USART_PRESC_PRESCALER_Pos (0U)
  6922. #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
  6923. #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
  6924. #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
  6925. #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
  6926. #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
  6927. #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
  6928. /******************************************************************************/
  6929. /* */
  6930. /* VREFBUF */
  6931. /* */
  6932. /******************************************************************************/
  6933. /******************* Bit definition for VREFBUF_CSR register ****************/
  6934. #define VREFBUF_CSR_ENVR_Pos (0U)
  6935. #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
  6936. #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
  6937. #define VREFBUF_CSR_HIZ_Pos (1U)
  6938. #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
  6939. #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
  6940. #define VREFBUF_CSR_VRS_Pos (2U)
  6941. #define VREFBUF_CSR_VRS_Msk (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000004 */
  6942. #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
  6943. #define VREFBUF_CSR_VRR_Pos (3U)
  6944. #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
  6945. #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
  6946. /******************* Bit definition for VREFBUF_CCR register ******************/
  6947. #define VREFBUF_CCR_TRIM_Pos (0U)
  6948. #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
  6949. #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
  6950. /******************************************************************************/
  6951. /* */
  6952. /* Window WATCHDOG */
  6953. /* */
  6954. /******************************************************************************/
  6955. /******************* Bit definition for WWDG_CR register ********************/
  6956. #define WWDG_CR_T_Pos (0U)
  6957. #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
  6958. #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
  6959. #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
  6960. #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
  6961. #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
  6962. #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
  6963. #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
  6964. #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
  6965. #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
  6966. #define WWDG_CR_WDGA_Pos (7U)
  6967. #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
  6968. #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
  6969. /******************* Bit definition for WWDG_CFR register *******************/
  6970. #define WWDG_CFR_W_Pos (0U)
  6971. #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
  6972. #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
  6973. #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
  6974. #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
  6975. #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
  6976. #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
  6977. #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
  6978. #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
  6979. #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
  6980. #define WWDG_CFR_WDGTB_Pos (11U)
  6981. #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
  6982. #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
  6983. #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
  6984. #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
  6985. #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
  6986. #define WWDG_CFR_EWI_Pos (9U)
  6987. #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
  6988. #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
  6989. /******************* Bit definition for WWDG_SR register ********************/
  6990. #define WWDG_SR_EWIF_Pos (0U)
  6991. #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
  6992. #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
  6993. /******************************************************************************/
  6994. /* */
  6995. /* Debug MCU */
  6996. /* */
  6997. /******************************************************************************/
  6998. /******************** Bit definition for DBG_IDCODE register *************/
  6999. #define DBG_IDCODE_DEV_ID_Pos (0U)
  7000. #define DBG_IDCODE_DEV_ID_Msk (0xFFFUL << DBG_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
  7001. #define DBG_IDCODE_DEV_ID DBG_IDCODE_DEV_ID_Msk
  7002. #define DBG_IDCODE_REV_ID_Pos (16U)
  7003. #define DBG_IDCODE_REV_ID_Msk (0xFFFFUL << DBG_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
  7004. #define DBG_IDCODE_REV_ID DBG_IDCODE_REV_ID_Msk
  7005. /******************** Bit definition for DBG_CR register *****************/
  7006. #define DBG_CR_DBG_STOP_Pos (1U)
  7007. #define DBG_CR_DBG_STOP_Msk (0x1UL << DBG_CR_DBG_STOP_Pos) /*!< 0x00000002 */
  7008. #define DBG_CR_DBG_STOP DBG_CR_DBG_STOP_Msk
  7009. #define DBG_CR_DBG_STANDBY_Pos (2U)
  7010. #define DBG_CR_DBG_STANDBY_Msk (0x1UL << DBG_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
  7011. #define DBG_CR_DBG_STANDBY DBG_CR_DBG_STANDBY_Msk
  7012. /******************** Bit definition for DBG_APB_FZ1 register ***********/
  7013. #define DBG_APB_FZ1_DBG_TIM2_STOP_Pos (0U)
  7014. #define DBG_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
  7015. #define DBG_APB_FZ1_DBG_TIM2_STOP DBG_APB_FZ1_DBG_TIM2_STOP_Msk
  7016. #define DBG_APB_FZ1_DBG_TIM3_STOP_Pos (1U)
  7017. #define DBG_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
  7018. #define DBG_APB_FZ1_DBG_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP_Msk
  7019. #define DBG_APB_FZ1_DBG_RTC_STOP_Pos (10U)
  7020. #define DBG_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
  7021. #define DBG_APB_FZ1_DBG_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP_Msk
  7022. #define DBG_APB_FZ1_DBG_WWDG_STOP_Pos (11U)
  7023. #define DBG_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
  7024. #define DBG_APB_FZ1_DBG_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP_Msk
  7025. #define DBG_APB_FZ1_DBG_IWDG_STOP_Pos (12U)
  7026. #define DBG_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
  7027. #define DBG_APB_FZ1_DBG_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP_Msk
  7028. #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos (21U)
  7029. #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Pos) /*!< 0x00200000 */
  7030. #define DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP_Msk
  7031. #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos (30U)
  7032. #define DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_LPTIM2_STOP_Pos) /*!< 0x40000000 */
  7033. #define DBG_APB_FZ1_DBG_LPTIM2_STOP DBG_APB_FZ1_DBG_LPTIM2_STOP_Msk
  7034. #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos (31U)
  7035. #define DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk (0x1UL << DBG_APB_FZ1_DBG_LPTIM1_STOP_Pos) /*!< 0x80000000 */
  7036. #define DBG_APB_FZ1_DBG_LPTIM1_STOP DBG_APB_FZ1_DBG_LPTIM1_STOP_Msk
  7037. /******************** Bit definition for DBG_APB_FZ2 register ************/
  7038. #define DBG_APB_FZ2_DBG_TIM1_STOP_Pos (11U)
  7039. #define DBG_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
  7040. #define DBG_APB_FZ2_DBG_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP_Msk
  7041. #define DBG_APB_FZ2_DBG_TIM14_STOP_Pos (15U)
  7042. #define DBG_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */
  7043. #define DBG_APB_FZ2_DBG_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP_Msk
  7044. #define DBG_APB_FZ2_DBG_TIM16_STOP_Pos (17U)
  7045. #define DBG_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
  7046. #define DBG_APB_FZ2_DBG_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP_Msk
  7047. #define DBG_APB_FZ2_DBG_TIM17_STOP_Pos (18U)
  7048. #define DBG_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBG_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
  7049. #define DBG_APB_FZ2_DBG_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP_Msk
  7050. /** @addtogroup Exported_macros
  7051. * @{
  7052. */
  7053. /******************************* ADC Instances ********************************/
  7054. #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
  7055. #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
  7056. /******************************* CRC Instances ********************************/
  7057. #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
  7058. /******************************** DMA Instances *******************************/
  7059. #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
  7060. ((INSTANCE) == DMA1_Channel2) || \
  7061. ((INSTANCE) == DMA1_Channel3) || \
  7062. ((INSTANCE) == DMA1_Channel4) || \
  7063. ((INSTANCE) == DMA1_Channel5))
  7064. /******************************** DMAMUX Instances ****************************/
  7065. #define IS_DMAMUX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMAMUX1)
  7066. #define IS_DMAMUX_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
  7067. ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
  7068. ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
  7069. ((INSTANCE) == DMAMUX1_RequestGenerator3))
  7070. /******************************* GPIO Instances *******************************/
  7071. #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  7072. ((INSTANCE) == GPIOB) || \
  7073. ((INSTANCE) == GPIOC) || \
  7074. ((INSTANCE) == GPIOD) || \
  7075. ((INSTANCE) == GPIOF))
  7076. /******************************* GPIO AF Instances ****************************/
  7077. #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
  7078. /**************************** GPIO Lock Instances *****************************/
  7079. #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
  7080. ((INSTANCE) == GPIOB) || \
  7081. ((INSTANCE) == GPIOC))
  7082. /******************************** I2C Instances *******************************/
  7083. #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
  7084. ((INSTANCE) == I2C2))
  7085. /****************************** RTC Instances *********************************/
  7086. #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
  7087. /****************************** SMBUS Instances *******************************/
  7088. #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
  7089. /****************************** WAKEUP_FROMSTOP Instances *******************************/
  7090. #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1))
  7091. /******************************** SPI Instances *******************************/
  7092. #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
  7093. ((INSTANCE) == SPI2))
  7094. /******************************** SPI Instances *******************************/
  7095. #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
  7096. /****************** LPTIM Instances : All supported instances *****************/
  7097. #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
  7098. ((INSTANCE) == LPTIM2))
  7099. /****************** LPTIM Instances : All supported instances *****************/
  7100. #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
  7101. /****************** TIM Instances : All supported instances *******************/
  7102. #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7103. ((INSTANCE) == TIM2) || \
  7104. ((INSTANCE) == TIM3) || \
  7105. ((INSTANCE) == TIM14) || \
  7106. ((INSTANCE) == TIM16) || \
  7107. ((INSTANCE) == TIM17))
  7108. /****************** TIM Instances : supporting 32 bits counter ****************/
  7109. #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
  7110. /****************** TIM Instances : supporting the break function *************/
  7111. #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7112. ((INSTANCE) == TIM16) || \
  7113. ((INSTANCE) == TIM17))
  7114. /************** TIM Instances : supporting Break source selection *************/
  7115. #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7116. ((INSTANCE) == TIM16) || \
  7117. ((INSTANCE) == TIM17))
  7118. /****************** TIM Instances : supporting 2 break inputs *****************/
  7119. #define IS_TIM_BKIN2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7120. /************* TIM Instances : at least 1 capture/compare channel *************/
  7121. #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7122. ((INSTANCE) == TIM2) || \
  7123. ((INSTANCE) == TIM3) || \
  7124. ((INSTANCE) == TIM14) || \
  7125. ((INSTANCE) == TIM16) || \
  7126. ((INSTANCE) == TIM17))
  7127. /************ TIM Instances : at least 2 capture/compare channels *************/
  7128. #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7129. ((INSTANCE) == TIM2) || \
  7130. ((INSTANCE) == TIM3))
  7131. /************ TIM Instances : at least 3 capture/compare channels *************/
  7132. #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7133. ((INSTANCE) == TIM2) || \
  7134. ((INSTANCE) == TIM3))
  7135. /************ TIM Instances : at least 4 capture/compare channels *************/
  7136. #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7137. ((INSTANCE) == TIM2) || \
  7138. ((INSTANCE) == TIM3))
  7139. /****************** TIM Instances : at least 5 capture/compare channels *******/
  7140. #define IS_TIM_CC5_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7141. /****************** TIM Instances : at least 6 capture/compare channels *******/
  7142. #define IS_TIM_CC6_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7143. /************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
  7144. #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7145. ((INSTANCE) == TIM16) || \
  7146. ((INSTANCE) == TIM17))
  7147. /****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
  7148. #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7149. ((INSTANCE) == TIM2) || \
  7150. ((INSTANCE) == TIM3) || \
  7151. ((INSTANCE) == TIM16) || \
  7152. ((INSTANCE) == TIM17))
  7153. /************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
  7154. #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7155. ((INSTANCE) == TIM2) || \
  7156. ((INSTANCE) == TIM3) || \
  7157. ((INSTANCE) == TIM14) || \
  7158. ((INSTANCE) == TIM16) || \
  7159. ((INSTANCE) == TIM17))
  7160. /******************** TIM Instances : DMA burst feature ***********************/
  7161. #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7162. ((INSTANCE) == TIM2) || \
  7163. ((INSTANCE) == TIM3) || \
  7164. ((INSTANCE) == TIM16) || \
  7165. ((INSTANCE) == TIM17))
  7166. /******************* TIM Instances : output(s) available **********************/
  7167. #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
  7168. ((((INSTANCE) == TIM1) && \
  7169. (((CHANNEL) == TIM_CHANNEL_1) || \
  7170. ((CHANNEL) == TIM_CHANNEL_2) || \
  7171. ((CHANNEL) == TIM_CHANNEL_3) || \
  7172. ((CHANNEL) == TIM_CHANNEL_4) || \
  7173. ((CHANNEL) == TIM_CHANNEL_5) || \
  7174. ((CHANNEL) == TIM_CHANNEL_6))) \
  7175. || \
  7176. (((INSTANCE) == TIM2) && \
  7177. (((CHANNEL) == TIM_CHANNEL_1) || \
  7178. ((CHANNEL) == TIM_CHANNEL_2) || \
  7179. ((CHANNEL) == TIM_CHANNEL_3) || \
  7180. ((CHANNEL) == TIM_CHANNEL_4))) \
  7181. || \
  7182. (((INSTANCE) == TIM3) && \
  7183. (((CHANNEL) == TIM_CHANNEL_1) || \
  7184. ((CHANNEL) == TIM_CHANNEL_2) || \
  7185. ((CHANNEL) == TIM_CHANNEL_3) || \
  7186. ((CHANNEL) == TIM_CHANNEL_4))) \
  7187. || \
  7188. (((INSTANCE) == TIM14) && \
  7189. (((CHANNEL) == TIM_CHANNEL_1))) \
  7190. || \
  7191. (((INSTANCE) == TIM16) && \
  7192. (((CHANNEL) == TIM_CHANNEL_1))) \
  7193. || \
  7194. (((INSTANCE) == TIM17) && \
  7195. (((CHANNEL) == TIM_CHANNEL_1))))
  7196. /****************** TIM Instances : supporting complementary output(s) ********/
  7197. #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
  7198. ((((INSTANCE) == TIM1) && \
  7199. (((CHANNEL) == TIM_CHANNEL_1) || \
  7200. ((CHANNEL) == TIM_CHANNEL_2) || \
  7201. ((CHANNEL) == TIM_CHANNEL_3))) \
  7202. || \
  7203. (((INSTANCE) == TIM16) && \
  7204. ((CHANNEL) == TIM_CHANNEL_1)) \
  7205. || \
  7206. (((INSTANCE) == TIM17) && \
  7207. ((CHANNEL) == TIM_CHANNEL_1)))
  7208. /****************** TIM Instances : supporting clock division *****************/
  7209. #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7210. ((INSTANCE) == TIM2) || \
  7211. ((INSTANCE) == TIM3) || \
  7212. ((INSTANCE) == TIM14) || \
  7213. ((INSTANCE) == TIM16) || \
  7214. ((INSTANCE) == TIM17))
  7215. /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
  7216. #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7217. ((INSTANCE) == TIM2) || \
  7218. ((INSTANCE) == TIM3))
  7219. /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
  7220. #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7221. ((INSTANCE) == TIM2) || \
  7222. ((INSTANCE) == TIM3))
  7223. /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
  7224. #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7225. ((INSTANCE) == TIM2) || \
  7226. ((INSTANCE) == TIM3))
  7227. /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
  7228. #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7229. ((INSTANCE) == TIM2) || \
  7230. ((INSTANCE) == TIM3))
  7231. /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
  7232. #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
  7233. /****************** TIM Instances : supporting commutation event generation ***/
  7234. #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7235. ((INSTANCE) == TIM16) || \
  7236. ((INSTANCE) == TIM17))
  7237. /****************** TIM Instances : supporting counting mode selection ********/
  7238. #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7239. ((INSTANCE) == TIM2) || \
  7240. ((INSTANCE) == TIM3))
  7241. /****************** TIM Instances : supporting encoder interface **************/
  7242. #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7243. ((INSTANCE) == TIM2) || \
  7244. ((INSTANCE) == TIM3))
  7245. /****************** TIM Instances : supporting Hall sensor interface **********/
  7246. #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7247. ((INSTANCE) == TIM2) || \
  7248. ((INSTANCE) == TIM3))
  7249. /**************** TIM Instances : external trigger input available ************/
  7250. #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7251. ((INSTANCE) == TIM2) || \
  7252. ((INSTANCE) == TIM3))
  7253. /************* TIM Instances : supporting ETR source selection ***************/
  7254. #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7255. ((INSTANCE) == TIM2) || \
  7256. ((INSTANCE) == TIM3))
  7257. /****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
  7258. #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7259. ((INSTANCE) == TIM2) || \
  7260. ((INSTANCE) == TIM3))
  7261. /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
  7262. #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7263. ((INSTANCE) == TIM2) || \
  7264. ((INSTANCE) == TIM3))
  7265. /****************** TIM Instances : supporting OCxREF clear *******************/
  7266. #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7267. ((INSTANCE) == TIM2) || \
  7268. ((INSTANCE) == TIM3))
  7269. /****************** TIM Instances : remapping capability **********************/
  7270. #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7271. ((INSTANCE) == TIM2) || \
  7272. ((INSTANCE) == TIM3))
  7273. /****************** TIM Instances : supporting repetition counter *************/
  7274. #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7275. ((INSTANCE) == TIM16) || \
  7276. ((INSTANCE) == TIM17))
  7277. /****************** TIM Instances : supporting synchronization ****************/
  7278. #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
  7279. /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
  7280. #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  7281. /******************* TIM Instances : Timer input XOR function *****************/
  7282. #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7283. ((INSTANCE) == TIM2) || \
  7284. ((INSTANCE) == TIM3))
  7285. /******************* TIM Instances : Timer input selection ********************/
  7286. #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
  7287. ((INSTANCE) == TIM2) || \
  7288. ((INSTANCE) == TIM3) || \
  7289. ((INSTANCE) == TIM14) || \
  7290. ((INSTANCE) == TIM16) || \
  7291. ((INSTANCE) == TIM17))
  7292. /************ TIM Instances : Advanced timers ********************************/
  7293. #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
  7294. /******************** UART Instances : Asynchronous mode **********************/
  7295. #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7296. ((INSTANCE) == USART2))
  7297. /******************** USART Instances : Synchronous mode **********************/
  7298. #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7299. ((INSTANCE) == USART2))
  7300. /****************** UART Instances : Hardware Flow control ********************/
  7301. #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7302. ((INSTANCE) == USART2) || \
  7303. ((INSTANCE) == LPUART1))
  7304. /********************* USART Instances : Smard card mode ***********************/
  7305. #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  7306. /****************** UART Instances : Auto Baud Rate detection ****************/
  7307. #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  7308. /******************** UART Instances : Half-Duplex mode **********************/
  7309. #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7310. ((INSTANCE) == USART2) || \
  7311. ((INSTANCE) == LPUART1))
  7312. /******************** UART Instances : LIN mode **********************/
  7313. #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  7314. /******************** UART Instances : Wake-up from Stop mode **********************/
  7315. #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7316. ((INSTANCE) == LPUART1))
  7317. /****************** UART Instances : Driver Enable *****************/
  7318. #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7319. ((INSTANCE) == USART2) || \
  7320. ((INSTANCE) == LPUART1))
  7321. /****************** UART Instances : SPI Slave selection mode ***************/
  7322. #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7323. ((INSTANCE) == USART2))
  7324. /****************** UART Instances : Driver Enable *****************/
  7325. #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
  7326. ((INSTANCE) == LPUART1))
  7327. /*********************** UART Instances : IRDA mode ***************************/
  7328. #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
  7329. /******************** LPUART Instance *****************************************/
  7330. #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
  7331. /****************************** IWDG Instances ********************************/
  7332. #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
  7333. /****************************** WWDG Instances ********************************/
  7334. #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
  7335. /**
  7336. * @}
  7337. */
  7338. /**
  7339. * @}
  7340. */
  7341. /**
  7342. * @}
  7343. */
  7344. #ifdef __cplusplus
  7345. }
  7346. #endif /* __cplusplus */
  7347. #endif /* STM32G031xx_H */
  7348. /**
  7349. * @}
  7350. */
  7351. /**
  7352. * @}
  7353. */
  7354. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/