drv_gpio.c 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208
  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023/01/5 chushicheng first version
  9. *
  10. */
  11. #include "drv_gpio.h"
  12. #include <stdbool.h>
  13. #include "bl808_gpio.h"
  14. #include "bl808_glb.h"
  15. #include "bl808.h"
  16. #ifdef RT_USING_PIN
  17. #define DBG_TAG "drv.gpio"
  18. #define DBG_LVL DBG_INFO
  19. #include <rtdbg.h>
  20. static void GPIO0_IRQHandler(void);
  21. struct gpio_int_cfg_private
  22. {
  23. slist_t list;
  24. uint32_t pin;
  25. void (*hdr)(uint32_t pin);
  26. };
  27. static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head);
  28. static void bl808_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  29. {
  30. GLB_GPIO_Write(pin, value);
  31. }
  32. static int bl808_pin_read(rt_device_t dev, rt_base_t pin)
  33. {
  34. int value;
  35. value = GLB_GPIO_Read(pin);;
  36. return value;
  37. }
  38. static void bl808_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  39. {
  40. GLB_GPIO_Cfg_Type gpio_cfg;
  41. gpio_cfg.gpioFun = GPIO_FUN_GPIO;
  42. gpio_cfg.gpioPin = pin;
  43. gpio_cfg.drive = 0;
  44. gpio_cfg.smtCtrl = 1;
  45. gpio_cfg.outputMode = 0;
  46. switch (mode)
  47. {
  48. case GPIO_OUTPUT_MODE:
  49. gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
  50. gpio_cfg.pullType = GPIO_PULL_NONE;
  51. break;
  52. case GPIO_OUTPUT_PP_MODE:
  53. gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
  54. gpio_cfg.pullType = GPIO_PULL_UP;
  55. break;
  56. case GPIO_OUTPUT_PD_MODE:
  57. gpio_cfg.gpioMode = GPIO_MODE_OUTPUT;
  58. gpio_cfg.pullType = GPIO_PULL_DOWN;
  59. break;
  60. case GPIO_INPUT_MODE:
  61. gpio_cfg.gpioMode = GPIO_MODE_INPUT;
  62. gpio_cfg.pullType = GPIO_PULL_NONE;
  63. break;
  64. case GPIO_INPUT_PP_MODE:
  65. gpio_cfg.gpioMode = GPIO_MODE_INPUT;
  66. gpio_cfg.pullType = GPIO_PULL_UP;
  67. break;
  68. case GPIO_INPUT_PD_MODE:
  69. gpio_cfg.gpioMode = GPIO_MODE_INPUT;
  70. gpio_cfg.pullType = GPIO_PULL_DOWN;
  71. break;
  72. case GPIO_HZ_MODE:
  73. GLB_GPIO_Set_HZ(pin);
  74. default:
  75. CPU_Interrupt_Disable(GPIO_INT0_IRQn);
  76. GLB_GPIO_IntMask(pin, MASK);
  77. GLB_GPIO_INT_Cfg_Type intCfg;
  78. intCfg.gpioPin = pin;
  79. intCfg.intMask = MASK;
  80. gpio_cfg.gpioMode = GPIO_MODE_INPUT;
  81. if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE)
  82. {
  83. gpio_cfg.pullType = GPIO_PULL_DOWN;
  84. intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE;
  85. }
  86. else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE)
  87. {
  88. gpio_cfg.pullType = GPIO_PULL_UP;
  89. intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE;
  90. }
  91. else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE)
  92. {
  93. gpio_cfg.pullType = GPIO_PULL_DOWN;
  94. intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL;
  95. }
  96. else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE)
  97. {
  98. gpio_cfg.pullType = GPIO_PULL_UP;
  99. intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL;
  100. }
  101. else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE)
  102. {
  103. gpio_cfg.pullType = GPIO_PULL_DOWN;
  104. intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE;
  105. }
  106. else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE)
  107. {
  108. gpio_cfg.pullType = GPIO_PULL_UP;
  109. intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE;
  110. }
  111. else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE)
  112. {
  113. gpio_cfg.pullType = GPIO_PULL_NONE;
  114. intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE;
  115. }
  116. else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE)
  117. {
  118. gpio_cfg.pullType = GPIO_PULL_DOWN;
  119. intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL;
  120. }
  121. else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE)
  122. {
  123. gpio_cfg.pullType = GPIO_PULL_UP;
  124. intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL;
  125. }
  126. GLB_GPIO_Int_Init(&intCfg);
  127. break;
  128. }
  129. GLB_GPIO_Init(&gpio_cfg);
  130. }
  131. static rt_err_t bl808_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  132. rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
  133. {
  134. struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private));
  135. int_cfg->hdr = hdr;
  136. int_cfg->pin = pin;
  137. slist_add_tail(&gpio_int_head, &int_cfg->list);
  138. CPU_Interrupt_Disable(GPIO_INT0_IRQn);
  139. Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO0_IRQHandler);
  140. CPU_Interrupt_Enable(GPIO_INT0_IRQn);
  141. return RT_EOK;
  142. }
  143. static rt_err_t bl808_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  144. rt_uint32_t enabled)
  145. {
  146. if (enabled)
  147. {
  148. GLB_GPIO_IntMask(pin, UNMASK);
  149. }
  150. else
  151. {
  152. GLB_GPIO_IntMask(pin, MASK);
  153. }
  154. return RT_EOK;
  155. }
  156. const static struct rt_pin_ops _bl808_pin_ops =
  157. {
  158. bl808_pin_mode,
  159. bl808_pin_write,
  160. bl808_pin_read,
  161. bl808_pin_attach_irq,
  162. bl808_pin_irq_enable,
  163. NULL,
  164. };
  165. int rt_hw_pin_init(void)
  166. {
  167. return rt_device_pin_register("pin", &_bl808_pin_ops, RT_NULL);
  168. }
  169. INIT_BOARD_EXPORT(rt_hw_pin_init);
  170. /* irq handle */
  171. void GPIO0_IRQHandler(void)
  172. {
  173. rt_interrupt_enter();
  174. // GPIO_INT0_IRQHandler();
  175. rt_interrupt_leave();
  176. }
  177. #endif /* RT_USING_PIN */