drv_hwtimer.c 8.1 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-03-16 Leo first version
  9. */
  10. #include <board.h>
  11. #include "drv_hwtimer.h"
  12. #define DRV_DEBUG
  13. #define LOG_TAG "drv.hwtimer"
  14. #include <drv_log.h>
  15. #ifdef BSP_USING_HWTIMER
  16. enum
  17. {
  18. #ifdef BSP_USING_HWTMR1
  19. TMR1_INDEX,
  20. #endif
  21. #ifdef BSP_USING_HWTMR2
  22. TMR2_INDEX,
  23. #endif
  24. #ifdef BSP_USING_HWTMR3
  25. TMR3_INDEX,
  26. #endif
  27. #ifdef BSP_USING_HWTMR4
  28. TMR4_INDEX,
  29. #endif
  30. #ifdef BSP_USING_HWTMR5
  31. TMR5_INDEX,
  32. #endif
  33. #ifdef BSP_USING_HWTMR6
  34. TMR6_INDEX,
  35. #endif
  36. #ifdef BSP_USING_HWTMR7
  37. TMR7_INDEX,
  38. #endif
  39. #ifdef BSP_USING_HW_TMR8
  40. TMR8_INDEX,
  41. #endif
  42. #ifdef BSP_USING_HWTMR9
  43. TMR9_INDEX,
  44. #endif
  45. #ifdef BSP_USING_HWTMR10
  46. TMR10_INDEX,
  47. #endif
  48. #ifdef BSP_USING_HWTMR11
  49. TMR11_INDEX,
  50. #endif
  51. #ifdef BSP_USING_HWTMR12
  52. TMR12_INDEX,
  53. #endif
  54. #ifdef BSP_USING_HWTMR13
  55. TMR13_INDEX,
  56. #endif
  57. #ifdef BSP_USING_HWTMR14
  58. TMR14_INDEX,
  59. #endif
  60. #ifdef BSP_USING_HWTMR15
  61. TMR15_INDEX,
  62. #endif
  63. };
  64. struct at32_hwtimer
  65. {
  66. rt_hwtimer_t time_device;
  67. TMR_Type* tim_handle;
  68. IRQn_Type tim_irqn;
  69. char *name;
  70. };
  71. static struct at32_hwtimer at32_hwtimer_obj[] =
  72. {
  73. #ifdef BSP_USING_HWTMR1
  74. TMR1_CONFIG,
  75. #endif
  76. #ifdef BSP_USING_HWTMR2
  77. TMR2_CONFIG,
  78. #endif
  79. #ifdef BSP_USING_HWTMR3
  80. TMR3_CONFIG,
  81. #endif
  82. #ifdef BSP_USING_HWTMR4
  83. TMR4_CONFIG,
  84. #endif
  85. #ifdef BSP_USING_HWTMR5
  86. TMR5_CONFIG,
  87. #endif
  88. #ifdef BSP_USING_HWTMR6
  89. TMR6_CONFIG,
  90. #endif
  91. #ifdef BSP_USING_HWTMR7
  92. TMR7_CONFIG,
  93. #endif
  94. #ifdef BSP_USING_HWTMR8
  95. TMR8_CONFIG,
  96. #endif
  97. #ifdef BSP_USING_HWTMR9
  98. TMR9_CONFIG,
  99. #endif
  100. #ifdef BSP_USING_HWTMR10
  101. TMR10_CONFIG,
  102. #endif
  103. #ifdef BSP_USING_HWTMR11
  104. TMR11_CONFIG,
  105. #endif
  106. #ifdef BSP_USING_HWTMR12
  107. TMR12_CONFIG,
  108. #endif
  109. #ifdef BSP_USING_HWTMR13
  110. TMR13_CONFIG,
  111. #endif
  112. #ifdef BSP_USING_HWTMR14
  113. TMR14_CONFIG,
  114. #endif
  115. #ifdef BSP_USING_HWTMR15
  116. TMR15_CONFIG,
  117. #endif
  118. };
  119. static void at32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
  120. {
  121. RCC_ClockType RCC_ClockStruct;
  122. TMR_TimerBaseInitType TMR_TMReBaseStructure;
  123. NVIC_InitType NVIC_InitStructure;
  124. uint32_t prescaler_value = 0;
  125. TMR_Type *tim = RT_NULL;
  126. struct at32_hwtimer *tim_device = RT_NULL;
  127. RT_ASSERT(timer != RT_NULL);
  128. if (state)
  129. {
  130. tim = (TMR_Type *)timer->parent.user_data;
  131. tim_device = (struct at32_hwtimer *)timer;
  132. /* timer clock enable */
  133. at32_msp_hwtmr_init(tim);
  134. /* timer init */
  135. RCC_GetClocksFreq(&RCC_ClockStruct);
  136. /* Set timer clock is 1Mhz */
  137. prescaler_value = (uint32_t)(RCC_ClockStruct.SYSCLK_Freq / 10000) - 1;
  138. TMR_TMReBaseStructure.TMR_Period = 10000 - 1;
  139. TMR_TMReBaseStructure.TMR_DIV = prescaler_value;
  140. TMR_TMReBaseStructure.TMR_ClockDivision = TMR_CKD_DIV1;
  141. TMR_TMReBaseStructure.TMR_RepetitionCounter = 0;
  142. if (timer->info->cntmode == HWTIMER_CNTMODE_UP)
  143. {
  144. TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Up;
  145. }
  146. else
  147. {
  148. TMR_TMReBaseStructure.TMR_CounterMode = TMR_CounterDIR_Down;
  149. }
  150. TMR_TimeBaseInit(tim, &TMR_TMReBaseStructure);
  151. /* Enable the TMRx global Interrupt */
  152. NVIC_InitStructure.NVIC_IRQChannel = tim_device->tim_irqn;
  153. NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
  154. NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
  155. NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
  156. NVIC_Init(&NVIC_InitStructure);
  157. TMR_INTConfig(tim, TMR_INT_Overflow ,ENABLE);
  158. TMR_ClearITPendingBit(tim, TMR_INT_Overflow);
  159. LOG_D("%s init success", tim_device->name);
  160. }
  161. }
  162. static rt_err_t at32_timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
  163. {
  164. rt_err_t result = RT_EOK;
  165. TMR_Type *tim = RT_NULL;
  166. RT_ASSERT(timer != RT_NULL);
  167. tim = (TMR_Type *)timer->parent.user_data;
  168. /* set tim cnt */
  169. TMR_SetCounter(tim, 0);
  170. /* set tim arr */
  171. TMR_SetAutoreload(tim, t - 1);
  172. if (opmode == HWTIMER_MODE_ONESHOT)
  173. {
  174. /* set timer to single mode */
  175. TMR_SelectOnePulseMode(tim, TMR_OPMode_Once);
  176. }
  177. else
  178. {
  179. TMR_SelectOnePulseMode(tim, TMR_OPMode_Repetitive);
  180. }
  181. /* start timer */
  182. TMR_Cmd(tim, ENABLE);
  183. return result;
  184. }
  185. static void at32_timer_stop(rt_hwtimer_t *timer)
  186. {
  187. TMR_Type *tim = RT_NULL;
  188. RT_ASSERT(timer != RT_NULL);
  189. tim = (TMR_Type *)timer->parent.user_data;
  190. /* stop timer */
  191. TMR_Cmd(tim, ENABLE);
  192. /* set tim cnt */
  193. TMR_SetCounter(tim, 0);
  194. }
  195. static rt_uint32_t at32_timer_counter_get(rt_hwtimer_t *timer)
  196. {
  197. TMR_Type *tim = RT_NULL;
  198. RT_ASSERT(timer != RT_NULL);
  199. tim = (TMR_Type *)timer->parent.user_data;
  200. return tim->CNT;
  201. }
  202. static rt_err_t at32_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
  203. {
  204. RCC_ClockType RCC_ClockStruct;
  205. TMR_Type *tim = RT_NULL;
  206. rt_err_t result = RT_EOK;
  207. RT_ASSERT(timer != RT_NULL);
  208. RT_ASSERT(arg != RT_NULL);
  209. tim = (TMR_Type *)timer->parent.user_data;
  210. switch(cmd)
  211. {
  212. case HWTIMER_CTRL_FREQ_SET:
  213. {
  214. rt_uint32_t freq;
  215. rt_uint16_t val;
  216. /* set timer frequence */
  217. freq = *((rt_uint32_t *)arg);
  218. /* time init */
  219. RCC_GetClocksFreq(&RCC_ClockStruct);
  220. val = RCC_ClockStruct.SYSCLK_Freq / freq;
  221. TMR_DIVConfig(tim, val - 1, TMR_DIVReloadMode_Immediate);
  222. }
  223. break;
  224. default:
  225. {
  226. result = -RT_ENOSYS;
  227. }
  228. break;
  229. }
  230. return result;
  231. }
  232. static const struct rt_hwtimer_info _info = TMR_DEV_INFO_CONFIG;
  233. static const struct rt_hwtimer_ops _ops =
  234. {
  235. .init = at32_timer_init,
  236. .start = at32_timer_start,
  237. .stop = at32_timer_stop,
  238. .count_get = at32_timer_counter_get,
  239. .control = at32_timer_ctrl,
  240. };
  241. #ifdef BSP_USING_HWTMR2
  242. void TMR2_GLOBAL_IRQHandler(void)
  243. {
  244. /* enter interrupt */
  245. rt_interrupt_enter();
  246. if(TMR_GetINTStatus(TMR2, TMR_INT_Overflow) == SET)
  247. {
  248. rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR2_INDEX].time_device);
  249. TMR_ClearITPendingBit(TMR2, TMR_INT_Overflow);
  250. }
  251. /* leave interrupt */
  252. rt_interrupt_leave();
  253. }
  254. #endif
  255. #ifdef BSP_USING_HWTMR3
  256. void TMR3_GLOBAL_IRQHandler(void)
  257. {
  258. /* enter interrupt */
  259. rt_interrupt_enter();
  260. if(TMR_GetINTStatus(TMR3, TMR_INT_Overflow) == SET)
  261. {
  262. rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR3_INDEX].time_device);
  263. TMR_ClearITPendingBit(TMR3, TMR_INT_Overflow);
  264. }
  265. /* leave interrupt */
  266. rt_interrupt_leave();
  267. }
  268. #endif
  269. #ifdef BSP_USING_HWTMR4
  270. void TMR4_GLOBAL_IRQHandler(void)
  271. {
  272. /* enter interrupt */
  273. rt_interrupt_enter();
  274. if(TMR_GetINTStatus(TMR4, TMR_INT_Overflow) == SET)
  275. {
  276. rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR4_INDEX].time_device);
  277. TMR_ClearITPendingBit(TMR4, TMR_INT_Overflow);
  278. }
  279. /* leave interrupt */
  280. rt_interrupt_leave();
  281. }
  282. #endif
  283. #ifdef BSP_USING_HWTMR5
  284. void TMR5_GLOBAL_IRQHandler(void)
  285. {
  286. /* enter interrupt */
  287. rt_interrupt_enter();
  288. if(TMR_GetINTStatus(TMR5, TMR_INT_Overflow) == SET)
  289. {
  290. rt_device_hwtimer_isr(&at32_hwtimer_obj[TMR5_INDEX].time_device);
  291. TMR_ClearITPendingBit(TMR5, TMR_INT_Overflow);
  292. }
  293. /* leave interrupt */
  294. rt_interrupt_leave();
  295. }
  296. #endif
  297. static int rt_hw_hwtimer_init(void)
  298. {
  299. int i = 0;
  300. int result = RT_EOK;
  301. for (i = 0; i < sizeof(at32_hwtimer_obj) / sizeof(at32_hwtimer_obj[0]); i++)
  302. {
  303. at32_hwtimer_obj[i].time_device.info = &_info;
  304. at32_hwtimer_obj[i].time_device.ops = &_ops;
  305. if (rt_device_hwtimer_register(&at32_hwtimer_obj[i].time_device, at32_hwtimer_obj[i].name, at32_hwtimer_obj[i].tim_handle) == RT_EOK)
  306. {
  307. LOG_D("%s register success", at32_hwtimer_obj[i].name);
  308. }
  309. else
  310. {
  311. LOG_E("%s register failed", at32_hwtimer_obj[i].name);
  312. result = -RT_ERROR;
  313. }
  314. }
  315. return result;
  316. }
  317. INIT_BOARD_EXPORT(rt_hw_hwtimer_init);
  318. #endif /* BSP_USING_HWTIMER */