serial.c 8.2 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2006-08-23 Bernard first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include "LPC24xx.h"
  13. #include "board.h"
  14. /* serial hardware register */
  15. #define REG8(d) (*((volatile unsigned char *)(d)))
  16. #define REG32(d) (*((volatile unsigned long *)(d)))
  17. #define UART_RBR(base) REG8(base + 0x00)
  18. #define UART_THR(base) REG8(base + 0x00)
  19. #define UART_IER(base) REG32(base + 0x04)
  20. #define UART_IIR(base) REG32(base + 0x08)
  21. #define UART_FCR(base) REG8(base + 0x08)
  22. #define UART_LCR(base) REG8(base + 0x0C)
  23. #define UART_MCR(base) REG8(base + 0x10)
  24. #define UART_LSR(base) REG8(base + 0x14)
  25. #define UART_MSR(base) REG8(base + 0x18)
  26. #define UART_SCR(base) REG8(base + 0x1C)
  27. #define UART_DLL(base) REG8(base + 0x00)
  28. #define UART_DLM(base) REG8(base + 0x04)
  29. #define UART_ACR(base) REG32(base + 0x20)
  30. #define UART_FDR(base) REG32(base + 0x28)
  31. #define UART_TER(base) REG8(base + 0x30)
  32. /* LPC serial device */
  33. struct rt_lpcserial
  34. {
  35. /* inherit from device */
  36. struct rt_device parent;
  37. rt_uint32_t hw_base;
  38. rt_uint32_t irqno;
  39. rt_uint32_t baudrate;
  40. /* reception field */
  41. rt_uint16_t save_index, read_index;
  42. rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
  43. };
  44. #ifdef RT_USING_UART1
  45. struct rt_lpcserial serial1;
  46. #endif
  47. #ifdef RT_USING_UART2
  48. struct rt_lpcserial serial2;
  49. #endif
  50. void rt_hw_serial_init(void);
  51. #define U0PINS 0x00000005
  52. void rt_hw_uart_isr(int irqno, void *param)
  53. {
  54. RT_UNUSED rt_uint32_t iir;
  55. struct rt_lpcserial* lpc_serial = (struct rt_lpcserial*)param;
  56. RT_ASSERT(lpc_serial != RT_NULL)
  57. if (UART_LSR(lpc_serial->hw_base) & 0x01)
  58. {
  59. rt_base_t level;
  60. while (UART_LSR(lpc_serial->hw_base) & 0x01)
  61. {
  62. /* disable interrupt */
  63. level = rt_hw_interrupt_disable();
  64. /* read character */
  65. lpc_serial->rx_buffer[lpc_serial->save_index] =
  66. UART_RBR(lpc_serial->hw_base);
  67. lpc_serial->save_index ++;
  68. if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
  69. lpc_serial->save_index = 0;
  70. /* if the next position is read index, discard this 'read char' */
  71. if (lpc_serial->save_index == lpc_serial->read_index)
  72. {
  73. lpc_serial->read_index ++;
  74. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  75. lpc_serial->read_index = 0;
  76. }
  77. /* enable interrupt */
  78. rt_hw_interrupt_enable(level);
  79. }
  80. /* invoke callback */
  81. if(lpc_serial->parent.rx_indicate != RT_NULL)
  82. {
  83. lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
  84. }
  85. }
  86. /* clear interrupt source */
  87. iir = UART_IIR(lpc_serial->hw_base);
  88. /* acknowledge Interrupt */
  89. VICVectAddr = 0;
  90. }
  91. /**
  92. * @addtogroup LPC214x
  93. */
  94. /*@{*/
  95. static rt_err_t rt_serial_init (rt_device_t dev)
  96. {
  97. return RT_EOK;
  98. }
  99. static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
  100. {
  101. struct rt_lpcserial* lpc_serial;
  102. lpc_serial = (struct rt_lpcserial*) dev;
  103. RT_ASSERT(lpc_serial != RT_NULL);
  104. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  105. {
  106. /* init UART rx interrupt */
  107. UART_IER(lpc_serial->hw_base) = 0x01;
  108. /* install ISR */
  109. rt_hw_interrupt_install(lpc_serial->irqno,
  110. rt_hw_uart_isr, lpc_serial, RT_NULL);
  111. rt_hw_interrupt_umask(lpc_serial->irqno);
  112. }
  113. return RT_EOK;
  114. }
  115. static rt_err_t rt_serial_close(rt_device_t dev)
  116. {
  117. struct rt_lpcserial* lpc_serial;
  118. lpc_serial = (struct rt_lpcserial*) dev;
  119. RT_ASSERT(lpc_serial != RT_NULL);
  120. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  121. {
  122. /* disable UART rx interrupt */
  123. UART_IER(lpc_serial->hw_base) = 0x00;
  124. }
  125. return RT_EOK;
  126. }
  127. static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
  128. {
  129. return RT_EOK;
  130. }
  131. static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
  132. {
  133. rt_uint8_t* ptr;
  134. struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
  135. RT_ASSERT(lpc_serial != RT_NULL);
  136. /* point to buffer */
  137. ptr = (rt_uint8_t*) buffer;
  138. if (dev->flag & RT_DEVICE_FLAG_INT_RX)
  139. {
  140. while (size)
  141. {
  142. /* interrupt receive */
  143. rt_base_t level;
  144. /* disable interrupt */
  145. level = rt_hw_interrupt_disable();
  146. if (lpc_serial->read_index != lpc_serial->save_index)
  147. {
  148. *ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
  149. lpc_serial->read_index ++;
  150. if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
  151. lpc_serial->read_index = 0;
  152. }
  153. else
  154. {
  155. /* no data in rx buffer */
  156. /* enable interrupt */
  157. rt_hw_interrupt_enable(level);
  158. break;
  159. }
  160. /* enable interrupt */
  161. rt_hw_interrupt_enable(level);
  162. ptr ++; size --;
  163. }
  164. return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
  165. }
  166. else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
  167. {
  168. /* not support right now */
  169. RT_ASSERT(0);
  170. }
  171. /* polling mode */
  172. while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
  173. {
  174. /* Read Character */
  175. *ptr = UART_RBR(lpc_serial->hw_base);
  176. ptr ++;
  177. size --;
  178. }
  179. return (rt_size_t)ptr - (rt_size_t)buffer;
  180. }
  181. static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
  182. {
  183. struct rt_lpcserial* lpc_serial;
  184. char *ptr;
  185. lpc_serial = (struct rt_lpcserial*) dev;
  186. if (dev->flag & RT_DEVICE_FLAG_INT_TX)
  187. {
  188. /* not support */
  189. RT_ASSERT(0);
  190. }
  191. else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
  192. {
  193. /* not support */
  194. RT_ASSERT(0);
  195. }
  196. /* polling write */
  197. ptr = (char *)buffer;
  198. if (dev->flag & RT_DEVICE_FLAG_STREAM)
  199. {
  200. /* stream mode */
  201. while (size)
  202. {
  203. if (*ptr == '\n')
  204. {
  205. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  206. UART_THR(lpc_serial->hw_base) = '\r';
  207. }
  208. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  209. UART_THR(lpc_serial->hw_base) = *ptr;
  210. ptr ++;
  211. size --;
  212. }
  213. }
  214. else
  215. {
  216. while (size)
  217. {
  218. while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
  219. UART_THR(lpc_serial->hw_base) = *ptr;
  220. ptr ++;
  221. size --;
  222. }
  223. }
  224. return (rt_size_t) ptr - (rt_size_t) buffer;
  225. }
  226. void rt_hw_serial_init(void)
  227. {
  228. struct rt_lpcserial* lpc_serial;
  229. #ifdef RT_USING_UART1
  230. lpc_serial = &serial1;
  231. lpc_serial->parent.type = RT_Device_Class_Char;
  232. lpc_serial->hw_base = 0xE000C000;
  233. lpc_serial->baudrate = 115200;
  234. lpc_serial->irqno = UART0_INT;
  235. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  236. lpc_serial->read_index = lpc_serial->save_index = 0;
  237. /* Enable UART0 RxD and TxD pins */
  238. PINSEL0 |= 0x50;
  239. /* 8 bits, no Parity, 1 Stop bit */
  240. UART_LCR(lpc_serial->hw_base) = 0x83;
  241. /* Setup Baudrate */
  242. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  243. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  244. /* DLAB = 0 */
  245. UART_LCR(lpc_serial->hw_base) = 0x03;
  246. lpc_serial->parent.type = RT_Device_Class_Char;
  247. lpc_serial->parent.init = rt_serial_init;
  248. lpc_serial->parent.open = rt_serial_open;
  249. lpc_serial->parent.close = rt_serial_close;
  250. lpc_serial->parent.read = rt_serial_read;
  251. lpc_serial->parent.write = rt_serial_write;
  252. lpc_serial->parent.control = rt_serial_control;
  253. lpc_serial->parent.user_data = RT_NULL;
  254. rt_device_register(&lpc_serial->parent,
  255. "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
  256. #endif
  257. #ifdef RT_USING_UART2
  258. lpc_serial = &serial2;
  259. lpc_serial->parent.type = RT_Device_Class_Char;
  260. lpc_serial->hw_base = 0xE0010000;
  261. lpc_serial->baudrate = 115200;
  262. lpc_serial->irqno = UART1_INT;
  263. rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
  264. lpc_serial->read_index = lpc_serial->save_index = 0;
  265. /* Enable UART1 RxD and TxD pins */
  266. PINSEL0 |= 0x05 << 16;
  267. /* 8 bits, no Parity, 1 Stop bit */
  268. UART_LCR(lpc_serial->hw_base) = 0x83;
  269. /* Setup Baudrate */
  270. UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
  271. UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
  272. /* DLAB = 0 */
  273. UART_LCR(lpc_serial->hw_base) = 0x03;
  274. lpc_serial->parent.type = RT_Device_Class_Char;
  275. lpc_serial->parent.init = rt_serial_init;
  276. lpc_serial->parent.open = rt_serial_open;
  277. lpc_serial->parent.close = rt_serial_close;
  278. lpc_serial->parent.read = rt_serial_read;
  279. lpc_serial->parent.write = rt_serial_write;
  280. lpc_serial->parent.control = rt_serial_control;
  281. lpc_serial->parent.user_data = RT_NULL;
  282. rt_device_register(&lpc_serial->parent,
  283. "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
  284. #endif
  285. }
  286. /*@}*/