drv_pulse_encoder.c 16 KB

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  1. /*
  2. * Copyright (C) 2020, Huada Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-10-30 CDT first version
  9. */
  10. #include <rtdevice.h>
  11. #include <rtdbg.h>
  12. #ifdef RT_USING_PULSE_ENCODER
  13. #if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) && \
  14. !defined(BSP_USING_PULSE_ENCODER4) && !defined(BSP_USING_PULSE_ENCODER5) && !defined(BSP_USING_PULSE_ENCODER6) && \
  15. !defined(BSP_USING_PULSE_ENCODER7) && !defined(BSP_USING_PULSE_ENCODER8) && !defined(BSP_USING_PULSE_ENCODER9) && \
  16. !defined(BSP_USING_PULSE_ENCODER10) && !defined(BSP_USING_PULSE_ENCODER11) && !defined(BSP_USING_PULSE_ENCODER12)
  17. #error "Please define at least one BSP_USING_PULSE_ENCODERx"
  18. /* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable Pulse Encoder */
  19. #endif
  20. #include "drv_pulse_encoder.h"
  21. #include "drv_irq.h"
  22. #define TIMER_AUTO_RELOAD_VALUE (0xFFFFU)
  23. enum
  24. {
  25. #ifdef BSP_USING_PULSE_ENCODER1
  26. PULSE_ENCODER1_INDEX,
  27. #endif
  28. #ifdef BSP_USING_PULSE_ENCODER2
  29. PULSE_ENCODER2_INDEX,
  30. #endif
  31. #ifdef BSP_USING_PULSE_ENCODER3
  32. PULSE_ENCODER3_INDEX,
  33. #endif
  34. #ifdef BSP_USING_PULSE_ENCODER4
  35. PULSE_ENCODER4_INDEX,
  36. #endif
  37. #ifdef BSP_USING_PULSE_ENCODER5
  38. PULSE_ENCODER5_INDEX,
  39. #endif
  40. #ifdef BSP_USING_PULSE_ENCODER6
  41. PULSE_ENCODER6_INDEX,
  42. #endif
  43. #ifdef BSP_USING_PULSE_ENCODER7
  44. PULSE_ENCODER7_INDEX,
  45. #endif
  46. #ifdef BSP_USING_PULSE_ENCODER8
  47. PULSE_ENCODER8_INDEX,
  48. #endif
  49. #ifdef BSP_USING_PULSE_ENCODER9
  50. PULSE_ENCODER9_INDEX,
  51. #endif
  52. #ifdef BSP_USING_PULSE_ENCODER10
  53. PULSE_ENCODER10_INDEX,
  54. #endif
  55. #ifdef BSP_USING_PULSE_ENCODER11
  56. PULSE_ENCODER11_INDEX,
  57. #endif
  58. #ifdef BSP_USING_PULSE_ENCODER12
  59. PULSE_ENCODER12_INDEX,
  60. #endif
  61. };
  62. #ifdef BSP_USING_PULSE_ENCODER1
  63. static void pulse_encoder1_irq_handler(void);
  64. #endif
  65. #ifdef BSP_USING_PULSE_ENCODER2
  66. static void pulse_encoder2_irq_handler(void);
  67. #endif
  68. #ifdef BSP_USING_PULSE_ENCODER3
  69. static void pulse_encoder3_irq_handler(void);
  70. #endif
  71. #ifdef BSP_USING_PULSE_ENCODER4
  72. static void pulse_encoder4_irq_handler(void);
  73. #endif
  74. #ifdef BSP_USING_PULSE_ENCODER5
  75. static void pulse_encoder5_irq_handler(void);
  76. #endif
  77. #ifdef BSP_USING_PULSE_ENCODER6
  78. static void pulse_encoder6_irq_handler(void);
  79. #endif
  80. #ifdef BSP_USING_PULSE_ENCODER7
  81. static void pulse_encoder7_irq_handler(void);
  82. #endif
  83. #ifdef BSP_USING_PULSE_ENCODER8
  84. static void pulse_encoder8_irq_handler(void);
  85. #endif
  86. #ifdef BSP_USING_PULSE_ENCODER9
  87. static void pulse_encoder9_irq_handler(void);
  88. #endif
  89. #ifdef BSP_USING_PULSE_ENCODER10
  90. static void pulse_encoder10_irq_handler(void);
  91. #endif
  92. #ifdef BSP_USING_PULSE_ENCODER11
  93. static void pulse_encoder11_irq_handler(void);
  94. #endif
  95. #ifdef BSP_USING_PULSE_ENCODER12
  96. static void pulse_encoder12_irq_handler(void);
  97. #endif
  98. struct hc32_pulse_encoder_config
  99. {
  100. struct rt_pulse_encoder_device pulse_encoder;
  101. M4_TMRA_TypeDef *timer_periph;
  102. struct hc32_irq_config ovf_irq_config;
  103. struct hc32_irq_config udf_irq_config;
  104. func_ptr_t irq_callback;
  105. rt_int32_t ovf_udf_count;
  106. char *name;
  107. };
  108. #ifndef HC32_PULSE_ENCODER_CONFIG
  109. #define HC32_PULSE_ENCODER_CONFIG(periph, irq, label, ovf_src, udf_src, \
  110. ovf_irq_info, udf_irq_info) \
  111. { \
  112. .timer_periph = periph, \
  113. .irq_callback = irq, \
  114. .name = label, \
  115. .ovf_irq_config = ovf_irq_info, \
  116. .udf_irq_config = udf_irq_info, \
  117. .ovf_irq_config.int_src = ovf_src, \
  118. .udf_irq_config.int_src = udf_src, \
  119. }
  120. #endif /* HC32_PULSE_ENCODER_CONFIG */
  121. static struct hc32_pulse_encoder_config pulse_encoder_obj[] =
  122. {
  123. #ifdef BSP_USING_PULSE_ENCODER1
  124. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_1, pulse_encoder1_irq_handler, "pulse1", INT_TMRA_1_OVF, INT_TMRA_1_UDF,
  125. PULSE_ENCODER1_OVF_IRQ_CONFIG, PULSE_ENCODER1_UDF_IRQ_CONFIG),
  126. #endif
  127. #ifdef BSP_USING_PULSE_ENCODER2
  128. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_2, pulse_encoder2_irq_handler, "pulse2", INT_TMRA_2_OVF, INT_TMRA_2_UDF,
  129. PULSE_ENCODER2_OVF_IRQ_CONFIG, PULSE_ENCODER2_UDF_IRQ_CONFIG),
  130. #endif
  131. #ifdef BSP_USING_PULSE_ENCODER3
  132. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_3, pulse_encoder3_irq_handler, "pulse3", INT_TMRA_3_OVF, INT_TMRA_3_UDF,
  133. PULSE_ENCODER3_OVF_IRQ_CONFIG, PULSE_ENCODER3_UDF_IRQ_CONFIG),
  134. #endif
  135. #ifdef BSP_USING_PULSE_ENCODER4
  136. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_4, pulse_encoder4_irq_handler, "pulse4", INT_TMRA_4_OVF, INT_TMRA_4_UDF,
  137. PULSE_ENCODER4_OVF_IRQ_CONFIG, PULSE_ENCODER4_UDF_IRQ_CONFIG),
  138. #endif
  139. #ifdef BSP_USING_PULSE_ENCODER5
  140. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_5, pulse_encoder5_irq_handler, "pulse5", INT_TMRA_5_OVF, INT_TMRA_5_UDF,
  141. PULSE_ENCODER5_OVF_IRQ_CONFIG, PULSE_ENCODER5_UDF_IRQ_CONFIG),
  142. #endif
  143. #ifdef BSP_USING_PULSE_ENCODER6
  144. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_6, pulse_encoder6_irq_handler, "pulse6", INT_TMRA_6_OVF, INT_TMRA_6_UDF,
  145. PULSE_ENCODER6_OVF_IRQ_CONFIG, PULSE_ENCODER6_UDF_IRQ_CONFIG),
  146. #endif
  147. #ifdef BSP_USING_PULSE_ENCODER7
  148. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_7, pulse_encoder7_irq_handler, "pulse7", INT_TMRA_7_OVF, INT_TMRA_7_UDF,
  149. PULSE_ENCODER7_OVF_IRQ_CONFIG, PULSE_ENCODER7_UDF_IRQ_CONFIG),
  150. #endif
  151. #ifdef BSP_USING_PULSE_ENCODER8
  152. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_8, pulse_encoder8_irq_handler, "pulse8", INT_TMRA_8_OVF, INT_TMRA_8_UDF,
  153. PULSE_ENCODER8_OVF_IRQ_CONFIG, PULSE_ENCODER8_UDF_IRQ_CONFIG),
  154. #endif
  155. #ifdef BSP_USING_PULSE_ENCODER9
  156. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_9, pulse_encoder9_irq_handler, "pulse9", INT_TMRA_9_OVF, INT_TMRA_9_UDF,
  157. PULSE_ENCODER9_OVF_IRQ_CONFIG, PULSE_ENCODER9_UDF_IRQ_CONFIG),
  158. #endif
  159. #ifdef BSP_USING_PULSE_ENCODER10
  160. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_10, pulse_encoder10_irq_handler, "pulse10", INT_TMRA_10_OVF, INT_TMRA_10_UDF,
  161. PULSE_ENCODER10_OVF_IRQ_CONFIG, PULSE_ENCODER10_UDF_IRQ_CONFIG),
  162. #endif
  163. #ifdef BSP_USING_PULSE_ENCODER11
  164. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_11, pulse_encoder11_irq_handler, "pulse11", INT_TMRA_11_OVF, INT_TMRA_11_UDF,
  165. PULSE_ENCODER11_OVF_IRQ_CONFIG, PULSE_ENCODER11_UDF_IRQ_CONFIG),
  166. #endif
  167. #ifdef BSP_USING_PULSE_ENCODER12
  168. HC32_PULSE_ENCODER_CONFIG(M4_TMRA_12, pulse_encoder12_irq_handler, "pulse12", INT_TMRA_12_OVF, INT_TMRA_12_UDF,
  169. PULSE_ENCODER12_OVF_IRQ_CONFIG, PULSE_ENCODER12_UDF_IRQ_CONFIG),
  170. #endif
  171. };
  172. static void hc32_pulse_encoder_irq_handler(struct hc32_pulse_encoder_config *pulse_encoder_config)
  173. {
  174. if (Set == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF))
  175. {
  176. pulse_encoder_config->ovf_udf_count++;
  177. TMRA_ClrStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF);
  178. }
  179. if (Set == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UNF))
  180. {
  181. pulse_encoder_config->ovf_udf_count--;
  182. TMRA_ClrStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UNF);
  183. }
  184. }
  185. #ifdef BSP_USING_PULSE_ENCODER1
  186. static void pulse_encoder1_irq_handler(void)
  187. {
  188. /* enter interrupt */
  189. rt_interrupt_enter();
  190. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER1_INDEX]);
  191. /* leave interrupt */
  192. rt_interrupt_leave();
  193. }
  194. #endif
  195. #ifdef BSP_USING_PULSE_ENCODER2
  196. static void pulse_encoder2_irq_handler(void)
  197. {
  198. /* enter interrupt */
  199. rt_interrupt_enter();
  200. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER2_INDEX]);
  201. /* leave interrupt */
  202. rt_interrupt_leave();
  203. }
  204. #endif
  205. #ifdef BSP_USING_PULSE_ENCODER3
  206. static void pulse_encoder3_irq_handler(void)
  207. {
  208. /* enter interrupt */
  209. rt_interrupt_enter();
  210. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER3_INDEX]);
  211. /* leave interrupt */
  212. rt_interrupt_leave();
  213. }
  214. #endif
  215. #ifdef BSP_USING_PULSE_ENCODER4
  216. static void pulse_encoder4_irq_handler(void)
  217. {
  218. /* enter interrupt */
  219. rt_interrupt_enter();
  220. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER4_INDEX]);
  221. /* leave interrupt */
  222. rt_interrupt_leave();
  223. }
  224. #endif
  225. #ifdef BSP_USING_PULSE_ENCODER5
  226. static void pulse_encoder5_irq_handler(void)
  227. {
  228. /* enter interrupt */
  229. rt_interrupt_enter();
  230. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER5_INDEX]);
  231. /* leave interrupt */
  232. rt_interrupt_leave();
  233. }
  234. #endif
  235. #ifdef BSP_USING_PULSE_ENCODER6
  236. static void pulse_encoder6_irq_handler(void)
  237. {
  238. /* enter interrupt */
  239. rt_interrupt_enter();
  240. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER6_INDEX]);
  241. /* leave interrupt */
  242. rt_interrupt_leave();
  243. }
  244. #endif
  245. #ifdef BSP_USING_PULSE_ENCODER7
  246. static void pulse_encoder7_irq_handler(void)
  247. {
  248. /* enter interrupt */
  249. rt_interrupt_enter();
  250. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER7_INDEX]);
  251. /* leave interrupt */
  252. rt_interrupt_leave();
  253. }
  254. #endif
  255. #ifdef BSP_USING_PULSE_ENCODER8
  256. static void pulse_encoder8_irq_handler(void)
  257. {
  258. /* enter interrupt */
  259. rt_interrupt_enter();
  260. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER8_INDEX]);
  261. /* leave interrupt */
  262. rt_interrupt_leave();
  263. }
  264. #endif
  265. #ifdef BSP_USING_PULSE_ENCODER9
  266. static void pulse_encoder9_irq_handler(void)
  267. {
  268. /* enter interrupt */
  269. rt_interrupt_enter();
  270. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER9_INDEX]);
  271. /* leave interrupt */
  272. rt_interrupt_leave();
  273. }
  274. #endif
  275. #ifdef BSP_USING_PULSE_ENCODER10
  276. static void pulse_encoder10_irq_handler(void)
  277. {
  278. /* enter interrupt */
  279. rt_interrupt_enter();
  280. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER10_INDEX]);
  281. /* leave interrupt */
  282. rt_interrupt_leave();
  283. }
  284. #endif
  285. #ifdef BSP_USING_PULSE_ENCODER11
  286. static void pulse_encoder11_irq_handler(void)
  287. {
  288. /* enter interrupt */
  289. rt_interrupt_enter();
  290. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER11_INDEX]);
  291. /* leave interrupt */
  292. rt_interrupt_leave();
  293. }
  294. #endif
  295. #ifdef BSP_USING_PULSE_ENCODER12
  296. static void pulse_encoder12_irq_handler(void)
  297. {
  298. /* enter interrupt */
  299. rt_interrupt_enter();
  300. hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER12_INDEX]);
  301. /* leave interrupt */
  302. rt_interrupt_leave();
  303. }
  304. #endif
  305. static rt_uint16_t hc32_timer_get_unit_number(M4_TMRA_TypeDef *TMRAx)
  306. {
  307. rt_uint16_t unit_num;
  308. const rt_uint32_t unit_step = 0x400U;
  309. if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)M4_TMRA_1))
  310. {
  311. unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_1)) / unit_step;
  312. }
  313. else
  314. {
  315. unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_5)) / unit_step + 4;
  316. }
  317. return unit_num;
  318. }
  319. static void hc32_timer_clock_config(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState)
  320. {
  321. rt_uint32_t timer_periph;
  322. rt_uint16_t unit_num;
  323. unit_num = hc32_timer_get_unit_number(TMRAx);
  324. timer_periph = PWC_FCG2_TMRA_1 << unit_num;
  325. PWC_Fcg2PeriphClockCmd(timer_periph, enNewState);
  326. }
  327. extern rt_err_t rt_hw_board_pulse_encoder_init(M4_TMRA_TypeDef *TMRAx);
  328. rt_err_t hc32_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder)
  329. {
  330. struct hc32_pulse_encoder_config *pulse_encoder_device;
  331. stc_tmra_init_t stcTmraInit;
  332. rt_err_t result;
  333. RT_ASSERT(pulse_encoder != RT_NULL);
  334. pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder;
  335. /* Enable Timer peripheral clock. */
  336. hc32_timer_clock_config(pulse_encoder_device->timer_periph, Enable);
  337. /* pwm pin configuration */
  338. result = rt_hw_board_pulse_encoder_init(pulse_encoder_device->timer_periph);
  339. if (RT_EOK == result)
  340. {
  341. TMRA_DeInit(pulse_encoder_device->timer_periph);
  342. TMRA_StructInit(&stcTmraInit);
  343. stcTmraInit.u32PeriodVal = TIMER_AUTO_RELOAD_VALUE;
  344. stcTmraInit.u32ClkSrc = TMRA_CLK_HW_UP_CLKBH_CLKAR | TMRA_CLK_HW_DOWN_CLKBL_CLKAR;
  345. TMRA_Init(pulse_encoder_device->timer_periph, &stcTmraInit);
  346. LOG_D("%s init success", pulse_encoder_device->name);
  347. hc32_install_irq_handler(&pulse_encoder_device->ovf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE);
  348. NVIC_EnableIRQ(pulse_encoder_device->ovf_irq_config.irq);
  349. hc32_install_irq_handler(&pulse_encoder_device->udf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE);
  350. NVIC_EnableIRQ(pulse_encoder_device->udf_irq_config.irq);
  351. /* clear update flag */
  352. TMRA_ClrStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UNF));
  353. }
  354. return result;
  355. }
  356. rt_err_t hc32_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder)
  357. {
  358. struct hc32_pulse_encoder_config *pulse_encoder_device;
  359. pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder;
  360. pulse_encoder_device->ovf_udf_count = 0;
  361. TMRA_Stop(pulse_encoder_device->timer_periph);
  362. TMRA_SetCntVal(pulse_encoder_device->timer_periph, 0);
  363. TMRA_ClrStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UNF));
  364. TMRA_Start(pulse_encoder_device->timer_periph);
  365. return RT_EOK;
  366. }
  367. rt_int32_t hc32_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder)
  368. {
  369. struct hc32_pulse_encoder_config *pulse_encoder_device;
  370. rt_int32_t period_val;
  371. rt_int32_t count_val;
  372. pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder;
  373. period_val = TMRA_GetCntVal(pulse_encoder_device->timer_periph);
  374. count_val = period_val + pulse_encoder_device->ovf_udf_count * TIMER_AUTO_RELOAD_VALUE;
  375. return count_val;
  376. }
  377. rt_err_t hc32_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args)
  378. {
  379. rt_err_t result = RT_EOK;
  380. struct hc32_pulse_encoder_config *pulse_encoder_device;
  381. pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder;
  382. switch (cmd)
  383. {
  384. case PULSE_ENCODER_CMD_ENABLE:
  385. TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UNF), Enable);
  386. TMRA_Start(pulse_encoder_device->timer_periph);
  387. break;
  388. case PULSE_ENCODER_CMD_DISABLE:
  389. TMRA_Stop(pulse_encoder_device->timer_periph);
  390. TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UNF), Disable);
  391. break;
  392. default:
  393. result = -RT_ENOSYS;
  394. break;
  395. }
  396. return result;
  397. }
  398. static const struct rt_pulse_encoder_ops pulse_encoder_ops =
  399. {
  400. .init = hc32_pulse_encoder_init,
  401. .get_count = hc32_pulse_encoder_get_count,
  402. .clear_count = hc32_pulse_encoder_clear_count,
  403. .control = hc32_pulse_encoder_control,
  404. };
  405. int hw_pulse_encoder_init(void)
  406. {
  407. int i;
  408. int result;
  409. result = RT_EOK;
  410. for (i = 0; i < sizeof(pulse_encoder_obj) / sizeof(pulse_encoder_obj[0]); i++)
  411. {
  412. pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER;
  413. pulse_encoder_obj[i].pulse_encoder.ops = &pulse_encoder_ops;
  414. if (rt_device_pulse_encoder_register(&pulse_encoder_obj[i].pulse_encoder, pulse_encoder_obj[i].name, pulse_encoder_obj[i].timer_periph) != RT_EOK)
  415. {
  416. LOG_E("%s register failed", pulse_encoder_obj[i].name);
  417. result = -RT_ERROR;
  418. }
  419. }
  420. return result;
  421. }
  422. INIT_BOARD_EXPORT(hw_pulse_encoder_init);
  423. #endif