drv_spi.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377
  1. /*
  2. * Copyright (C) 2020, Huada Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-10-30 CDT first version
  9. */
  10. #ifndef __DRV_SPI_H__
  11. #define __DRV_SPI_H__
  12. /*******************************************************************************
  13. * Include files
  14. ******************************************************************************/
  15. #include <rtthread.h>
  16. #include "rtdevice.h"
  17. #include "drv_dma.h"
  18. #include "board_config.h"
  19. #ifdef __cplusplus
  20. extern "C" {
  21. #endif
  22. #ifdef BSP_USING_SPI1
  23. #define SPI1_BUS_NAME "spi1"
  24. #define SPI1_BUS_MUTEX_NAME "spi1_bus_mutex"
  25. #endif
  26. #ifdef BSP_USING_SPI2
  27. #define SPI2_BUS_NAME "spi2"
  28. #define SPI2_BUS_MUTEX_NAME "spi2_bus_mutex"
  29. #endif
  30. #ifdef BSP_USING_SPI3
  31. #define SPI3_BUS_NAME "spi3"
  32. #define SPI3_BUS_MUTEX_NAME "spi3_bus_mutex"
  33. #endif
  34. #ifdef BSP_USING_SPI4
  35. #define SPI4_BUS_NAME "spi4"
  36. #define SPI4_BUS_MUTEX_NAME "spi4_bus_mutex"
  37. #endif
  38. #ifdef BSP_USING_SPI5
  39. #define SPI4_BUS_NAME "spi5"
  40. #define SPI4_BUS_MUTEX_NAME "spi5_bus_mutex"
  41. #endif
  42. #ifdef BSP_USING_SPI6
  43. #define SPI4_BUS_NAME "spi6"
  44. #define SPI4_BUS_MUTEX_NAME "spi6_bus_mutex"
  45. #endif
  46. #ifdef BSP_USING_SPI1
  47. #ifndef SPI1_BUS_CONFIG
  48. #define SPI1_BUS_CONFIG \
  49. { \
  50. .Instance = M4_SPI1, \
  51. .bus_name = SPI1_BUS_NAME, \
  52. }
  53. #endif /* SPI1_BUS_CONFIG */
  54. #endif /* BSP_USING_SPI1 */
  55. #ifdef BSP_SPI1_TX_USING_DMA
  56. #ifndef SPI1_TX_DMA_CONFIG
  57. #define SPI1_TX_DMA_CONFIG \
  58. { \
  59. .Instance = SPI1_TX_DMA_INSTANCE, \
  60. .channel = SPI1_TX_DMA_CHANNEL, \
  61. .trigger_evt_src = EVT_SPI1_SPTI, \
  62. .irq_config = \
  63. { \
  64. .irq = SPI1_TX_DMA_IRQn, \
  65. .irq_prio = SPI1_TX_DMA_INT_PRIO, \
  66. .int_src = SPI1_TX_DMA_INT_SRC, \
  67. } \
  68. }
  69. #endif /* SPI1_TX_DMA_CONFIG */
  70. #endif /* BSP_SPI1_TX_USING_DMA */
  71. #ifdef BSP_SPI1_RX_USING_DMA
  72. #ifndef SPI1_RX_DMA_CONFIG
  73. #define SPI1_RX_DMA_CONFIG \
  74. { \
  75. .Instance = SPI1_RX_DMA_INSTANCE, \
  76. .channel = SPI1_RX_DMA_CHANNEL, \
  77. .trigger_evt_src = EVT_SPI1_SPRI, \
  78. .irq_config = \
  79. { \
  80. .irq = SPI1_RX_DMA_IRQn, \
  81. .irq_prio = SPI1_RX_DMA_INT_PRIO, \
  82. .int_src = SPI1_RX_DMA_INT_SRC, \
  83. } \
  84. }
  85. #endif /* SPI1_RX_DMA_CONFIG */
  86. #endif /* BSP_SPI1_RX_USING_DMA */
  87. #ifdef BSP_USING_SPI2
  88. #ifndef SPI2_BUS_CONFIG
  89. #define SPI2_BUS_CONFIG \
  90. { \
  91. .Instance = M4_SPI2, \
  92. .bus_name = SPI2_BUS_NAME, \
  93. }
  94. #endif /* SPI2_BUS_CONFIG */
  95. #endif /* BSP_USING_SPI2 */
  96. #ifdef BSP_SPI2_TX_USING_DMA
  97. #ifndef SPI2_TX_DMA_CONFIG
  98. #define SPI2_TX_DMA_CONFIG \
  99. { \
  100. .Instance = SPI2_TX_DMA_INSTANCE, \
  101. .channel = SPI2_TX_DMA_CHANNEL, \
  102. .trigger_evt_src = EVT_SPI2_SPTI, \
  103. .irq_config = \
  104. { \
  105. .irq = SPI2_TX_DMA_IRQn, \
  106. .irq_prio = SPI2_TX_DMA_INT_PRIO, \
  107. .int_src = SPI2_TX_DMA_INT_SRC, \
  108. } \
  109. }
  110. #endif /* SPI2_TX_DMA_CONFIG */
  111. #endif /* BSP_SPI2_TX_USING_DMA */
  112. #ifdef BSP_SPI2_RX_USING_DMA
  113. #ifndef SPI2_RX_DMA_CONFIG
  114. #define SPI2_RX_DMA_CONFIG \
  115. { \
  116. .Instance = SPI2_RX_DMA_INSTANCE, \
  117. .channel = SPI2_RX_DMA_CHANNEL, \
  118. .trigger_evt_src = EVT_SPI2_SPRI, \
  119. .irq_config = \
  120. { \
  121. .irq = SPI2_RX_DMA_IRQn, \
  122. .irq_prio = SPI2_RX_DMA_INT_PRIO, \
  123. .int_src = SPI2_RX_DMA_INT_SRC, \
  124. } \
  125. }
  126. #endif /* SPI2_RX_DMA_CONFIG */
  127. #endif /* BSP_SPI2_RX_USING_DMA */
  128. #ifdef BSP_USING_SPI3
  129. #ifndef SPI3_BUS_CONFIG
  130. #define SPI3_BUS_CONFIG \
  131. { \
  132. .Instance = M4_SPI3, \
  133. .bus_name = SPI3_BUS_NAME, \
  134. }
  135. #endif /* SPI3_BUS_CONFIG */
  136. #endif /* BSP_USING_SPI3 */
  137. #ifdef BSP_SPI3_TX_USING_DMA
  138. #ifndef SPI3_TX_DMA_CONFIG
  139. #define SPI3_TX_DMA_CONFIG \
  140. { \
  141. .Instance = SPI3_TX_DMA_INSTANCE, \
  142. .channel = SPI3_TX_DMA_CHANNEL, \
  143. .trigger_evt_src = EVT_SPI3_SPTI, \
  144. .irq_config = \
  145. { \
  146. .irq = SPI3_TX_DMA_IRQn, \
  147. .irq_prio = SPI3_TX_DMA_INT_PRIO, \
  148. .int_src = SPI3_TX_DMA_INT_SRC, \
  149. } \
  150. }
  151. #endif /* SPI3_TX_DMA_CONFIG */
  152. #endif /* BSP_SPI3_TX_USING_DMA */
  153. #ifdef BSP_SPI3_RX_USING_DMA
  154. #ifndef SPI3_RX_DMA_CONFIG
  155. #define SPI3_RX_DMA_CONFIG \
  156. { \
  157. .Instance = SPI3_RX_DMA_INSTANCE, \
  158. .channel = SPI3_RX_DMA_CHANNEL, \
  159. .trigger_evt_src = EVT_SPI3_SPRI, \
  160. .irq_config = \
  161. { \
  162. .irq = SPI3_RX_DMA_IRQn, \
  163. .irq_prio = SPI3_RX_DMA_INT_PRIO, \
  164. .int_src = SPI3_RX_DMA_INT_SRC, \
  165. } \
  166. }
  167. #endif /* SPI3_RX_DMA_CONFIG */
  168. #endif /* BSP_SPI3_RX_USING_DMA */
  169. #ifdef BSP_USING_SPI4
  170. #ifndef SPI4_BUS_CONFIG
  171. #define SPI4_BUS_CONFIG \
  172. { \
  173. .Instance = M4_SPI4, \
  174. .bus_name = SPI4_BUS_NAME, \
  175. }
  176. #endif /* SPI4_BUS_CONFIG */
  177. #endif /* BSP_USING_SPI4 */
  178. #ifdef BSP_SPI4_TX_USING_DMA
  179. #ifndef SPI4_TX_DMA_CONFIG
  180. #define SPI4_TX_DMA_CONFIG \
  181. { \
  182. .Instance = SPI4_TX_DMA_INSTANCE, \
  183. .channel = SPI4_TX_DMA_CHANNEL, \
  184. .trigger_evt_src = EVT_SPI4_SPTI, \
  185. .irq_config = \
  186. { \
  187. .irq = SPI4_TX_DMA_IRQn, \
  188. .irq_prio = SPI4_TX_DMA_INT_PRIO, \
  189. .int_src = SPI4_TX_DMA_INT_SRC, \
  190. } \
  191. }
  192. #endif /* SPI4_TX_DMA_CONFIG */
  193. #endif /* BSP_SPI4_TX_USING_DMA */
  194. #ifdef BSP_SPI4_RX_USING_DMA
  195. #ifndef SPI4_RX_DMA_CONFIG
  196. #define SPI4_RX_DMA_CONFIG \
  197. { \
  198. .Instance = SPI4_RX_DMA_INSTANCE, \
  199. .channel = SPI4_RX_DMA_CHANNEL, \
  200. .trigger_evt_src = EVT_SPI4_SPRI, \
  201. .irq_config = \
  202. { \
  203. .irq = SPI4_RX_DMA_IRQn, \
  204. .irq_prio = SPI4_RX_DMA_INT_PRIO, \
  205. .int_src = SPI4_RX_DMA_INT_SRC, \
  206. } \
  207. }
  208. #endif /* SPI4_RX_DMA_CONFIG */
  209. #endif /* BSP_SPI4_RX_USING_DMA */
  210. #ifdef BSP_USING_SPI5
  211. #ifndef SPI5_BUS_CONFIG
  212. #define SPI5_BUS_CONFIG \
  213. { \
  214. .Instance = M4_SPI5, \
  215. .bus_name = SPI5_BUS_NAME, \
  216. }
  217. #endif /* SPI5_BUS_CONFIG */
  218. #endif /* BSP_USING_SPI5 */
  219. #ifdef BSP_SPI5_TX_USING_DMA
  220. #ifndef SPI5_TX_DMA_CONFIG
  221. #define SPI5_TX_DMA_CONFIG \
  222. { \
  223. .Instance = SPI5_TX_DMA_INSTANCE, \
  224. .channel = SPI5_TX_DMA_CHANNEL, \
  225. .trigger_evt_src = EVT_SPI5_SPTI, \
  226. .irq_config = \
  227. { \
  228. .irq = SPI5_TX_DMA_IRQn, \
  229. .irq_prio = SPI5_TX_DMA_INT_PRIO, \
  230. .int_src = SPI5_TX_DMA_INT_SRC, \
  231. } \
  232. }
  233. #endif /* SPI5_TX_DMA_CONFIG */
  234. #endif /* BSP_SPI5_TX_USING_DMA */
  235. #ifdef BSP_SPI5_RX_USING_DMA
  236. #ifndef SPI5_RX_DMA_CONFIG
  237. #define SPI5_RX_DMA_CONFIG \
  238. { \
  239. .Instance = SPI5_RX_DMA_INSTANCE, \
  240. .channel = SPI5_RX_DMA_CHANNEL, \
  241. .trigger_evt_src = EVT_SPI5_SPRI, \
  242. .irq_config = \
  243. { \
  244. .irq = SPI5_RX_DMA_IRQn, \
  245. .irq_prio = SPI5_RX_DMA_INT_PRIO, \
  246. .int_src = SPI5_RX_DMA_INT_SRC, \
  247. } \
  248. }
  249. #endif /* SPI5_RX_DMA_CONFIG */
  250. #endif /* BSP_SPI5_RX_USING_DMA */
  251. #ifdef BSP_USING_SPI6
  252. #ifndef SPI6_BUS_CONFIG
  253. #define SPI6_BUS_CONFIG \
  254. { \
  255. .Instance = M4_SPI6, \
  256. .bus_name = SPI6_BUS_NAME, \
  257. }
  258. #endif /* SPI6_BUS_CONFIG */
  259. #endif /* BSP_USING_SPI6 */
  260. #ifdef BSP_SPI6_TX_USING_DMA
  261. #ifndef SPI6_TX_DMA_CONFIG
  262. #define SPI6_TX_DMA_CONFIG \
  263. { \
  264. .Instance = SPI6_TX_DMA_INSTANCE, \
  265. .channel = SPI6_TX_DMA_CHANNEL, \
  266. .trigger_evt_src = EVT_SPI6_SPTI, \
  267. .irq_config = \
  268. { \
  269. .irq = SPI6_TX_DMA_IRQn, \
  270. .irq_prio = SPI6_TX_DMA_INT_PRIO, \
  271. .int_src = SPI6_TX_DMA_INT_SRC, \
  272. } \
  273. }
  274. #endif /* SPI6_TX_DMA_CONFIG */
  275. #endif /* BSP_SPI6_TX_USING_DMA */
  276. #ifdef BSP_SPI6_RX_USING_DMA
  277. #ifndef SPI6_RX_DMA_CONFIG
  278. #define SPI6_RX_DMA_CONFIG \
  279. { \
  280. .Instance = SPI6_RX_DMA_INSTANCE, \
  281. .channel = SPI6_RX_DMA_CHANNEL, \
  282. .trigger_evt_src = EVT_SPI6_SPRI, \
  283. .irq_config = \
  284. { \
  285. .irq = SPI6_RX_DMA_IRQn, \
  286. .irq_prio = SPI6_RX_DMA_INT_PRIO, \
  287. .int_src = SPI6_RX_DMA_INT_SRC, \
  288. } \
  289. }
  290. #endif /* SPI6_RX_DMA_CONFIG */
  291. #endif /* BSP_SPI6_RX_USING_DMA */
  292. typedef struct __SPI_HandleType
  293. {
  294. M4_SPI_TypeDef *Instance; /* SPI registers base address */
  295. stc_spi_init_t Init; /* SPI communication parameters */
  296. }SPI_HandleType;
  297. struct hc32_hw_spi_cs
  298. {
  299. rt_uint8_t port;
  300. rt_uint16_t pin;
  301. };
  302. struct hc32_spi_config
  303. {
  304. M4_SPI_TypeDef *Instance;
  305. char *bus_name;
  306. struct dma_config *dma_rx;
  307. struct dma_config *dma_tx;
  308. };
  309. struct stm32_spi_device
  310. {
  311. rt_uint32_t pin;
  312. char *bus_name;
  313. char *device_name;
  314. };
  315. /* HC32 SPI index */
  316. struct spi_index
  317. {
  318. rt_uint32_t index;
  319. M4_SPI_TypeDef *Instance;
  320. };
  321. struct hc32_spi
  322. {
  323. struct rt_spi_bus spi_bus;
  324. SPI_HandleType handle;
  325. struct hc32_spi_config *config;
  326. struct rt_spi_configuration *cfg;
  327. rt_uint16_t spi_dma_flag;
  328. };
  329. /* HC32 SPI irq handler */
  330. struct spi_irq_handler
  331. {
  332. void (*rx_dma_irq_handler)(void);
  333. void (*tx_dma_irq_handler)(void);
  334. };
  335. rt_err_t hc32_hw_spi_device_attach(const char *bus_name,
  336. const char *device_name,
  337. uint8_t cs_gpio_port,
  338. uint16_t cs_gpio_pin);
  339. #ifdef __cplusplus
  340. }
  341. #endif
  342. #endif /* __DRV_SPI_H__ */