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- /*
- * Copyright 2018 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
- #include "evkmimxrt1064_flexspi_nor_config.h"
- /*******************************************************************************
- * Code
- ******************************************************************************/
- #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
- #if defined(__CC_ARM) || defined(__GNUC__)
- __attribute__((section(".boot_hdr.conf")))
- #elif defined(__ICCARM__)
- #pragma location = ".boot_hdr.conf"
- #endif
- const flexspi_nor_config_t qspiflash_config = {
- .memConfig =
- {
- .tag = FLEXSPI_CFG_BLK_TAG,
- .version = FLEXSPI_CFG_BLK_VERSION,
- .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
- .csHoldTime = 3u,
- .csSetupTime = 3u,
- // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
- .sflashPadType = kSerialFlash_4Pads,
- .serialClkFreq = kFlexSpiSerialClk_100MHz,
- .sflashA1Size = 8u * 1024u * 1024u,
- .lookupTable =
- {
- // Read LUTs
- FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18),
- FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
- },
- },
- .pageSize = 256u,
- .sectorSize = 4u * 1024u,
- .blockSize = 256u * 1024u,
- .isUniformBlockSize = false,
- };
- #endif /* XIP_BOOT_HEADER_ENABLE */
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