board.h 1.2 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-20 breo.com first version
  9. */
  10. #ifndef __BOARD_H__
  11. #define __BOARD_H__
  12. #include <n32g45x.h>
  13. #include "n32_msp.h"
  14. #ifdef __cplusplus
  15. extern "C" {
  16. #endif
  17. /* Just only support for N32G452XX */
  18. #define N32_FLASH_START_ADRESS ((uint32_t)0x08000000)
  19. #define FLASH_PAGE_SIZE (2 * 1024)
  20. #define N32_FLASH_SIZE (256 * 1024)
  21. #define N32_FLASH_END_ADDRESS ((uint32_t)(N32_FLASH_START_ADRESS + N32_FLASH_SIZE))
  22. /* Internal SRAM memory size[Kbytes] <80>, Default: 80*/
  23. #define N32_SRAM_SIZE (80)
  24. #define N32_SRAM_END (0x20000000 + N32_SRAM_SIZE * 1024)
  25. #if defined(__CC_ARM) || defined(__CLANG_ARM)
  26. extern int Image$$RW_IRAM1$$ZI$$Limit;
  27. #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
  28. #elif __ICCARM__
  29. #pragma section="CSTACK"
  30. #define HEAP_BEGIN (__segment_end("CSTACK"))
  31. #else
  32. extern int __bss_end;
  33. #define HEAP_BEGIN ((void *)&__bss_end)
  34. #endif
  35. #define HEAP_END N32_SRAM_END
  36. #ifdef __cplusplus
  37. }
  38. #endif
  39. #endif /* __BOARD_H__ */