hwtimer.c 7.8 KB

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  1. /*
  2. * Copyright (c) 2006-2021, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2015-08-31 heyuanjie87 first version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include <rthw.h>
  13. rt_inline rt_uint32_t timeout_calc(rt_hwtimer_t *timer, rt_hwtimerval_t *tv)
  14. {
  15. float overflow;
  16. float timeout;
  17. rt_uint32_t counter;
  18. int i, index = 0;
  19. float tv_sec;
  20. float devi_min = 1;
  21. float devi;
  22. /* changed to second */
  23. overflow = timer->info->maxcnt/(float)timer->freq;
  24. tv_sec = tv->sec + tv->usec/(float)1000000;
  25. if (tv_sec < (1/(float)timer->freq))
  26. {
  27. /* little timeout */
  28. i = 0;
  29. timeout = 1/(float)timer->freq;
  30. }
  31. else
  32. {
  33. for (i = 1; i > 0; i ++)
  34. {
  35. timeout = tv_sec/i;
  36. if (timeout <= overflow)
  37. {
  38. counter = (rt_uint32_t)(timeout * timer->freq);
  39. devi = tv_sec - (counter / (float)timer->freq) * i;
  40. /* Minimum calculation error */
  41. if (devi > devi_min)
  42. {
  43. i = index;
  44. timeout = tv_sec/i;
  45. break;
  46. }
  47. else if (devi == 0)
  48. {
  49. break;
  50. }
  51. else if (devi < devi_min)
  52. {
  53. devi_min = devi;
  54. index = i;
  55. }
  56. }
  57. }
  58. }
  59. timer->cycles = i;
  60. timer->reload = i;
  61. timer->period_sec = timeout;
  62. counter = (rt_uint32_t)(timeout * timer->freq);
  63. return counter;
  64. }
  65. static rt_err_t rt_hwtimer_init(struct rt_device *dev)
  66. {
  67. rt_err_t result = RT_EOK;
  68. rt_hwtimer_t *timer;
  69. timer = (rt_hwtimer_t *)dev;
  70. /* try to change to 1MHz */
  71. if ((1000000 <= timer->info->maxfreq) && (1000000 >= timer->info->minfreq))
  72. {
  73. timer->freq = 1000000;
  74. }
  75. else
  76. {
  77. timer->freq = timer->info->minfreq;
  78. }
  79. timer->mode = HWTIMER_MODE_ONESHOT;
  80. timer->cycles = 0;
  81. timer->overflow = 0;
  82. if (timer->ops->init)
  83. {
  84. timer->ops->init(timer, 1);
  85. }
  86. else
  87. {
  88. result = -RT_ENOSYS;
  89. }
  90. return result;
  91. }
  92. static rt_err_t rt_hwtimer_open(struct rt_device *dev, rt_uint16_t oflag)
  93. {
  94. rt_err_t result = RT_EOK;
  95. rt_hwtimer_t *timer;
  96. timer = (rt_hwtimer_t *)dev;
  97. if (timer->ops->control != RT_NULL)
  98. {
  99. timer->ops->control(timer, HWTIMER_CTRL_FREQ_SET, &timer->freq);
  100. }
  101. else
  102. {
  103. result = -RT_ENOSYS;
  104. }
  105. return result;
  106. }
  107. static rt_err_t rt_hwtimer_close(struct rt_device *dev)
  108. {
  109. rt_err_t result = RT_EOK;
  110. rt_hwtimer_t *timer;
  111. timer = (rt_hwtimer_t*)dev;
  112. if (timer->ops->init != RT_NULL)
  113. {
  114. timer->ops->init(timer, 0);
  115. }
  116. else
  117. {
  118. result = -RT_ENOSYS;
  119. }
  120. dev->flag &= ~RT_DEVICE_FLAG_ACTIVATED;
  121. dev->rx_indicate = RT_NULL;
  122. return result;
  123. }
  124. static rt_size_t rt_hwtimer_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size)
  125. {
  126. rt_hwtimer_t *timer;
  127. rt_hwtimerval_t tv;
  128. rt_uint32_t cnt;
  129. rt_base_t level;
  130. rt_int32_t overflow;
  131. float t;
  132. timer = (rt_hwtimer_t *)dev;
  133. if (timer->ops->count_get == RT_NULL)
  134. return 0;
  135. level = rt_hw_interrupt_disable();
  136. cnt = timer->ops->count_get(timer);
  137. overflow = timer->overflow;
  138. rt_hw_interrupt_enable(level);
  139. if (timer->info->cntmode == HWTIMER_CNTMODE_DW)
  140. {
  141. cnt = (rt_uint32_t)(timer->freq * timer->period_sec) - cnt;
  142. }
  143. t = overflow * timer->period_sec + cnt/(float)timer->freq;
  144. tv.sec = (rt_int32_t)t;
  145. tv.usec = (rt_int32_t)((t - tv.sec) * 1000000);
  146. size = size > sizeof(tv)? sizeof(tv) : size;
  147. rt_memcpy(buffer, &tv, size);
  148. return size;
  149. }
  150. static rt_size_t rt_hwtimer_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size)
  151. {
  152. rt_uint32_t t;
  153. rt_hwtimer_mode_t opm = HWTIMER_MODE_PERIOD;
  154. rt_hwtimer_t *timer;
  155. timer = (rt_hwtimer_t *)dev;
  156. if ((timer->ops->start == RT_NULL) || (timer->ops->stop == RT_NULL))
  157. return 0;
  158. if (size != sizeof(rt_hwtimerval_t))
  159. return 0;
  160. timer->ops->stop(timer);
  161. timer->overflow = 0;
  162. t = timeout_calc(timer, (rt_hwtimerval_t*)buffer);
  163. if ((timer->cycles <= 1) && (timer->mode == HWTIMER_MODE_ONESHOT))
  164. {
  165. opm = HWTIMER_MODE_ONESHOT;
  166. }
  167. if (timer->ops->start(timer, t, opm) != RT_EOK)
  168. size = 0;
  169. return size;
  170. }
  171. static rt_err_t rt_hwtimer_control(struct rt_device *dev, int cmd, void *args)
  172. {
  173. rt_err_t result = RT_EOK;
  174. rt_hwtimer_t *timer;
  175. timer = (rt_hwtimer_t *)dev;
  176. switch (cmd)
  177. {
  178. case HWTIMER_CTRL_STOP:
  179. {
  180. if (timer->ops->stop != RT_NULL)
  181. {
  182. timer->ops->stop(timer);
  183. }
  184. else
  185. {
  186. result = -RT_ENOSYS;
  187. }
  188. }
  189. break;
  190. case HWTIMER_CTRL_FREQ_SET:
  191. {
  192. rt_uint32_t *f;
  193. if (args == RT_NULL)
  194. {
  195. result = -RT_EEMPTY;
  196. break;
  197. }
  198. f = (rt_uint32_t*)args;
  199. if ((*f > timer->info->maxfreq) || (*f < timer->info->minfreq))
  200. {
  201. result = -RT_ERROR;
  202. break;
  203. }
  204. if (timer->ops->control != RT_NULL)
  205. {
  206. result = timer->ops->control(timer, cmd, args);
  207. if (result == RT_EOK)
  208. {
  209. timer->freq = *f;
  210. }
  211. }
  212. else
  213. {
  214. result = -RT_ENOSYS;
  215. }
  216. }
  217. break;
  218. case HWTIMER_CTRL_INFO_GET:
  219. {
  220. if (args == RT_NULL)
  221. {
  222. result = -RT_EEMPTY;
  223. break;
  224. }
  225. *((struct rt_hwtimer_info*)args) = *timer->info;
  226. }
  227. break;
  228. case HWTIMER_CTRL_MODE_SET:
  229. {
  230. rt_hwtimer_mode_t *m;
  231. if (args == RT_NULL)
  232. {
  233. result = -RT_EEMPTY;
  234. break;
  235. }
  236. m = (rt_hwtimer_mode_t*)args;
  237. if ((*m != HWTIMER_MODE_ONESHOT) && (*m != HWTIMER_MODE_PERIOD))
  238. {
  239. result = -RT_ERROR;
  240. break;
  241. }
  242. timer->mode = *m;
  243. }
  244. break;
  245. default:
  246. {
  247. result = -RT_ENOSYS;
  248. }
  249. break;
  250. }
  251. return result;
  252. }
  253. void rt_device_hwtimer_isr(rt_hwtimer_t *timer)
  254. {
  255. RT_ASSERT(timer != RT_NULL);
  256. timer->overflow ++;
  257. if (timer->cycles != 0)
  258. {
  259. timer->cycles --;
  260. }
  261. if (timer->cycles == 0)
  262. {
  263. timer->cycles = timer->reload;
  264. if (timer->mode == HWTIMER_MODE_ONESHOT)
  265. {
  266. if (timer->ops->stop != RT_NULL)
  267. {
  268. timer->ops->stop(timer);
  269. }
  270. }
  271. if (timer->parent.rx_indicate != RT_NULL)
  272. {
  273. timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_hwtimerval));
  274. }
  275. }
  276. }
  277. #ifdef RT_USING_DEVICE_OPS
  278. const static struct rt_device_ops hwtimer_ops =
  279. {
  280. rt_hwtimer_init,
  281. rt_hwtimer_open,
  282. rt_hwtimer_close,
  283. rt_hwtimer_read,
  284. rt_hwtimer_write,
  285. rt_hwtimer_control
  286. };
  287. #endif
  288. rt_err_t rt_device_hwtimer_register(rt_hwtimer_t *timer, const char *name, void *user_data)
  289. {
  290. struct rt_device *device;
  291. RT_ASSERT(timer != RT_NULL);
  292. RT_ASSERT(timer->ops != RT_NULL);
  293. RT_ASSERT(timer->info != RT_NULL);
  294. device = &(timer->parent);
  295. device->type = RT_Device_Class_Timer;
  296. device->rx_indicate = RT_NULL;
  297. device->tx_complete = RT_NULL;
  298. #ifdef RT_USING_DEVICE_OPS
  299. device->ops = &hwtimer_ops;
  300. #else
  301. device->init = rt_hwtimer_init;
  302. device->open = rt_hwtimer_open;
  303. device->close = rt_hwtimer_close;
  304. device->read = rt_hwtimer_read;
  305. device->write = rt_hwtimer_write;
  306. device->control = rt_hwtimer_control;
  307. #endif
  308. device->user_data = user_data;
  309. return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  310. }