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bsp
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bouffalo_lab
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bl61x
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board
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fw_header.c

fw_header.c 11 KB
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  1. #include "fw_header.h"
    2. 

  2. 

  3. __attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
    4. 

  4.     .magiccode = 0x504e4642,
    5. 

  5.     .rivison = 0x00000001,
    6. 

  6.     /*flash config */
    7. 

  7.     .flash_cfg.magiccode = 0x47464346,
    8. 

  8.     .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
    9. 

  9. #if defined (BSP_USING_BL61X_MODULE_DEFAULT)
    10. 

  10.     .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
    11. 

  11. #elif defined (BSP_USING_BL61X_MODULE_M0P)
    12. 

  12.     .flash_cfg.cfg.cReadSupport = 0x01,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
    13. 

  13. #endif
    14. 

  14.     .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
    15. 

  15.     .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
    16. 

  16.     .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
    17. 

  17.     .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
    18. 

  18.     .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
    19. 

  19.     .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
    20. 

  20.     .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
    21. 

  21.     .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
    22. 

  22.     .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
    23. 

  23.     .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
    24. 

  24.     .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
    25. 

  25.     .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
    26. 

  26.     .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
    27. 

  27.     .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
    28. 

  28.     .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
    29. 

  29.     .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
    30. 

  30.     .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
    31. 

  31.     .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
    32. 

  32.     .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
    33. 

  33.     .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
    34. 

  34.     .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
    35. 

  35.     .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
    36. 

  36.     .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
    37. 

  37.     .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
    38. 

  38.     .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
    39. 

  39.     .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
    40. 

  40.     .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
    41. 

  41.     .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
    42. 

  42.     .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
    43. 

  43.     .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
    44. 

  44.     .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
    45. 

  45.     .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
    46. 

  46.     .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
    47. 

  47.     .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
    48. 

  48.     .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
    49. 

  49.     .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
    50. 

  50.     .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
    51. 

  51.     .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
    52. 

  52.     .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
    53. 

  53.     .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
    54. 

  54.     .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
    55. 

  55.     .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
    56. 

  56.     .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
    57. 

  57.     .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
    58. 

  58.     .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
    59. 

  59.     .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
    60. 

  60.     .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
    61. 

  61.     .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
    62. 

  62.     .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
    63. 

  63.     .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
    64. 

  64.     .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
    65. 

  65.     .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
    66. 

  66.     .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
    67. 

  67.     .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
    68. 

  68.     .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
    69. 

  69.     .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
    70. 

  70.     .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
    71. 

  71.     .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
    72. 

  72.     .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
    73. 

  73.     .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
    74. 

  74.     .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
    75. 

  75.     .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
    76. 

  76.     .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
    77. 

  77.     .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
    78. 

  78.     .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
    79. 

  79.     .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
    80. 

  80.     .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
    81. 

  81.     .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
    82. 

  82.     .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
    83. 

  83.     .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
    84. 

  84.     .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
    85. 

  85.     .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
    86. 

  86.     .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
    87. 

  87.     .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
    88. 

  88.     .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
    89. 

  89.     .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
    90. 

  90.     .flash_cfg.crc32 = 0xdeadbeef,
    91. 

  91.     /* clock cfg */
    92. 

  92.     .clk_cfg.magiccode = 0x47464350,
    93. 

  93.     .clk_cfg.cfg.xtal_type = 0x07,      /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
    94. 

  94.     .clk_cfg.cfg.mcu_clk = 0x05,        /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
    95. 

  95.     .clk_cfg.cfg.mcu_clk_div = 0x00,    /*!< mcu_clk divider */
    96. 

  96.     .clk_cfg.cfg.mcu_bclk_div = 0x00,   /*!< mcu_bclk divider */
    97. 

  97.     .clk_cfg.cfg.mcu_pbclk_div = 0x03,  /*!< mcu_pclk divider */
    98. 

  98.     .clk_cfg.cfg.emi_clk = 0x02,        /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
    99. 

  99.     .clk_cfg.cfg.emi_clk_div = 0x01,    /*!< emi clock divider */
    100. 

  100.     .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
    101. 

  101.     .clk_cfg.cfg.flash_clk_div = 0x00,
    102. 

  102.     .clk_cfg.cfg.wifipll_pu = 0x01,
    103. 

  103.     .clk_cfg.cfg.aupll_pu = 0x00,
    104. 

  104.     .clk_cfg.crc32 = 0xdeadbeef,
    105. 

  105.     /* basic cfg */
    106. 

  106.     .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
    107. 

  107.     .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
    108. 

  108.     .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
    109. 

  109.     .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
    110. 

  110.     .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
    111. 

  111.     .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
    112. 

  112.     .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
    113. 

  113.     .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
    114. 

  114.     .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
    115. 

  115.     .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
    116. 

  116.     .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
    117. 

  117.     .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
    118. 

  118.     .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
    119. 

  119.     .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
    120. 

  120.     .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
    121. 

  121. #if 0
    122. 

  122. # 0 : cmds bypass wrap commands to macro, original mode;
    123. 

  123. # 1 : cmds handle wrap commands, original mode;
    124. 

  124. # 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
    125. 

  125. # 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
    126. 

  126. #endif
    127. 

  127.     .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
    128. 

  128. #if 0
    129. 

  129. # 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
    130. 

  130. # 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
    131. 

  131. #endif
    132. 

  132.     .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
    133. 

  133.     .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
    134. 

  134.     .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
    135. 

  135.     .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
    136. 

  136. 

  137.     .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
    138. 

  138.     .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
    139. 

  139. 

  140.     .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
    141. 

  141.     .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
    142. 

  142. 

  143.     /* cpu cfg */
    144. 

  144.     .cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
    145. 

  145.     .cpu_cfg.halt_cpu = 0x0,       /* halt this cpu */
    146. 

  146.     .cpu_cfg.cache_enable = 0x0,   /* cache setting :only for BL Cache */
    147. 

  147.     .cpu_cfg.cache_wa = 0x0,       /* cache setting :only for BL Cache*/
    148. 

  148.     .cpu_cfg.cache_wb = 0x0,       /* cache setting :only for BL Cache*/
    149. 

  149.     .cpu_cfg.cache_wt = 0x0,       /* cache setting :only for BL Cache*/
    150. 

  150.     .cpu_cfg.cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
    151. 

  151.     .cpu_cfg.rsvd = 0x0,
    152. 

  152. 

  153.     /* image_address_offset */
    154. 

  154.     .cpu_cfg.image_address_offset = 0x0,
    155. 

  155.     .cpu_cfg.rsvd1 = 0xA0000000,   /* rsvd */
    156. 

  156.     .cpu_cfg.msp_val = 0x00000000, /* msp value */
    157. 

  157. 

  158.     /* address of partition table 0 */
    159. 

  159.     .boot2_pt_table_0_rsvd = 0x00000000,
    160. 

  160.     /* address of partition table 1 */
    161. 

  161.     .boot2_pt_table_1_rsvd = 0x00000000,
    162. 

  162. 

  163.     /* address of flashcfg table list */
    164. 

  164.     .flash_cfg_table_addr = 0x00000000,
    165. 

  165.     /* flashcfg table list len */
    166. 

  166.     .flash_cfg_table_len = 0x00000000,
    167. 

  167. 

  168.     .crc32 = 0xdeadbeef
    169. 

  169. };
    170.