drv_spi.c 5.6 KB

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  1. /*
  2. * Copyright (c) 2006-2020, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-10-28 0xcccccccccccc Initial Version
  9. */
  10. /**
  11. * @addtogroup ls2k
  12. */
  13. /*@{*/
  14. #include <stdio.h>
  15. #include <stdlib.h>
  16. #include <ctype.h>
  17. #include <rtthread.h>
  18. #include <drivers/spi.h>
  19. #include "drv_spi.h"
  20. #ifdef RT_USING_SPI
  21. static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
  22. {
  23. SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011));
  24. SET_SPI(PARAM, 0x40);
  25. SET_SPI(PARAM2, 0x01);
  26. SET_SPI(SPER, (spre_spr & 0b00001100) >> 2);
  27. SET_SPI(SPCR, 0x50 | copl << 3 | cpha << 2);
  28. SET_SPI(SOFTCS, 0xff);
  29. }
  30. static void spi_set_csn(uint8_t val)
  31. {
  32. SET_SPI(SOFTCS, val);
  33. }
  34. #ifdef RT_USING_SPI_GPIOCS
  35. #include <drivers/pin.h>
  36. #endif
  37. static void spi_set_cs(unsigned char cs, int new_status)
  38. {
  39. if (cs < 4)
  40. {
  41. unsigned char val = 0;
  42. val = GET_SPI(SOFTCS);
  43. val |= 0x01 << cs ; // csen=1
  44. if (new_status) // cs = 1
  45. {
  46. val |= (0x10 << cs); // csn=1
  47. }
  48. else // cs = 0
  49. {
  50. val &= ~(0x10 << cs); // csn=0
  51. }
  52. SET_SPI(SOFTCS, val);
  53. return ;
  54. }
  55. #ifdef RT_USING_SPI_GPIOCS
  56. else
  57. {
  58. rt_pin_mode(cs, PIN_MODE_OUTPUT); // with RT_USING_SPI_GPIOCS feature enabled, gpio will be used as csn pin.
  59. rt_pin_write(cs, new_status);
  60. }
  61. #endif
  62. }
  63. static uint8_t spi_write_for_response(uint8_t data)
  64. {
  65. uint8_t val;
  66. SET_SPI(TXFIFO, data);
  67. while ((GET_SPI(SPSR))&RFEMPTY); //wait for echo
  68. val = GET_SPI(RXFIFO);
  69. return val;
  70. }
  71. static int cmd_spi_init(int argc, char *argv[])
  72. {
  73. uint8_t spre_spr, cpol, cpha;
  74. switch (argc)
  75. {
  76. case 2:
  77. spre_spr = strtoul(argv[1], NULL, 0);
  78. spi_init(spre_spr, 0, 0);
  79. break;
  80. case 4:
  81. spre_spr = strtoul(argv[1], NULL, 0);
  82. cpol = strtoul(argv[2], NULL, 0);
  83. cpha = strtoul(argv[3], NULL, 0);
  84. spi_init(spre_spr, 0, 0);
  85. break;
  86. default:
  87. printf("\nusage : cmd_spi_init spre_spr <cpol> <cpha>\n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n");
  88. break;
  89. }
  90. }
  91. MSH_CMD_EXPORT(cmd_spi_init, cmd_spi_init);
  92. static int cmd_spi_set_csn(int argc, char *argv[])
  93. {
  94. uint8_t val, csn;
  95. switch (argc)
  96. {
  97. case 3:
  98. csn = strtoul(argv[1], NULL, 0);
  99. val = strtoul(argv[2], NULL, 0);
  100. spi_set_cs(csn, val);
  101. break;
  102. default:
  103. printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n");
  104. break;
  105. }
  106. }
  107. MSH_CMD_EXPORT(cmd_spi_set_csn, cmd_spi_set_csn);
  108. static int cmd_spi_write(int argc, char *argv[])
  109. {
  110. uint8_t data, resp;
  111. switch (argc)
  112. {
  113. case 2:
  114. data = strtoul(argv[1], NULL, 0);
  115. resp = spi_write_for_response(data);
  116. printf("resp:%2X\n", resp);
  117. break;
  118. default:
  119. printf("usage:cmd_spi_write data\n");
  120. break;
  121. }
  122. }
  123. MSH_CMD_EXPORT(cmd_spi_write, cmd_spi_write);
  124. static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
  125. static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message);
  126. const static unsigned char SPI_DIV_TABLE[] = {0b0000, 0b0001, 0b0100, 0b0010, 0b0011, 0b0101, 0b0110, 0b0111, 0b1000, 0b1001, 0b1010, 0b1011};
  127. // 2 4 8 16 32 64 128 256 512 1024 2048 4096
  128. static rt_err_t configure(struct rt_spi_device *device,
  129. struct rt_spi_configuration *configuration)
  130. {
  131. unsigned char cpol = 0;
  132. unsigned char cpha = 0;
  133. RT_ASSERT(NULL != device);
  134. RT_ASSERT(NULL != configuration);
  135. // baudrate
  136. if (configuration->mode & RT_SPI_CPOL) // cpol
  137. {
  138. cpol = 1;
  139. }
  140. else
  141. {
  142. cpol = 0;
  143. }
  144. if (configuration->mode & RT_SPI_CPHA) // cpha
  145. {
  146. cpha = 1;
  147. }
  148. else
  149. {
  150. cpha = 0;
  151. }
  152. float spi_max_speed = ((float)APB_MAX_SPEED) / (8.0 / (float)APB_FREQSCALE);
  153. uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz);
  154. int ctr = 0;
  155. while (div != 1 && ctr < 12)
  156. {
  157. ctr++;
  158. div = div >> 1;
  159. }
  160. spi_init(SPI_DIV_TABLE[ctr], cpol, cpha);
  161. return RT_EOK;
  162. }
  163. static rt_uint32_t xfer(struct rt_spi_device *device,
  164. struct rt_spi_message *message)
  165. {
  166. unsigned char cs = 0;
  167. rt_uint32_t size = 0;
  168. const rt_uint8_t *send_ptr = NULL;
  169. rt_uint8_t *recv_ptr = NULL;
  170. rt_uint8_t data = 0;
  171. RT_ASSERT(NULL != device);
  172. RT_ASSERT(NULL != message);
  173. cs = (unsigned char)(device->parent.user_data);
  174. size = message->length;
  175. if (message->cs_take)
  176. {
  177. spi_set_cs(cs, 0);
  178. }
  179. // send data
  180. send_ptr = message->send_buf;
  181. recv_ptr = message->recv_buf;
  182. while (size--)
  183. {
  184. data = 0xFF;
  185. if (NULL != send_ptr)
  186. {
  187. data = *send_ptr++;
  188. }
  189. if (NULL != recv_ptr)
  190. {
  191. *recv_ptr++ = spi_write_for_response(data);
  192. }
  193. else
  194. {
  195. spi_write_for_response(data);
  196. }
  197. }
  198. // release cs
  199. if (message->cs_release)
  200. {
  201. spi_set_cs(cs, 1);
  202. }
  203. return message->length;
  204. }
  205. static struct rt_spi_ops loongson_spi_ops =
  206. {
  207. .configure = configure,
  208. .xfer = xfer
  209. };
  210. static struct rt_spi_bus loongson_spi;
  211. static int loongson_spi_init()
  212. {
  213. //rt_kprintf("spi_init\n");
  214. return rt_spi_bus_register(&loongson_spi, "spi", &loongson_spi_ops);
  215. }
  216. INIT_BOARD_EXPORT(loongson_spi_init);
  217. #endif
  218. /*@}*/