Driver_MCI.h 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360
  1. /*
  2. * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the License); you may
  7. * not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. *
  18. * $Date: 2. Feb 2017
  19. * $Revision: V2.3
  20. *
  21. * Project: MCI (Memory Card Interface) Driver definitions
  22. */
  23. /* History:
  24. * Version 2.3
  25. * ARM_MCI_STATUS made volatile
  26. * Version 2.2
  27. * Added timeout and error flags to ARM_MCI_STATUS
  28. * Added support for controlling optional RST_n pin (eMMC)
  29. * Removed explicit Clock Control (ARM_MCI_CONTROL_CLOCK)
  30. * Removed event ARM_MCI_EVENT_BOOT_ACK_TIMEOUT
  31. * Version 2.1
  32. * Decoupled SPI mode from MCI driver
  33. * Replaced function ARM_MCI_CardSwitchRead with ARM_MCI_ReadCD and ARM_MCI_ReadWP
  34. * Version 2.0
  35. * Added support for:
  36. * SD UHS-I (Ultra High Speed)
  37. * SD I/O Interrupt
  38. * Read Wait (SD I/O)
  39. * Suspend/Resume (SD I/O)
  40. * MMC Interrupt
  41. * MMC Boot
  42. * Stream Data transfer (MMC)
  43. * VCCQ Power Supply Control (eMMC)
  44. * Command Completion Signal (CCS) for CE-ATA
  45. * Added ARM_MCI_Control function
  46. * Added ARM_MCI_GetStatus function
  47. * Removed ARM_MCI_BusMode, ARM_MCI_BusDataWidth, ARM_MCI_BusSingaling functions
  48. * (replaced by ARM_MCI_Control)
  49. * Changed ARM_MCI_CardPower function (voltage parameter)
  50. * Changed ARM_MCI_SendCommnad function (flags parameter)
  51. * Changed ARM_MCI_SetupTransfer function (mode parameter)
  52. * Removed ARM_MCI_ReadTransfer and ARM_MCI_WriteTransfer functions
  53. * Changed prefix ARM_DRV -> ARM_DRIVER
  54. * Changed return values of some functions to int32_t
  55. * Version 1.10
  56. * Namespace prefix ARM_ added
  57. * Version 1.00
  58. * Initial release
  59. */
  60. #ifndef DRIVER_MCI_H_
  61. #define DRIVER_MCI_H_
  62. #ifdef __cplusplus
  63. extern "C"
  64. {
  65. #endif
  66. #include "Driver_Common.h"
  67. #define ARM_MCI_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
  68. /****** MCI Send Command Flags *****/
  69. #define ARM_MCI_RESPONSE_Pos 0
  70. #define ARM_MCI_RESPONSE_Msk (3UL << ARM_MCI_RESPONSE_Pos)
  71. #define ARM_MCI_RESPONSE_NONE (0UL << ARM_MCI_RESPONSE_Pos) ///< No response expected (default)
  72. #define ARM_MCI_RESPONSE_SHORT (1UL << ARM_MCI_RESPONSE_Pos) ///< Short response (48-bit)
  73. #define ARM_MCI_RESPONSE_SHORT_BUSY (2UL << ARM_MCI_RESPONSE_Pos) ///< Short response with busy signal (48-bit)
  74. #define ARM_MCI_RESPONSE_LONG (3UL << ARM_MCI_RESPONSE_Pos) ///< Long response (136-bit)
  75. #define ARM_MCI_RESPONSE_INDEX (1UL << 2) ///< Check command index in response
  76. #define ARM_MCI_RESPONSE_CRC (1UL << 3) ///< Check CRC in response
  77. #define ARM_MCI_WAIT_BUSY (1UL << 4) ///< Wait until busy before sending the command
  78. #define ARM_MCI_TRANSFER_DATA (1UL << 5) ///< Activate Data transfer
  79. #define ARM_MCI_CARD_INITIALIZE (1UL << 6) ///< Execute Memory Card initialization sequence
  80. #define ARM_MCI_INTERRUPT_COMMAND (1UL << 7) ///< Send Interrupt command (CMD40 - MMC only)
  81. #define ARM_MCI_INTERRUPT_RESPONSE (1UL << 8) ///< Send Interrupt response (CMD40 - MMC only)
  82. #define ARM_MCI_BOOT_OPERATION (1UL << 9) ///< Execute Boot operation (MMC only)
  83. #define ARM_MCI_BOOT_ALTERNATIVE (1UL << 10) ///< Execute Alternative Boot operation (MMC only)
  84. #define ARM_MCI_BOOT_ACK (1UL << 11) ///< Expect Boot Acknowledge (MMC only)
  85. #define ARM_MCI_CCSD (1UL << 12) ///< Send Command Completion Signal Disable (CCSD) for CE-ATA device
  86. #define ARM_MCI_CCS (1UL << 13) ///< Expect Command Completion Signal (CCS) for CE-ATA device
  87. /****** MCI Setup Transfer Mode *****/
  88. #define ARM_MCI_TRANSFER_READ (0UL << 0) ///< Data Read Transfer (from MCI)
  89. #define ARM_MCI_TRANSFER_WRITE (1UL << 0) ///< Data Write Transfer (to MCI)
  90. #define ARM_MCI_TRANSFER_BLOCK (0UL << 1) ///< Block Data transfer (default)
  91. #define ARM_MCI_TRANSFER_STREAM (1UL << 1) ///< Stream Data transfer (MMC only)
  92. /****** MCI Control Codes *****/
  93. #define ARM_MCI_BUS_SPEED (0x01) ///< Set Bus Speed; arg = requested speed in bits/s; returns configured speed in bits/s
  94. #define ARM_MCI_BUS_SPEED_MODE (0x02) ///< Set Bus Speed Mode as specified with arg
  95. #define ARM_MCI_BUS_CMD_MODE (0x03) ///< Set CMD Line Mode as specified with arg
  96. #define ARM_MCI_BUS_DATA_WIDTH (0x04) ///< Set Bus Data Width as specified with arg
  97. #define ARM_MCI_DRIVER_STRENGTH (0x05) ///< Set SD UHS-I Driver Strength as specified with arg
  98. #define ARM_MCI_CONTROL_RESET (0x06) ///< Control optional RST_n Pin (eMMC); arg: 0=inactive, 1=active
  99. #define ARM_MCI_CONTROL_CLOCK_IDLE (0x07) ///< Control Clock generation on CLK Pin when idle; arg: 0=disabled, 1=enabled
  100. #define ARM_MCI_UHS_TUNING_OPERATION (0x08) ///< Sampling clock Tuning operation (SD UHS-I); arg: 0=reset, 1=execute
  101. #define ARM_MCI_UHS_TUNING_RESULT (0x09) ///< Sampling clock Tuning result (SD UHS-I); returns: 0=done, 1=in progress, -1=error
  102. #define ARM_MCI_DATA_TIMEOUT (0x0A) ///< Set Data timeout; arg = timeout in bus cycles
  103. #define ARM_MCI_CSS_TIMEOUT (0x0B) ///< Set Command Completion Signal (CCS) timeout; arg = timeout in bus cycles
  104. #define ARM_MCI_MONITOR_SDIO_INTERRUPT (0x0C) ///< Monitor SD I/O interrupt: arg: 0=disabled, 1=enabled
  105. #define ARM_MCI_CONTROL_READ_WAIT (0x0D) ///< Control Read/Wait for SD I/O; arg: 0=disabled, 1=enabled
  106. #define ARM_MCI_SUSPEND_TRANSFER (0x0E) ///< Suspend Data transfer (SD I/O); returns number of remaining bytes to transfer
  107. #define ARM_MCI_RESUME_TRANSFER (0x0F) ///< Resume Data transfer (SD I/O)
  108. /*----- MCI Bus Speed Mode -----*/
  109. #define ARM_MCI_BUS_DEFAULT_SPEED (0x00) ///< SD/MMC: Default Speed mode up to 25/26MHz
  110. #define ARM_MCI_BUS_HIGH_SPEED (0x01) ///< SD/MMC: High Speed mode up to 50/52MHz
  111. #define ARM_MCI_BUS_UHS_SDR12 (0x02) ///< SD: SDR12 (Single Data Rate) up to 25MHz, 12.5MB/s: UHS-I (Ultra High Speed) 1.8V signaling
  112. #define ARM_MCI_BUS_UHS_SDR25 (0x03) ///< SD: SDR25 (Single Data Rate) up to 50MHz, 25 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
  113. #define ARM_MCI_BUS_UHS_SDR50 (0x04) ///< SD: SDR50 (Single Data Rate) up to 100MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
  114. #define ARM_MCI_BUS_UHS_SDR104 (0x05) ///< SD: SDR104 (Single Data Rate) up to 208MHz, 104 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
  115. #define ARM_MCI_BUS_UHS_DDR50 (0x06) ///< SD: DDR50 (Dual Data Rate) up to 50MHz, 50 MB/s: UHS-I (Ultra High Speed) 1.8V signaling
  116. /*----- MCI CMD Line Mode -----*/
  117. #define ARM_MCI_BUS_CMD_PUSH_PULL (0x00) ///< Push-Pull CMD line (default)
  118. #define ARM_MCI_BUS_CMD_OPEN_DRAIN (0x01) ///< Open Drain CMD line (MMC only)
  119. /*----- MCI Bus Data Width -----*/
  120. #define ARM_MCI_BUS_DATA_WIDTH_1 (0x00) ///< Bus data width: 1 bit (default)
  121. #define ARM_MCI_BUS_DATA_WIDTH_4 (0x01) ///< Bus data width: 4 bits
  122. #define ARM_MCI_BUS_DATA_WIDTH_8 (0x02) ///< Bus data width: 8 bits
  123. #define ARM_MCI_BUS_DATA_WIDTH_4_DDR (0x03) ///< Bus data width: 4 bits, DDR (Dual Data Rate) - MMC only
  124. #define ARM_MCI_BUS_DATA_WIDTH_8_DDR (0x04) ///< Bus data width: 8 bits, DDR (Dual Data Rate) - MMC only
  125. /*----- MCI Driver Strength -----*/
  126. #define ARM_MCI_DRIVER_TYPE_A (0x01) ///< SD UHS-I Driver Type A
  127. #define ARM_MCI_DRIVER_TYPE_B (0x00) ///< SD UHS-I Driver Type B (default)
  128. #define ARM_MCI_DRIVER_TYPE_C (0x02) ///< SD UHS-I Driver Type C
  129. #define ARM_MCI_DRIVER_TYPE_D (0x03) ///< SD UHS-I Driver Type D
  130. /****** MCI Card Power *****/
  131. #define ARM_MCI_POWER_VDD_Pos 0
  132. #define ARM_MCI_POWER_VDD_Msk (0x0FUL << ARM_MCI_POWER_VDD_Pos)
  133. #define ARM_MCI_POWER_VDD_OFF (0x01UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) turned off
  134. #define ARM_MCI_POWER_VDD_3V3 (0x02UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 3.3V
  135. #define ARM_MCI_POWER_VDD_1V8 (0x03UL << ARM_MCI_POWER_VDD_Pos) ///< VDD (VCC) = 1.8V
  136. #define ARM_MCI_POWER_VCCQ_Pos 4
  137. #define ARM_MCI_POWER_VCCQ_Msk (0x0FUL << ARM_MCI_POWER_VCCQ_Pos)
  138. #define ARM_MCI_POWER_VCCQ_OFF (0x01UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ turned off
  139. #define ARM_MCI_POWER_VCCQ_3V3 (0x02UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 3.3V
  140. #define ARM_MCI_POWER_VCCQ_1V8 (0x03UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.8V
  141. #define ARM_MCI_POWER_VCCQ_1V2 (0x04UL << ARM_MCI_POWER_VCCQ_Pos) ///< eMMC VCCQ = 1.2V
  142. /**
  143. \brief MCI Status
  144. */
  145. typedef volatile struct _ARM_MCI_STATUS {
  146. uint32_t command_active : 1; ///< Command active flag
  147. uint32_t command_timeout : 1; ///< Command timeout flag (cleared on start of next command)
  148. uint32_t command_error : 1; ///< Command error flag (cleared on start of next command)
  149. uint32_t transfer_active : 1; ///< Transfer active flag
  150. uint32_t transfer_timeout : 1; ///< Transfer timeout flag (cleared on start of next command)
  151. uint32_t transfer_error : 1; ///< Transfer error flag (cleared on start of next command)
  152. uint32_t sdio_interrupt : 1; ///< SD I/O Interrupt flag (cleared on start of monitoring)
  153. uint32_t ccs : 1; ///< CCS flag (cleared on start of next command)
  154. uint32_t reserved : 24;
  155. } ARM_MCI_STATUS;
  156. /****** MCI Card Event *****/
  157. #define ARM_MCI_EVENT_CARD_INSERTED (1UL << 0) ///< Memory Card inserted
  158. #define ARM_MCI_EVENT_CARD_REMOVED (1UL << 1) ///< Memory Card removed
  159. #define ARM_MCI_EVENT_COMMAND_COMPLETE (1UL << 2) ///< Command completed
  160. #define ARM_MCI_EVENT_COMMAND_TIMEOUT (1UL << 3) ///< Command timeout
  161. #define ARM_MCI_EVENT_COMMAND_ERROR (1UL << 4) ///< Command response error (CRC error or invalid response)
  162. #define ARM_MCI_EVENT_TRANSFER_COMPLETE (1UL << 5) ///< Data transfer completed
  163. #define ARM_MCI_EVENT_TRANSFER_TIMEOUT (1UL << 6) ///< Data transfer timeout
  164. #define ARM_MCI_EVENT_TRANSFER_ERROR (1UL << 7) ///< Data transfer CRC failed
  165. #define ARM_MCI_EVENT_SDIO_INTERRUPT (1UL << 8) ///< SD I/O Interrupt
  166. #define ARM_MCI_EVENT_CCS (1UL << 9) ///< Command Completion Signal (CCS)
  167. #define ARM_MCI_EVENT_CCS_TIMEOUT (1UL << 10) ///< Command Completion Signal (CCS) Timeout
  168. // Function documentation
  169. /**
  170. \fn ARM_DRIVER_VERSION ARM_MCI_GetVersion (void)
  171. \brief Get driver version.
  172. \return \ref ARM_DRIVER_VERSION
  173. */
  174. /**
  175. \fn ARM_MCI_CAPABILITIES ARM_MCI_GetCapabilities (void)
  176. \brief Get driver capabilities.
  177. \return \ref ARM_MCI_CAPABILITIES
  178. */
  179. /**
  180. \fn int32_t ARM_MCI_Initialize (ARM_MCI_SignalEvent_t cb_event)
  181. \brief Initialize the Memory Card Interface
  182. \param[in] cb_event Pointer to \ref ARM_MCI_SignalEvent
  183. \return \ref execution_status
  184. */
  185. /**
  186. \fn int32_t ARM_MCI_Uninitialize (void)
  187. \brief De-initialize Memory Card Interface.
  188. \return \ref execution_status
  189. */
  190. /**
  191. \fn int32_t ARM_MCI_PowerControl (ARM_POWER_STATE state)
  192. \brief Control Memory Card Interface Power.
  193. \param[in] state Power state \ref ARM_POWER_STATE
  194. \return \ref execution_status
  195. */
  196. /**
  197. \fn int32_t ARM_MCI_CardPower (uint32_t voltage)
  198. \brief Set Memory Card Power supply voltage.
  199. \param[in] voltage Memory Card Power supply voltage
  200. \return \ref execution_status
  201. */
  202. /**
  203. \fn int32_t ARM_MCI_ReadCD (void)
  204. \brief Read Card Detect (CD) state.
  205. \return 1:card detected, 0:card not detected, or error
  206. */
  207. /**
  208. \fn int32_t ARM_MCI_ReadWP (void)
  209. \brief Read Write Protect (WP) state.
  210. \return 1:write protected, 0:not write protected, or error
  211. */
  212. /**
  213. \fn int32_t ARM_MCI_SendCommand (uint32_t cmd,
  214. uint32_t arg,
  215. uint32_t flags,
  216. uint32_t *response)
  217. \brief Send Command to card and get the response.
  218. \param[in] cmd Memory Card command
  219. \param[in] arg Command argument
  220. \param[in] flags Command flags
  221. \param[out] response Pointer to buffer for response
  222. \return \ref execution_status
  223. */
  224. /**
  225. \fn int32_t ARM_MCI_SetupTransfer (uint8_t *data,
  226. uint32_t block_count,
  227. uint32_t block_size,
  228. uint32_t mode)
  229. \brief Setup read or write transfer operation.
  230. \param[in,out] data Pointer to data block(s) to be written or read
  231. \param[in] block_count Number of blocks
  232. \param[in] block_size Size of a block in bytes
  233. \param[in] mode Transfer mode
  234. \return \ref execution_status
  235. */
  236. /**
  237. \fn int32_t ARM_MCI_AbortTransfer (void)
  238. \brief Abort current read/write data transfer.
  239. \return \ref execution_status
  240. */
  241. /**
  242. \fn int32_t ARM_MCI_Control (uint32_t control, uint32_t arg)
  243. \brief Control MCI Interface.
  244. \param[in] control Operation
  245. \param[in] arg Argument of operation (optional)
  246. \return \ref execution_status
  247. */
  248. /**
  249. \fn ARM_MCI_STATUS ARM_MCI_GetStatus (void)
  250. \brief Get MCI status.
  251. \return MCI status \ref ARM_MCI_STATUS
  252. */
  253. /**
  254. \fn void ARM_MCI_SignalEvent (uint32_t event)
  255. \brief Callback function that signals a MCI Card Event.
  256. \param[in] event \ref mci_event_gr
  257. \return none
  258. */
  259. typedef void (*ARM_MCI_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_MCI_SignalEvent : Signal MCI Card Event.
  260. /**
  261. \brief MCI Driver Capabilities.
  262. */
  263. typedef struct _ARM_MCI_CAPABILITIES {
  264. uint32_t cd_state : 1; ///< Card Detect State available
  265. uint32_t cd_event : 1; ///< Signal Card Detect change event
  266. uint32_t wp_state : 1; ///< Write Protect State available
  267. uint32_t vdd : 1; ///< Supports VDD Card Power Supply Control
  268. uint32_t vdd_1v8 : 1; ///< Supports 1.8 VDD Card Power Supply
  269. uint32_t vccq : 1; ///< Supports VCCQ Card Power Supply Control (eMMC)
  270. uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ Card Power Supply (eMMC)
  271. uint32_t vccq_1v2 : 1; ///< Supports 1.2 VCCQ Card Power Supply (eMMC)
  272. uint32_t data_width_4 : 1; ///< Supports 4-bit data
  273. uint32_t data_width_8 : 1; ///< Supports 8-bit data
  274. uint32_t data_width_4_ddr : 1; ///< Supports 4-bit data, DDR (Dual Data Rate) - MMC only
  275. uint32_t data_width_8_ddr : 1; ///< Supports 8-bit data, DDR (Dual Data Rate) - MMC only
  276. uint32_t high_speed : 1; ///< Supports SD/MMC High Speed Mode
  277. uint32_t uhs_signaling : 1; ///< Supports SD UHS-I (Ultra High Speed) 1.8V signaling
  278. uint32_t uhs_tuning : 1; ///< Supports SD UHS-I tuning
  279. uint32_t uhs_sdr50 : 1; ///< Supports SD UHS-I SDR50 (Single Data Rate) up to 50MB/s
  280. uint32_t uhs_sdr104 : 1; ///< Supports SD UHS-I SDR104 (Single Data Rate) up to 104MB/s
  281. uint32_t uhs_ddr50 : 1; ///< Supports SD UHS-I DDR50 (Dual Data Rate) up to 50MB/s
  282. uint32_t uhs_driver_type_a : 1; ///< Supports SD UHS-I Driver Type A
  283. uint32_t uhs_driver_type_c : 1; ///< Supports SD UHS-I Driver Type C
  284. uint32_t uhs_driver_type_d : 1; ///< Supports SD UHS-I Driver Type D
  285. uint32_t sdio_interrupt : 1; ///< Supports SD I/O Interrupt
  286. uint32_t read_wait : 1; ///< Supports Read Wait (SD I/O)
  287. uint32_t suspend_resume : 1; ///< Supports Suspend/Resume (SD I/O)
  288. uint32_t mmc_interrupt : 1; ///< Supports MMC Interrupt
  289. uint32_t mmc_boot : 1; ///< Supports MMC Boot
  290. uint32_t rst_n : 1; ///< Supports RST_n Pin Control (eMMC)
  291. uint32_t ccs : 1; ///< Supports Command Completion Signal (CCS) for CE-ATA
  292. uint32_t ccs_timeout : 1; ///< Supports Command Completion Signal (CCS) timeout for CE-ATA
  293. uint32_t reserved : 3; ///< Reserved (must be zero)
  294. } ARM_MCI_CAPABILITIES;
  295. /**
  296. \brief Access structure of the MCI Driver.
  297. */
  298. typedef struct _ARM_DRIVER_MCI {
  299. ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_MCI_GetVersion : Get driver version.
  300. ARM_MCI_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_MCI_GetCapabilities : Get driver capabilities.
  301. int32_t (*Initialize) (ARM_MCI_SignalEvent_t cb_event); ///< Pointer to \ref ARM_MCI_Initialize : Initialize MCI Interface.
  302. int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_MCI_Uninitialize : De-initialize MCI Interface.
  303. int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_MCI_PowerControl : Control MCI Interface Power.
  304. int32_t (*CardPower) (uint32_t voltage); ///< Pointer to \ref ARM_MCI_CardPower : Set card power supply voltage.
  305. int32_t (*ReadCD) (void); ///< Pointer to \ref ARM_MCI_ReadCD : Read Card Detect (CD) state.
  306. int32_t (*ReadWP) (void); ///< Pointer to \ref ARM_MCI_ReadWP : Read Write Protect (WP) state.
  307. int32_t (*SendCommand) (uint32_t cmd,
  308. uint32_t arg,
  309. uint32_t flags,
  310. uint32_t *response); ///< Pointer to \ref ARM_MCI_SendCommand : Send Command to card and get the response.
  311. int32_t (*SetupTransfer) (uint8_t *data,
  312. uint32_t block_count,
  313. uint32_t block_size,
  314. uint32_t mode); ///< Pointer to \ref ARM_MCI_SetupTransfer : Setup data transfer operation.
  315. int32_t (*AbortTransfer) (void); ///< Pointer to \ref ARM_MCI_AbortTransfer : Abort current data transfer.
  316. int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_MCI_Control : Control MCI Interface.
  317. ARM_MCI_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_MCI_GetStatus : Get MCI status.
  318. } const ARM_DRIVER_MCI;
  319. #ifdef __cplusplus
  320. }
  321. #endif
  322. #endif /* DRIVER_MCI_H_ */