Driver_USART.h 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341
  1. /*
  2. * Copyright (c) 2013-2017 ARM Limited. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Licensed under the Apache License, Version 2.0 (the License); you may
  7. * not use this file except in compliance with the License.
  8. * You may obtain a copy of the License at
  9. *
  10. * www.apache.org/licenses/LICENSE-2.0
  11. *
  12. * Unless required by applicable law or agreed to in writing, software
  13. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  14. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  15. * See the License for the specific language governing permissions and
  16. * limitations under the License.
  17. *
  18. * $Date: 2. Feb 2017
  19. * $Revision: V2.3
  20. *
  21. * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter)
  22. * Driver definitions
  23. */
  24. /* History:
  25. * Version 2.3
  26. * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile
  27. * Version 2.2
  28. * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions
  29. * Version 2.1
  30. * Removed optional argument parameter from Signal Event
  31. * Version 2.0
  32. * New simplified driver:
  33. * complexity moved to upper layer (especially data handling)
  34. * more unified API for different communication interfaces
  35. * renamed driver UART -> USART (Asynchronous & Synchronous)
  36. * Added modes:
  37. * Synchronous
  38. * Single-wire
  39. * IrDA
  40. * Smart Card
  41. * Changed prefix ARM_DRV -> ARM_DRIVER
  42. * Version 1.10
  43. * Namespace prefix ARM_ added
  44. * Version 1.01
  45. * Added events:
  46. * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT
  47. * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD
  48. * Added functions: SetTxThreshold, SetRxThreshold
  49. * Added "rx_timeout_event" to capabilities
  50. * Version 1.00
  51. * Initial release
  52. */
  53. #ifndef DRIVER_USART_H_
  54. #define DRIVER_USART_H_
  55. #ifdef __cplusplus
  56. extern "C"
  57. {
  58. #endif
  59. #include "Driver_Common.h"
  60. #define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */
  61. /****** USART Control Codes *****/
  62. #define ARM_USART_CONTROL_Pos 0
  63. #define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos)
  64. /*----- USART Control Codes: Mode -----*/
  65. #define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate
  66. #define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate
  67. #define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal)
  68. #define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate
  69. #define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate
  70. #define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate
  71. /*----- USART Control Codes: Mode Parameters: Data Bits -----*/
  72. #define ARM_USART_DATA_BITS_Pos 8
  73. #define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos)
  74. #define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits
  75. #define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit
  76. #define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits
  77. #define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default)
  78. #define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits
  79. /*----- USART Control Codes: Mode Parameters: Parity -----*/
  80. #define ARM_USART_PARITY_Pos 12
  81. #define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos)
  82. #define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default)
  83. #define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity
  84. #define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity
  85. /*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
  86. #define ARM_USART_STOP_BITS_Pos 14
  87. #define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos)
  88. #define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default)
  89. #define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits
  90. #define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits
  91. #define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits
  92. /*----- USART Control Codes: Mode Parameters: Flow Control -----*/
  93. #define ARM_USART_FLOW_CONTROL_Pos 16
  94. #define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos)
  95. #define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default)
  96. #define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control
  97. #define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control
  98. #define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control
  99. /*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
  100. #define ARM_USART_CPOL_Pos 18
  101. #define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos)
  102. #define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default)
  103. #define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1
  104. /*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
  105. #define ARM_USART_CPHA_Pos 19
  106. #define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos)
  107. #define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default)
  108. #define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1
  109. /*----- USART Control Codes: Miscellaneous Controls -----*/
  110. #define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value
  111. #define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period
  112. #define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods
  113. #define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated
  114. #define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled
  115. #define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled
  116. #define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled
  117. #define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled
  118. #define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send
  119. #define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive
  120. #define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer
  121. /****** USART specific error codes *****/
  122. #define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported
  123. #define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported
  124. #define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported
  125. #define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported
  126. #define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported
  127. #define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported
  128. #define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported
  129. #define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported
  130. /**
  131. \brief USART Status
  132. */
  133. typedef volatile struct _ARM_USART_STATUS {
  134. uint32_t tx_busy : 1; ///< Transmitter busy flag
  135. uint32_t rx_busy : 1; ///< Receiver busy flag
  136. uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation)
  137. uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation)
  138. uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation)
  139. uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation)
  140. uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation)
  141. uint32_t reserved : 25;
  142. } ARM_USART_STATUS;
  143. /**
  144. \brief USART Modem Control
  145. */
  146. typedef enum _ARM_USART_MODEM_CONTROL {
  147. ARM_USART_RTS_CLEAR, ///< Deactivate RTS
  148. ARM_USART_RTS_SET, ///< Activate RTS
  149. ARM_USART_DTR_CLEAR, ///< Deactivate DTR
  150. ARM_USART_DTR_SET ///< Activate DTR
  151. } ARM_USART_MODEM_CONTROL;
  152. /**
  153. \brief USART Modem Status
  154. */
  155. typedef volatile struct _ARM_USART_MODEM_STATUS {
  156. uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive
  157. uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive
  158. uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive
  159. uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive
  160. uint32_t reserved : 28;
  161. } ARM_USART_MODEM_STATUS;
  162. /****** USART Event *****/
  163. #define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data
  164. #define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed
  165. #define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed
  166. #define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional)
  167. #define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave)
  168. #define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow
  169. #define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional)
  170. #define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive
  171. #define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive
  172. #define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive
  173. #define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional)
  174. #define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional)
  175. #define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional)
  176. #define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional)
  177. // Function documentation
  178. /**
  179. \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void)
  180. \brief Get driver version.
  181. \return \ref ARM_DRIVER_VERSION
  182. \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void)
  183. \brief Get driver capabilities
  184. \return \ref ARM_USART_CAPABILITIES
  185. \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event)
  186. \brief Initialize USART Interface.
  187. \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent
  188. \return \ref execution_status
  189. \fn int32_t ARM_USART_Uninitialize (void)
  190. \brief De-initialize USART Interface.
  191. \return \ref execution_status
  192. \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state)
  193. \brief Control USART Interface Power.
  194. \param[in] state Power state
  195. \return \ref execution_status
  196. \fn int32_t ARM_USART_Send (const void *data, uint32_t num)
  197. \brief Start sending data to USART transmitter.
  198. \param[in] data Pointer to buffer with data to send to USART transmitter
  199. \param[in] num Number of data items to send
  200. \return \ref execution_status
  201. \fn int32_t ARM_USART_Receive (void *data, uint32_t num)
  202. \brief Start receiving data from USART receiver.
  203. \param[out] data Pointer to buffer for data to receive from USART receiver
  204. \param[in] num Number of data items to receive
  205. \return \ref execution_status
  206. \fn int32_t ARM_USART_Transfer (const void *data_out,
  207. void *data_in,
  208. uint32_t num)
  209. \brief Start sending/receiving data to/from USART transmitter/receiver.
  210. \param[in] data_out Pointer to buffer with data to send to USART transmitter
  211. \param[out] data_in Pointer to buffer for data to receive from USART receiver
  212. \param[in] num Number of data items to transfer
  213. \return \ref execution_status
  214. \fn uint32_t ARM_USART_GetTxCount (void)
  215. \brief Get transmitted data count.
  216. \return number of data items transmitted
  217. \fn uint32_t ARM_USART_GetRxCount (void)
  218. \brief Get received data count.
  219. \return number of data items received
  220. \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg)
  221. \brief Control USART Interface.
  222. \param[in] control Operation
  223. \param[in] arg Argument of operation (optional)
  224. \return common \ref execution_status and driver specific \ref usart_execution_status
  225. \fn ARM_USART_STATUS ARM_USART_GetStatus (void)
  226. \brief Get USART status.
  227. \return USART status \ref ARM_USART_STATUS
  228. \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control)
  229. \brief Set USART Modem Control line state.
  230. \param[in] control \ref ARM_USART_MODEM_CONTROL
  231. \return \ref execution_status
  232. \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void)
  233. \brief Get USART Modem Status lines state.
  234. \return modem status \ref ARM_USART_MODEM_STATUS
  235. \fn void ARM_USART_SignalEvent (uint32_t event)
  236. \brief Signal USART Events.
  237. \param[in] event \ref USART_events notification mask
  238. \return none
  239. */
  240. typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event.
  241. /**
  242. \brief USART Device Driver Capabilities.
  243. */
  244. typedef struct _ARM_USART_CAPABILITIES {
  245. uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode
  246. uint32_t synchronous_master : 1; ///< supports Synchronous Master mode
  247. uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode
  248. uint32_t single_wire : 1; ///< supports UART Single-wire mode
  249. uint32_t irda : 1; ///< supports UART IrDA mode
  250. uint32_t smart_card : 1; ///< supports UART Smart Card mode
  251. uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available
  252. uint32_t flow_control_rts : 1; ///< RTS Flow Control available
  253. uint32_t flow_control_cts : 1; ///< CTS Flow Control available
  254. uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE
  255. uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT
  256. uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available
  257. uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available
  258. uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available
  259. uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available
  260. uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available
  261. uint32_t ri : 1; ///< RI Line: 0=not available, 1=available
  262. uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS
  263. uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR
  264. uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD
  265. uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI
  266. uint32_t reserved : 11; ///< Reserved (must be zero)
  267. } ARM_USART_CAPABILITIES;
  268. /**
  269. \brief Access structure of the USART Driver.
  270. */
  271. typedef struct _ARM_DRIVER_USART {
  272. ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version.
  273. ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities.
  274. int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface.
  275. int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface.
  276. int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power.
  277. int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter.
  278. int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver.
  279. int32_t (*Transfer) (const void *data_out,
  280. void *data_in,
  281. uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART.
  282. uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count.
  283. uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count.
  284. int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface.
  285. ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status.
  286. int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state.
  287. ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state.
  288. } const ARM_DRIVER_USART;
  289. #ifdef __cplusplus
  290. }
  291. #endif
  292. #endif /* DRIVER_USART_H_ */