usb_hc_ehci.c 44 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usb_hc_ehci.h"
  7. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  8. #include "usb_hc_ohci.h"
  9. #endif
  10. #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
  11. #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
  12. #define EHCI_TUNE_RL_TT 0
  13. #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
  14. #define EHCI_TUNE_MULT_TT 1
  15. struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS];
  16. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM];
  17. /* The head of the asynchronous queue */
  18. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS];
  19. /* The head of the periodic queue */
  20. USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS];
  21. /* The frame list */
  22. USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096)));
  23. static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus)
  24. {
  25. struct ehci_qh_hw *qh;
  26. struct ehci_qtd_hw *qtd;
  27. size_t flags;
  28. flags = usb_osal_enter_critical_section();
  29. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  30. if (!g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i]) {
  31. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = true;
  32. usb_osal_leave_critical_section(flags);
  33. qh = &ehci_qh_pool[bus->hcd.hcd_id][i];
  34. memset(&qh->hw, 0, sizeof(struct ehci_qh));
  35. qh->hw.hlp = QTD_LIST_END;
  36. qh->hw.overlay.next_qtd = QTD_LIST_END;
  37. qh->hw.overlay.alt_next_qtd = QTD_LIST_END;
  38. qh->urb = NULL;
  39. for (uint32_t j = 0; j < CONFIG_USB_EHCI_QTD_NUM; j++) {
  40. qtd = &qh->qtd_pool[j];
  41. qtd->hw.next_qtd = QTD_LIST_END;
  42. qtd->hw.alt_next_qtd = QTD_LIST_END;
  43. qtd->hw.token = QTD_TOKEN_STATUS_HALTED;
  44. qtd->urb = NULL;
  45. }
  46. return qh;
  47. }
  48. }
  49. usb_osal_leave_critical_section(flags);
  50. return NULL;
  51. }
  52. static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh)
  53. {
  54. size_t flags;
  55. for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) {
  56. if (&ehci_qh_pool[bus->hcd.hcd_id][i] == qh) {
  57. flags = usb_osal_enter_critical_section();
  58. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = false;
  59. usb_osal_leave_critical_section(flags);
  60. qh->urb = NULL;
  61. return;
  62. }
  63. }
  64. }
  65. #ifdef CONFIG_USB_DCACHE_ENABLE
  66. static inline void usb_ehci_qh_qtd_flush(struct ehci_qh_hw *qh)
  67. {
  68. struct ehci_qtd_hw *qtd;
  69. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  70. while (qtd) {
  71. usb_dcache_clean((uintptr_t)&qtd->hw, USB_ALIGN_UP(SIZEOF_EHCI_QTD, CONFIG_USB_EHCI_ALIGN_SIZE));
  72. if (!qtd->dir_in) {
  73. usb_dcache_clean(qtd->bufaddr, USB_ALIGN_UP(qtd->length, CONFIG_USB_ALIGN_SIZE));
  74. }
  75. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  76. }
  77. usb_dcache_clean((uintptr_t)&qh->hw, USB_ALIGN_UP(SIZEOF_EHCI_QH, CONFIG_USB_EHCI_ALIGN_SIZE));
  78. }
  79. #else
  80. #define usb_ehci_qh_qtd_flush(qh)
  81. #endif
  82. static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  83. {
  84. n->hw.hlp = head->hw.hlp;
  85. usb_ehci_qh_qtd_flush(n);
  86. head->hw.hlp = QH_HLP_QH(n);
  87. usb_dcache_clean((uintptr_t)&head->hw, USB_ALIGN_UP(SIZEOF_EHCI_QH, CONFIG_USB_EHCI_ALIGN_SIZE));
  88. }
  89. static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n)
  90. {
  91. struct ehci_qh_hw *tmp = head;
  92. while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) {
  93. tmp = EHCI_ADDR2QH(tmp->hw.hlp);
  94. }
  95. if (tmp) {
  96. tmp->hw.hlp = n->hw.hlp;
  97. usb_dcache_clean((uintptr_t)&tmp->hw, USB_ALIGN_UP(SIZEOF_EHCI_QH, CONFIG_USB_EHCI_ALIGN_SIZE));
  98. }
  99. }
  100. static int ehci_caculate_smask(int binterval)
  101. {
  102. int order, interval;
  103. interval = 1;
  104. while (binterval > 1) {
  105. interval *= 2;
  106. binterval--;
  107. }
  108. if (interval < 2) /* interval 1 */
  109. return 0xFF;
  110. if (interval < 4) /* interval 2 */
  111. return 0x55;
  112. if (interval < 8) /* interval 4 */
  113. return 0x22;
  114. for (order = 0; (interval > 1); order++) {
  115. interval >>= 1;
  116. }
  117. return (0x1 << (order % 8));
  118. }
  119. static void ehci_qh_fill(struct ehci_qh_hw *qh,
  120. uint8_t dev_addr,
  121. uint8_t ep_addr,
  122. uint8_t ep_type,
  123. uint16_t ep_mps,
  124. uint8_t ep_mult,
  125. uint8_t ep_interval,
  126. uint8_t speed,
  127. uint8_t hubaddr,
  128. uint8_t hubport)
  129. {
  130. uint32_t epchar = 0;
  131. uint32_t epcap = 0;
  132. /* QH endpoint characteristics:
  133. *
  134. * FIELD DESCRIPTION
  135. * -------- -------------------------------
  136. * DEVADDR Device address
  137. * I Inactivate on Next Transaction
  138. * ENDPT Endpoint number
  139. * EPS Endpoint speed
  140. * DTC Data toggle control
  141. * MAXPKT Max packet size
  142. * C Control endpoint
  143. * RL NAK count reloaded
  144. */
  145. /* QH endpoint capabilities
  146. *
  147. * FIELD DESCRIPTION
  148. * -------- -------------------------------
  149. * SSMASK Interrupt Schedule Mask
  150. * SCMASK Split Completion Mask
  151. * HUBADDR Hub Address
  152. * PORT Port number
  153. * MULT High band width multiplier
  154. */
  155. epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT);
  156. epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT);
  157. epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT);
  158. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  159. epchar |= QH_EPCHAR_DTC; /* toggle from qtd */
  160. }
  161. switch (speed) {
  162. case USB_SPEED_LOW:
  163. epchar |= QH_EPCHAR_EPS_LOW;
  164. __attribute__((fallthrough));
  165. case USB_SPEED_FULL:
  166. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  167. epchar |= QH_EPCHAR_C; /* for TT */
  168. }
  169. if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) {
  170. epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT);
  171. }
  172. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT);
  173. epcap |= QH_EPCAPS_HUBADDR(hubaddr);
  174. epcap |= QH_EPCAPS_PORT(hubport);
  175. if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) {
  176. epcap |= QH_EPCAPS_SSMASK(2);
  177. epcap |= QH_EPCAPS_SCMASK(0x78);
  178. }
  179. break;
  180. case USB_SPEED_HIGH:
  181. epchar |= QH_EPCHAR_EPS_HIGH;
  182. if (ep_type == USB_ENDPOINT_TYPE_CONTROL) {
  183. epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT);
  184. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  185. } else if (ep_type == USB_ENDPOINT_TYPE_BULK) {
  186. epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS);
  187. } else {
  188. /* only for interrupt ep */
  189. epcap |= QH_EPCAPS_MULT(ep_mult);
  190. epcap |= ehci_caculate_smask(ep_interval);
  191. }
  192. break;
  193. default:
  194. break;
  195. }
  196. qh->hw.epchar = epchar;
  197. qh->hw.epcap = epcap;
  198. }
  199. static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen)
  200. {
  201. uint32_t rest;
  202. qtd->hw.bpl[0] = bufaddr;
  203. rest = 0x1000 - (bufaddr & 0xfff);
  204. if (buflen < rest) {
  205. rest = buflen;
  206. } else {
  207. bufaddr += 0x1000;
  208. bufaddr &= ~0x0fff;
  209. for (int i = 1; rest < buflen && i < 5; i++) {
  210. qtd->hw.bpl[i] = bufaddr;
  211. bufaddr += 0x1000;
  212. if ((rest + 0x1000) < buflen) {
  213. rest += 0x1000;
  214. } else {
  215. rest = buflen;
  216. }
  217. }
  218. }
  219. }
  220. static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token)
  221. {
  222. /* qTD token
  223. *
  224. * FIELD DESCRIPTION
  225. * -------- -------------------------------
  226. * STATUS Status
  227. * PID PID Code
  228. * CERR Error Counter
  229. * CPAGE Current Page
  230. * IOC Interrupt on complete
  231. * NBYTES Total Bytes to Transfer
  232. * TOGGLE Data Toggle
  233. */
  234. qtd->hw.token = token;
  235. ehci_qtd_bpl_fill(qtd, usb_phyaddr2ramaddr(bufaddr), buflen);
  236. qtd->dir_in = ((token & QTD_TOKEN_PID_MASK) == QTD_TOKEN_PID_IN) ? true : false;
  237. qtd->bufaddr = bufaddr;
  238. qtd->length = buflen;
  239. }
  240. static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen)
  241. {
  242. struct ehci_qh_hw *qh = NULL;
  243. struct ehci_qtd_hw *qtd_setup = NULL;
  244. struct ehci_qtd_hw *qtd_data = NULL;
  245. struct ehci_qtd_hw *qtd_status = NULL;
  246. uint32_t token;
  247. size_t flags;
  248. qh = ehci_qh_alloc(bus);
  249. if (qh == NULL) {
  250. return NULL;
  251. }
  252. qtd_setup = &qh->qtd_pool[0];
  253. qtd_data = &qh->qtd_pool[1];
  254. qtd_status = &qh->qtd_pool[2];
  255. ehci_qh_fill(qh,
  256. urb->hport->dev_addr,
  257. urb->ep->bEndpointAddress,
  258. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  259. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  260. 0,
  261. 0,
  262. urb->hport->speed,
  263. urb->hport->parent->hub_addr,
  264. urb->hport->port);
  265. /* fill setup qtd */
  266. token = QTD_TOKEN_STATUS_ACTIVE |
  267. QTD_TOKEN_PID_SETUP |
  268. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  269. ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT);
  270. ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token);
  271. qtd_setup->urb = urb;
  272. /* fill data qtd */
  273. if (setup->wLength > 0) {
  274. if ((setup->bmRequestType & 0x80) == 0x80) {
  275. token = QTD_TOKEN_PID_IN;
  276. } else {
  277. token = QTD_TOKEN_PID_OUT;
  278. }
  279. token |= QTD_TOKEN_STATUS_ACTIVE |
  280. QTD_TOKEN_PID_OUT |
  281. QTD_TOKEN_TOGGLE |
  282. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  283. ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT);
  284. ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token);
  285. qtd_data->urb = urb;
  286. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data);
  287. qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  288. } else {
  289. qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status);
  290. }
  291. /* fill status qtd */
  292. if ((setup->bmRequestType & 0x80) == 0x80) {
  293. token = QTD_TOKEN_PID_OUT;
  294. } else {
  295. token = QTD_TOKEN_PID_IN;
  296. }
  297. token |= QTD_TOKEN_STATUS_ACTIVE |
  298. QTD_TOKEN_TOGGLE |
  299. QTD_TOKEN_IOC |
  300. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  301. ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT);
  302. ehci_qtd_fill(qtd_status, 0, 0, token);
  303. qtd_status->urb = urb;
  304. qtd_status->hw.next_qtd = QTD_LIST_END;
  305. /* update qh first qtd */
  306. qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup);
  307. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup);
  308. /* record qh first qtd */
  309. qh->first_qtd = EHCI_PTR2ADDR(qtd_setup);
  310. flags = usb_osal_enter_critical_section();
  311. qh->urb = urb;
  312. urb->hcpriv = qh;
  313. /* add qh into async list */
  314. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  315. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  316. usb_osal_leave_critical_section(flags);
  317. return qh;
  318. }
  319. static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  320. {
  321. struct ehci_qh_hw *qh = NULL;
  322. struct ehci_qtd_hw *qtd = NULL;
  323. struct ehci_qtd_hw *first_qtd = NULL;
  324. struct ehci_qtd_hw *prev_qtd = NULL;
  325. uint32_t qtd_num = 0;
  326. uint32_t xfer_len = 0;
  327. uint32_t token;
  328. size_t flags;
  329. qh = ehci_qh_alloc(bus);
  330. if (qh == NULL) {
  331. return NULL;
  332. }
  333. ehci_qh_fill(qh,
  334. urb->hport->dev_addr,
  335. urb->ep->bEndpointAddress,
  336. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  337. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  338. 0,
  339. 0,
  340. urb->hport->speed,
  341. urb->hport->parent->hub_addr,
  342. urb->hport->port);
  343. while (1) {
  344. qtd = &qh->qtd_pool[qtd_num];
  345. if (buflen > 0x4000) {
  346. xfer_len = 0x4000;
  347. buflen -= 0x4000;
  348. } else {
  349. xfer_len = buflen;
  350. buflen = 0;
  351. }
  352. if (urb->ep->bEndpointAddress & 0x80) {
  353. token = QTD_TOKEN_PID_IN;
  354. } else {
  355. token = QTD_TOKEN_PID_OUT;
  356. }
  357. token |= QTD_TOKEN_STATUS_ACTIVE |
  358. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  359. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  360. if (buflen == 0) {
  361. token |= QTD_TOKEN_IOC;
  362. }
  363. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  364. qtd->urb = urb;
  365. qtd->hw.next_qtd = QTD_LIST_END;
  366. buffer += xfer_len;
  367. if (prev_qtd) {
  368. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  369. } else {
  370. first_qtd = qtd;
  371. }
  372. prev_qtd = qtd;
  373. if (buflen == 0) {
  374. break;
  375. }
  376. qtd_num++;
  377. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  378. return NULL;
  379. }
  380. }
  381. /* update qh first qtd */
  382. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  383. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  384. /* update data toggle */
  385. if (urb->data_toggle) {
  386. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  387. } else {
  388. qh->hw.overlay.token = 0;
  389. }
  390. /* record qh first qtd */
  391. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  392. flags = usb_osal_enter_critical_section();
  393. qh->urb = urb;
  394. urb->hcpriv = qh;
  395. /* add qh into async list */
  396. ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh);
  397. EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN;
  398. usb_osal_leave_critical_section(flags);
  399. return qh;
  400. }
  401. static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen)
  402. {
  403. struct ehci_qh_hw *qh = NULL;
  404. struct ehci_qtd_hw *qtd = NULL;
  405. struct ehci_qtd_hw *first_qtd = NULL;
  406. struct ehci_qtd_hw *prev_qtd = NULL;
  407. uint32_t qtd_num = 0;
  408. uint32_t xfer_len = 0;
  409. uint32_t token;
  410. size_t flags;
  411. qh = ehci_qh_alloc(bus);
  412. if (qh == NULL) {
  413. return NULL;
  414. }
  415. ehci_qh_fill(qh,
  416. urb->hport->dev_addr,
  417. urb->ep->bEndpointAddress,
  418. USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes),
  419. USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize),
  420. USB_GET_MULT(urb->ep->wMaxPacketSize) + 1,
  421. urb->ep->bInterval,
  422. urb->hport->speed,
  423. urb->hport->parent->hub_addr,
  424. urb->hport->port);
  425. while (1) {
  426. qtd = &qh->qtd_pool[qtd_num];
  427. if (buflen > 0x4000) {
  428. xfer_len = 0x4000;
  429. buflen -= 0x4000;
  430. } else {
  431. xfer_len = buflen;
  432. buflen = 0;
  433. }
  434. if (urb->ep->bEndpointAddress & 0x80) {
  435. token = QTD_TOKEN_PID_IN;
  436. } else {
  437. token = QTD_TOKEN_PID_OUT;
  438. }
  439. token |= QTD_TOKEN_STATUS_ACTIVE |
  440. ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) |
  441. ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT);
  442. if (buflen == 0) {
  443. token |= QTD_TOKEN_IOC;
  444. }
  445. ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token);
  446. qtd->urb = urb;
  447. qtd->hw.next_qtd = QTD_LIST_END;
  448. buffer += xfer_len;
  449. if (prev_qtd) {
  450. prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd);
  451. } else {
  452. first_qtd = qtd;
  453. }
  454. prev_qtd = qtd;
  455. if (buflen == 0) {
  456. break;
  457. }
  458. qtd_num++;
  459. if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) {
  460. return NULL;
  461. }
  462. }
  463. /* update qh first qtd */
  464. qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd);
  465. qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd);
  466. /* update data toggle */
  467. if (urb->data_toggle) {
  468. qh->hw.overlay.token = QTD_TOKEN_TOGGLE;
  469. } else {
  470. qh->hw.overlay.token = 0;
  471. }
  472. /* record qh first qtd */
  473. qh->first_qtd = EHCI_PTR2ADDR(first_qtd);
  474. flags = usb_osal_enter_critical_section();
  475. qh->urb = urb;
  476. urb->hcpriv = qh;
  477. /* add qh into periodic list */
  478. ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh);
  479. EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN;
  480. usb_osal_leave_critical_section(flags);
  481. return qh;
  482. }
  483. static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb)
  484. {
  485. struct ehci_qh_hw *qh;
  486. qh = (struct ehci_qh_hw *)urb->hcpriv;
  487. qh->urb = NULL;
  488. urb->hcpriv = NULL;
  489. qh->remove_in_iaad = 0;
  490. if (urb->timeout) {
  491. usb_osal_sem_give(qh->waitsem);
  492. } else {
  493. ehci_qh_free(bus, qh);
  494. }
  495. if (urb->complete) {
  496. if (urb->errorcode < 0) {
  497. urb->complete(urb->arg, urb->errorcode);
  498. } else {
  499. urb->complete(urb->arg, urb->actual_length);
  500. }
  501. }
  502. }
  503. static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  504. {
  505. struct ehci_qtd_hw *qtd;
  506. (void)bus;
  507. ehci_qh_remove(qhead, qh);
  508. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  509. while (qtd) {
  510. if (qtd->dir_in) {
  511. usb_dcache_invalidate(qtd->bufaddr, USB_ALIGN_UP(qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT), CONFIG_USB_ALIGN_SIZE));
  512. }
  513. qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT));
  514. qh->first_qtd = qtd->hw.next_qtd;
  515. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  516. }
  517. }
  518. static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  519. {
  520. struct usbh_urb *urb;
  521. struct ehci_qtd_hw *qtd;
  522. uint32_t token;
  523. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  524. if (qtd == NULL) {
  525. return;
  526. }
  527. while (qtd) {
  528. usb_dcache_invalidate((uintptr_t)&qtd->hw, USB_ALIGN_UP(SIZEOF_EHCI_QTD, CONFIG_USB_EHCI_ALIGN_SIZE));
  529. token = qtd->hw.token;
  530. if (token & QTD_TOKEN_STATUS_ERRORS) {
  531. break;
  532. } else if (token & QTD_TOKEN_STATUS_ACTIVE) {
  533. return;
  534. }
  535. qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd);
  536. }
  537. urb = qh->urb;
  538. if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) {
  539. if (token & QTD_TOKEN_TOGGLE) {
  540. urb->data_toggle = true;
  541. } else {
  542. urb->data_toggle = false;
  543. }
  544. urb->errorcode = 0;
  545. } else {
  546. if (token & QTD_TOKEN_STATUS_BABBLE) {
  547. urb->errorcode = -USB_ERR_BABBLE;
  548. urb->data_toggle = 0;
  549. } else if (token & QTD_TOKEN_STATUS_HALTED) {
  550. urb->errorcode = -USB_ERR_STALL;
  551. urb->data_toggle = 0;
  552. } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) {
  553. urb->errorcode = -USB_ERR_IO;
  554. }
  555. }
  556. ehci_qh_scan_qtds(bus, qhead, qh);
  557. if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  558. ehci_urb_waitup(bus, urb);
  559. } else {
  560. qh->remove_in_iaad = 1;
  561. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  562. }
  563. }
  564. static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh)
  565. {
  566. struct ehci_qtd_hw *qtd;
  567. (void)bus;
  568. ehci_qh_remove(qhead, qh);
  569. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  570. while (qtd) {
  571. qh->first_qtd = qtd->hw.next_qtd;
  572. qtd = EHCI_ADDR2QTD(qh->first_qtd);
  573. }
  574. }
  575. static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port)
  576. {
  577. volatile uint32_t timeout = 0;
  578. uint32_t regval;
  579. #if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO
  580. if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */
  581. EHCI_HCOR->portsc[port - 1] |= (1 << 29);
  582. } else {
  583. EHCI_HCOR->portsc[port - 1] &= ~(1 << 29);
  584. }
  585. #endif
  586. regval = EHCI_HCOR->portsc[port - 1];
  587. regval &= ~EHCI_PORTSC_PE;
  588. regval |= EHCI_PORTSC_RESET;
  589. EHCI_HCOR->portsc[port - 1] = regval;
  590. usb_osal_msleep(55);
  591. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET;
  592. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) {
  593. usb_osal_msleep(1);
  594. timeout++;
  595. if (timeout > 100) {
  596. return -USB_ERR_TIMEOUT;
  597. }
  598. }
  599. return 0;
  600. }
  601. __WEAK void usb_hc_low_level_init(struct usbh_bus *bus)
  602. {
  603. (void)bus;
  604. }
  605. __WEAK void usb_hc_low_level2_init(struct usbh_bus *bus)
  606. {
  607. (void)bus;
  608. }
  609. __WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus)
  610. {
  611. (void)bus;
  612. }
  613. int usb_hc_init(struct usbh_bus *bus)
  614. {
  615. struct ehci_qh_hw *qh;
  616. volatile uint32_t timeout = 0;
  617. uint32_t regval;
  618. memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd));
  619. memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM);
  620. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  621. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  622. if ((uint32_t)&qh->hw % 32) {
  623. USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n");
  624. return -USB_ERR_INVAL;
  625. }
  626. for (uint8_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) {
  627. if ((uint32_t)&qh->qtd_pool[i] % 32) {
  628. USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n");
  629. return -USB_ERR_INVAL;
  630. }
  631. }
  632. }
  633. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  634. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  635. qh->waitsem = usb_osal_sem_create(0);
  636. }
  637. memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  638. g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]);
  639. g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H;
  640. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  641. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  642. g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  643. g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  644. memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  645. memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw));
  646. g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END;
  647. g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1);
  648. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END;
  649. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END;
  650. g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED;
  651. g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END;
  652. for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) {
  653. g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]);
  654. }
  655. usb_dcache_clean((uintptr_t)&g_async_qh_head[bus->hcd.hcd_id].hw, USB_ALIGN_UP(SIZEOF_EHCI_QH, CONFIG_USB_EHCI_ALIGN_SIZE));
  656. usb_dcache_clean((uintptr_t)&g_periodic_qh_head[bus->hcd.hcd_id].hw, USB_ALIGN_UP(SIZEOF_EHCI_QH, CONFIG_USB_EHCI_ALIGN_SIZE));
  657. usb_dcache_clean((uintptr_t)g_framelist[bus->hcd.hcd_id], sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE);
  658. usb_hc_low_level_init(bus);
  659. USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion);
  660. USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams);
  661. USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams);
  662. g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false;
  663. g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;
  664. g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT;
  665. g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT;
  666. g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true;
  667. g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength;
  668. USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n",
  669. g_ehci_hcd[bus->hcd.hcd_id].ppc,
  670. g_ehci_hcd[bus->hcd.hcd_id].n_ports,
  671. g_ehci_hcd[bus->hcd.hcd_id].n_cc,
  672. g_ehci_hcd[bus->hcd.hcd_id].n_pcc);
  673. EHCI_HCOR->usbcmd &= ~EHCI_USBCMD_RUN;
  674. usb_osal_msleep(2);
  675. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  676. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) {
  677. usb_osal_msleep(1);
  678. timeout++;
  679. if (timeout > 100) {
  680. return -USB_ERR_TIMEOUT;
  681. }
  682. }
  683. usb_hc_low_level2_init(bus);
  684. EHCI_HCOR->usbintr = 0;
  685. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  686. /* Set the Current Asynchronous List Address. */
  687. EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]);
  688. /* Set the Periodic Frame List Base Address. */
  689. EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]);
  690. regval = 0;
  691. #if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024
  692. regval |= EHCI_USBCMD_FLSIZE_1024;
  693. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512
  694. regval |= EHCI_USBCMD_FLSIZE_512;
  695. #elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256
  696. regval |= EHCI_USBCMD_FLSIZE_256;
  697. #else
  698. #error Unsupported frame size list size
  699. #endif
  700. regval |= EHCI_USBCMD_ITHRE_1MF;
  701. regval |= EHCI_USBCMD_ASEN;
  702. regval |= EHCI_USBCMD_PSEN;
  703. regval |= EHCI_USBCMD_RUN;
  704. EHCI_HCOR->usbcmd = regval;
  705. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  706. EHCI_HCOR->configflag = EHCI_CONFIGFLAG;
  707. #endif
  708. /* Wait for the EHCI to run (no longer report halted) */
  709. timeout = 0;
  710. while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) {
  711. usb_osal_msleep(1);
  712. timeout++;
  713. if (timeout > 100) {
  714. return -USB_ERR_TIMEOUT;
  715. }
  716. }
  717. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  718. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  719. regval = EHCI_HCOR->portsc[port];
  720. regval |= EHCI_PORTSC_PP;
  721. regval &= ~(EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | EHCI_PORTSC_OCC);
  722. EHCI_HCOR->portsc[port] = regval;
  723. }
  724. }
  725. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  726. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  727. USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n");
  728. return -USB_ERR_INVAL;
  729. #endif
  730. }
  731. if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) {
  732. USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n");
  733. } else {
  734. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  735. USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n");
  736. ohci_init(bus);
  737. #else
  738. USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n");
  739. #endif
  740. }
  741. /* Enable EHCI interrupts. */
  742. EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA;
  743. return 0;
  744. }
  745. int usb_hc_deinit(struct usbh_bus *bus)
  746. {
  747. struct ehci_qh_hw *qh;
  748. volatile uint32_t timeout = 0;
  749. uint32_t regval;
  750. EHCI_HCOR->usbintr = 0;
  751. regval = EHCI_HCOR->usbcmd;
  752. regval &= ~EHCI_USBCMD_ASEN;
  753. regval &= ~EHCI_USBCMD_PSEN;
  754. regval &= ~EHCI_USBCMD_RUN;
  755. EHCI_HCOR->usbcmd = regval;
  756. while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS)) || ((EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) == 0)) {
  757. usb_osal_msleep(1);
  758. timeout++;
  759. if (timeout > 100) {
  760. return -USB_ERR_TIMEOUT;
  761. }
  762. }
  763. if (g_ehci_hcd[bus->hcd.hcd_id].ppc) {
  764. for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  765. regval = EHCI_HCOR->portsc[port];
  766. regval &= ~EHCI_PORTSC_PP;
  767. EHCI_HCOR->portsc[port] = regval;
  768. }
  769. }
  770. #ifdef CONFIG_USB_EHCI_CONFIGFLAG
  771. EHCI_HCOR->configflag = 0;
  772. #endif
  773. EHCI_HCOR->usbsts = EHCI_HCOR->usbsts;
  774. EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET;
  775. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  776. qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  777. usb_osal_sem_delete(qh->waitsem);
  778. }
  779. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  780. ohci_deinit(bus);
  781. #endif
  782. usb_hc_low_level_deinit(bus);
  783. return 0;
  784. }
  785. uint16_t usbh_get_frame_number(struct usbh_bus *bus)
  786. {
  787. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  788. if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) {
  789. return ohci_get_frame_number(bus);
  790. }
  791. #endif
  792. return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff);
  793. }
  794. int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf)
  795. {
  796. uint8_t nports;
  797. uint8_t port;
  798. uint32_t temp, status;
  799. nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports;
  800. port = setup->wIndex;
  801. temp = EHCI_HCOR->portsc[port - 1];
  802. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  803. if (temp & EHCI_PORTSC_OWNER) {
  804. return ohci_roothub_control(bus, setup, buf);
  805. }
  806. if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) {
  807. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  808. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  809. }
  810. USB_LOG_INFO("Switch port %u to OHCI\r\n", port);
  811. return ohci_roothub_control(bus, setup, buf);
  812. }
  813. #endif
  814. if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) {
  815. switch (setup->bRequest) {
  816. case HUB_REQUEST_CLEAR_FEATURE:
  817. switch (setup->wValue) {
  818. case HUB_FEATURE_HUB_C_LOCALPOWER:
  819. break;
  820. case HUB_FEATURE_HUB_C_OVERCURRENT:
  821. break;
  822. default:
  823. return -USB_ERR_NOTSUPP;
  824. }
  825. break;
  826. case HUB_REQUEST_SET_FEATURE:
  827. switch (setup->wValue) {
  828. case HUB_FEATURE_HUB_C_LOCALPOWER:
  829. break;
  830. case HUB_FEATURE_HUB_C_OVERCURRENT:
  831. break;
  832. default:
  833. return -USB_ERR_NOTSUPP;
  834. }
  835. break;
  836. case HUB_REQUEST_GET_DESCRIPTOR:
  837. break;
  838. case HUB_REQUEST_GET_STATUS:
  839. memset(buf, 0, 4);
  840. break;
  841. default:
  842. break;
  843. }
  844. } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) {
  845. switch (setup->bRequest) {
  846. case HUB_REQUEST_CLEAR_FEATURE:
  847. if (!port || port > nports) {
  848. return -USB_ERR_INVAL;
  849. }
  850. switch (setup->wValue) {
  851. case HUB_PORT_FEATURE_ENABLE:
  852. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE;
  853. break;
  854. case HUB_PORT_FEATURE_SUSPEND:
  855. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME;
  856. usb_osal_msleep(20);
  857. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME;
  858. while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) {
  859. }
  860. temp = EHCI_HCOR->usbcmd;
  861. temp |= EHCI_USBCMD_ASEN;
  862. temp |= EHCI_USBCMD_PSEN;
  863. temp |= EHCI_USBCMD_RUN;
  864. EHCI_HCOR->usbcmd = temp;
  865. while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) {
  866. }
  867. case HUB_PORT_FEATURE_C_SUSPEND:
  868. break;
  869. case HUB_PORT_FEATURE_POWER:
  870. EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP;
  871. break;
  872. case HUB_PORT_FEATURE_C_CONNECTION:
  873. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC;
  874. break;
  875. case HUB_PORT_FEATURE_C_ENABLE:
  876. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC;
  877. break;
  878. case HUB_PORT_FEATURE_C_OVER_CURREN:
  879. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC;
  880. break;
  881. case HUB_PORT_FEATURE_C_RESET:
  882. break;
  883. default:
  884. return -USB_ERR_NOTSUPP;
  885. }
  886. break;
  887. case HUB_REQUEST_SET_FEATURE:
  888. if (!port || port > nports) {
  889. return -USB_ERR_INVAL;
  890. }
  891. switch (setup->wValue) {
  892. case HUB_PORT_FEATURE_SUSPEND:
  893. temp = EHCI_HCOR->usbcmd;
  894. temp &= ~EHCI_USBCMD_ASEN;
  895. temp &= ~EHCI_USBCMD_PSEN;
  896. temp &= ~EHCI_USBCMD_RUN;
  897. EHCI_HCOR->usbcmd = temp;
  898. while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) {
  899. }
  900. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND;
  901. while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) {
  902. }
  903. break;
  904. case HUB_PORT_FEATURE_POWER:
  905. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP;
  906. break;
  907. case HUB_PORT_FEATURE_RESET:
  908. usbh_reset_port(bus, port);
  909. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  910. if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) {
  911. EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER;
  912. while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) {
  913. }
  914. USB_LOG_INFO("Switch port %u to OHCI\r\n", port);
  915. return -USB_ERR_NOTSUPP;
  916. }
  917. #endif
  918. break;
  919. default:
  920. return -USB_ERR_NOTSUPP;
  921. }
  922. break;
  923. case HUB_REQUEST_GET_STATUS:
  924. if (!port || port > nports) {
  925. return -USB_ERR_INVAL;
  926. }
  927. temp = EHCI_HCOR->portsc[port - 1];
  928. status = 0;
  929. if (temp & EHCI_PORTSC_CSC) {
  930. status |= (1 << HUB_PORT_FEATURE_C_CONNECTION);
  931. }
  932. if (temp & EHCI_PORTSC_PEC) {
  933. status |= (1 << HUB_PORT_FEATURE_C_ENABLE);
  934. }
  935. if (temp & EHCI_PORTSC_OCC) {
  936. status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN);
  937. }
  938. if (temp & EHCI_PORTSC_CCS) {
  939. status |= (1 << HUB_PORT_FEATURE_CONNECTION);
  940. }
  941. if (temp & EHCI_PORTSC_PE) {
  942. status |= (1 << HUB_PORT_FEATURE_ENABLE);
  943. if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) {
  944. status |= (1 << HUB_PORT_FEATURE_LOWSPEED);
  945. } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) {
  946. status |= (1 << HUB_PORT_FEATURE_HIGHSPEED);
  947. }
  948. }
  949. if (temp & EHCI_PORTSC_SUSPEND) {
  950. status |= (1 << HUB_PORT_FEATURE_SUSPEND);
  951. }
  952. if (temp & EHCI_PORTSC_OCA) {
  953. status |= (1 << HUB_PORT_FEATURE_OVERCURRENT);
  954. }
  955. if (temp & EHCI_PORTSC_RESET) {
  956. status |= (1 << HUB_PORT_FEATURE_RESET);
  957. }
  958. if (temp & EHCI_PORTSC_PP || !(EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC)) {
  959. status |= (1 << HUB_PORT_FEATURE_POWER);
  960. }
  961. memcpy(buf, &status, 4);
  962. break;
  963. default:
  964. break;
  965. }
  966. }
  967. return 0;
  968. }
  969. int usbh_submit_urb(struct usbh_urb *urb)
  970. {
  971. struct ehci_qh_hw *qh = NULL;
  972. size_t flags;
  973. int ret = 0;
  974. struct usbh_hub *hub;
  975. struct usbh_hubport *hport;
  976. struct usbh_bus *bus;
  977. if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) {
  978. return -USB_ERR_INVAL;
  979. }
  980. #ifdef CONFIG_USB_DCACHE_ENABLE
  981. if (((uintptr_t)urb->setup % CONFIG_USB_ALIGN_SIZE) || ((uintptr_t)urb->transfer_buffer % CONFIG_USB_ALIGN_SIZE)) {
  982. USB_LOG_ERR("urb buffer is not align with %d\r\n", CONFIG_USB_ALIGN_SIZE);
  983. while (1) {
  984. }
  985. }
  986. #endif
  987. bus = urb->hport->bus;
  988. /* find active hubport in roothub */
  989. hport = urb->hport;
  990. hub = urb->hport->parent;
  991. while (!hub->is_roothub) {
  992. hport = hub->parent;
  993. hub = hub->parent->parent;
  994. }
  995. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  996. if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) {
  997. return ohci_submit_urb(urb);
  998. }
  999. #endif
  1000. if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) {
  1001. return -USB_ERR_NOTCONN;
  1002. }
  1003. if (urb->errorcode == -USB_ERR_BUSY) {
  1004. return -USB_ERR_BUSY;
  1005. }
  1006. flags = usb_osal_enter_critical_section();
  1007. urb->hcpriv = NULL;
  1008. urb->errorcode = -USB_ERR_BUSY;
  1009. urb->actual_length = 0;
  1010. usb_osal_leave_critical_section(flags);
  1011. switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) {
  1012. case USB_ENDPOINT_TYPE_CONTROL:
  1013. qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length);
  1014. if (qh == NULL) {
  1015. return -USB_ERR_NOMEM;
  1016. }
  1017. break;
  1018. case USB_ENDPOINT_TYPE_BULK:
  1019. qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  1020. if (qh == NULL) {
  1021. return -USB_ERR_NOMEM;
  1022. }
  1023. break;
  1024. case USB_ENDPOINT_TYPE_INTERRUPT:
  1025. qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length);
  1026. if (qh == NULL) {
  1027. return -USB_ERR_NOMEM;
  1028. }
  1029. break;
  1030. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  1031. #ifdef CONFIG_USB_EHCI_ISO
  1032. ret = ehci_iso_urb_init(bus, urb);
  1033. #endif
  1034. break;
  1035. default:
  1036. break;
  1037. }
  1038. if (urb->timeout > 0) {
  1039. /* wait until timeout or sem give */
  1040. ret = usb_osal_sem_take(qh->waitsem, urb->timeout);
  1041. if (ret < 0) {
  1042. goto errout_timeout;
  1043. }
  1044. urb->timeout = 0;
  1045. ret = urb->errorcode;
  1046. /* we can free qh when waitsem is done */
  1047. ehci_qh_free(bus, qh);
  1048. }
  1049. return ret;
  1050. errout_timeout:
  1051. urb->timeout = 0;
  1052. usbh_kill_urb(urb);
  1053. return ret;
  1054. }
  1055. int usbh_kill_urb(struct usbh_urb *urb)
  1056. {
  1057. struct ehci_qh_hw *qh;
  1058. struct usbh_bus *bus;
  1059. size_t flags;
  1060. bool remove_in_iaad = false;
  1061. if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) {
  1062. return -USB_ERR_INVAL;
  1063. }
  1064. bus = urb->hport->bus;
  1065. #ifdef CONFIG_USB_EHCI_WITH_OHCI
  1066. if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) {
  1067. return ohci_kill_urb(urb);
  1068. }
  1069. #endif
  1070. flags = usb_osal_enter_critical_section();
  1071. EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1072. if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) {
  1073. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1074. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1075. if (qh->urb == urb) {
  1076. remove_in_iaad = true;
  1077. ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1078. }
  1079. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1080. }
  1081. } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
  1082. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1083. while (qh) {
  1084. if (qh->urb == urb) {
  1085. ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1086. }
  1087. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1088. }
  1089. } else {
  1090. #ifdef CONFIG_USB_EHCI_ISO
  1091. ehci_kill_iso_urb(bus, urb);
  1092. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1093. usb_osal_leave_critical_section(flags);
  1094. return 0;
  1095. #endif
  1096. }
  1097. EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN);
  1098. qh = (struct ehci_qh_hw *)urb->hcpriv;
  1099. urb->hcpriv = NULL;
  1100. urb->errorcode = -USB_ERR_SHUTDOWN;
  1101. qh->urb = NULL;
  1102. if (urb->timeout) {
  1103. usb_osal_sem_give(qh->waitsem);
  1104. } else {
  1105. ehci_qh_free(bus, qh);
  1106. }
  1107. if (remove_in_iaad) {
  1108. volatile uint32_t timeout = 0;
  1109. EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD;
  1110. while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) {
  1111. usb_osal_msleep(1);
  1112. timeout++;
  1113. if (timeout > 100) {
  1114. usb_osal_leave_critical_section(flags);
  1115. return -USB_ERR_TIMEOUT;
  1116. }
  1117. }
  1118. EHCI_HCOR->usbsts = EHCI_USBSTS_IAA;
  1119. }
  1120. usb_osal_leave_critical_section(flags);
  1121. return 0;
  1122. }
  1123. static void ehci_scan_async_list(struct usbh_bus *bus)
  1124. {
  1125. struct ehci_qh_hw *qh;
  1126. qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp);
  1127. while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) {
  1128. if (qh->urb) {
  1129. ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh);
  1130. }
  1131. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1132. }
  1133. }
  1134. static void ehci_scan_periodic_list(struct usbh_bus *bus)
  1135. {
  1136. struct ehci_qh_hw *qh;
  1137. qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp);
  1138. while (qh) {
  1139. if (qh->urb) {
  1140. ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh);
  1141. }
  1142. qh = EHCI_ADDR2QH(qh->hw.hlp);
  1143. }
  1144. }
  1145. void USBH_IRQHandler(uint8_t busid)
  1146. {
  1147. uint32_t usbsts;
  1148. struct usbh_bus *bus;
  1149. bus = &g_usbhost_bus[busid];
  1150. usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr;
  1151. EHCI_HCOR->usbsts = usbsts;
  1152. if (usbsts & EHCI_USBSTS_INT) {
  1153. ehci_scan_async_list(bus);
  1154. ehci_scan_periodic_list(bus);
  1155. #ifdef CONFIG_USB_EHCI_ISO
  1156. ehci_scan_isochronous_list(bus);
  1157. #endif
  1158. }
  1159. if (usbsts & EHCI_USBSTS_ERR) {
  1160. ehci_scan_async_list(bus);
  1161. ehci_scan_periodic_list(bus);
  1162. #ifdef CONFIG_USB_EHCI_ISO
  1163. ehci_scan_isochronous_list(bus);
  1164. #endif
  1165. }
  1166. if (usbsts & EHCI_USBSTS_PCD) {
  1167. for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) {
  1168. uint32_t portsc = EHCI_HCOR->portsc[port];
  1169. if (portsc & EHCI_PORTSC_CSC) {
  1170. if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) {
  1171. } else {
  1172. #if defined(CONFIG_USB_EHCI_NXP)
  1173. /* kUSB_ControllerEhci0 and kUSB_ControllerEhci1*/
  1174. extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable);
  1175. USB_EhcihostPhyDisconnectDetectCmd(2 + busid, 0);
  1176. #endif
  1177. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1178. g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] = false;
  1179. }
  1180. for (uint8_t index = 0; index < CONFIG_USB_EHCI_ISO_NUM; index++) {
  1181. g_ehci_hcd[bus->hcd.hcd_id].ehci_iso_used[index] = false;
  1182. }
  1183. }
  1184. bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1));
  1185. usbh_hub_thread_wakeup(&bus->hcd.roothub);
  1186. }
  1187. }
  1188. }
  1189. if (usbsts & EHCI_USBSTS_IAA) {
  1190. for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) {
  1191. struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index];
  1192. if (g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] && qh->remove_in_iaad) {
  1193. ehci_urb_waitup(bus, qh->urb);
  1194. }
  1195. }
  1196. }
  1197. if (usbsts & EHCI_USBSTS_FATAL) {
  1198. }
  1199. }