drv_adc.c 5.6 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-12-05 zylx first version
  9. */
  10. #include <board.h>
  11. #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
  12. #include "drv_config.h"
  13. //#define DRV_DEBUG
  14. #define LOG_TAG "drv.adc"
  15. #include <drv_log.h>
  16. static ADC_HandleTypeDef adc_config[] =
  17. {
  18. #ifdef BSP_USING_ADC1
  19. ADC1_CONFIG,
  20. #endif
  21. #ifdef BSP_USING_ADC2
  22. ADC2_CONFIG,
  23. #endif
  24. #ifdef BSP_USING_ADC3
  25. ADC3_CONFIG,
  26. #endif
  27. };
  28. struct stm32_adc
  29. {
  30. ADC_HandleTypeDef ADC_Handler;
  31. struct rt_adc_device stm32_adc_device;
  32. };
  33. static struct stm32_adc stm32_adc_obj[sizeof(adc_config) / sizeof(adc_config[0])];
  34. static rt_err_t stm32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
  35. {
  36. ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
  37. RT_ASSERT(device != RT_NULL);
  38. if (enabled)
  39. {
  40. #ifdef SOC_SERIES_STM32L4
  41. ADC_Enable(stm32_adc_handler);
  42. #else
  43. __HAL_ADC_ENABLE(stm32_adc_handler);
  44. #endif
  45. }
  46. else
  47. {
  48. #ifdef SOC_SERIES_STM32L4
  49. ADC_Disable(stm32_adc_handler);
  50. #else
  51. __HAL_ADC_DISABLE(stm32_adc_handler);
  52. #endif
  53. }
  54. return RT_EOK;
  55. }
  56. static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
  57. {
  58. rt_uint32_t stm32_channel = 0;
  59. switch (channel)
  60. {
  61. case 0:
  62. stm32_channel = ADC_CHANNEL_0;
  63. break;
  64. case 1:
  65. stm32_channel = ADC_CHANNEL_1;
  66. break;
  67. case 2:
  68. stm32_channel = ADC_CHANNEL_2;
  69. break;
  70. case 3:
  71. stm32_channel = ADC_CHANNEL_3;
  72. break;
  73. case 4:
  74. stm32_channel = ADC_CHANNEL_4;
  75. break;
  76. case 5:
  77. stm32_channel = ADC_CHANNEL_5;
  78. break;
  79. case 6:
  80. stm32_channel = ADC_CHANNEL_6;
  81. break;
  82. case 7:
  83. stm32_channel = ADC_CHANNEL_7;
  84. break;
  85. case 8:
  86. stm32_channel = ADC_CHANNEL_8;
  87. break;
  88. case 9:
  89. stm32_channel = ADC_CHANNEL_9;
  90. break;
  91. case 10:
  92. stm32_channel = ADC_CHANNEL_10;
  93. break;
  94. case 11:
  95. stm32_channel = ADC_CHANNEL_11;
  96. break;
  97. case 12:
  98. stm32_channel = ADC_CHANNEL_12;
  99. break;
  100. case 13:
  101. stm32_channel = ADC_CHANNEL_13;
  102. break;
  103. case 14:
  104. stm32_channel = ADC_CHANNEL_14;
  105. break;
  106. case 15:
  107. stm32_channel = ADC_CHANNEL_15;
  108. break;
  109. case 16:
  110. stm32_channel = ADC_CHANNEL_16;
  111. break;
  112. case 17:
  113. stm32_channel = ADC_CHANNEL_17;
  114. break;
  115. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
  116. case 18:
  117. stm32_channel = ADC_CHANNEL_18;
  118. break;
  119. #endif
  120. }
  121. return stm32_channel;
  122. }
  123. static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
  124. {
  125. ADC_ChannelConfTypeDef ADC_ChanConf;
  126. ADC_HandleTypeDef *stm32_adc_handler = device->parent.user_data;
  127. RT_ASSERT(device != RT_NULL);
  128. RT_ASSERT(value != RT_NULL);
  129. rt_memset(&ADC_ChanConf, 0, sizeof(ADC_ChanConf));
  130. #if defined(SOC_SERIES_STM32F1)
  131. if (channel <= 17)
  132. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
  133. if (channel <= 18)
  134. #endif
  135. {
  136. /* set stm32 ADC channel */
  137. ADC_ChanConf.Channel = stm32_adc_get_channel(channel);
  138. }
  139. else
  140. {
  141. #if defined(SOC_SERIES_STM32F1)
  142. LOG_E("ADC channel must be between 0 and 17.");
  143. #elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
  144. LOG_E("ADC channel must be between 0 and 18.");
  145. #endif
  146. return -RT_ERROR;
  147. }
  148. ADC_ChanConf.Rank = 1;
  149. #if defined(SOC_SERIES_STM32F1)
  150. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
  151. #elif defined(SOC_SERIES_STM32F4)
  152. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
  153. #elif defined(SOC_SERIES_STM32L4)
  154. ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
  155. #endif
  156. #if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
  157. ADC_ChanConf.Offset = 0;
  158. #endif
  159. #ifdef SOC_SERIES_STM32L4
  160. ADC_ChanConf.OffsetNumber = ADC_OFFSET_NONE;
  161. ADC_ChanConf.SingleDiff = LL_ADC_SINGLE_ENDED;
  162. #endif
  163. HAL_ADC_ConfigChannel(stm32_adc_handler, &ADC_ChanConf);
  164. /* start ADC */
  165. HAL_ADC_Start(stm32_adc_handler);
  166. /* Wait for the ADC to convert */
  167. HAL_ADC_PollForConversion(stm32_adc_handler, 10);
  168. /* get ADC value */
  169. *value = (rt_uint32_t)HAL_ADC_GetValue(stm32_adc_handler);
  170. return RT_EOK;
  171. }
  172. static const struct rt_adc_ops stm_adc_ops =
  173. {
  174. .enabled = stm32_adc_enabled,
  175. .convert = stm32_get_adc_value,
  176. };
  177. static int stm32_adc_init(void)
  178. {
  179. int result = RT_EOK;
  180. /* save adc name */
  181. char name_buf[6] = {0};
  182. int i = 0;
  183. for (i = 0; i < sizeof(adc_config) / sizeof(adc_config[0]); i++)
  184. {
  185. /* ADC init */
  186. stm32_adc_obj[i].ADC_Handler = adc_config[i];
  187. if (HAL_ADC_Init(&stm32_adc_obj[i].ADC_Handler) != HAL_OK)
  188. {
  189. LOG_E("ADC%d init failed", i + 1);
  190. result = -RT_ERROR;
  191. }
  192. else
  193. {
  194. rt_sprintf(name_buf, "adc%d", i + 1);
  195. /* register ADC device */
  196. if (rt_hw_adc_register(&stm32_adc_obj[i].stm32_adc_device, name_buf, &stm_adc_ops, &stm32_adc_obj[i].ADC_Handler) == RT_EOK)
  197. {
  198. LOG_D("ADC%d init success", i + 1);
  199. }
  200. else
  201. {
  202. LOG_E("ADC%d register failed", i + 1);
  203. result = -RT_ERROR;
  204. }
  205. }
  206. }
  207. return result;
  208. }
  209. INIT_BOARD_EXPORT(stm32_adc_init);
  210. #endif /* BSP_USING_ADC */