drv_gpio.c 8.2 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-30 yangjie The first version for LPC54114
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #include <rtdevice.h>
  13. #include "fsl_gpio.h"
  14. #include "LPC54114_cm4.h"
  15. #include "core_cm4.h"
  16. #include "fsl_inputmux.h"
  17. #include "fsl_pint.h"
  18. #include "fsl_iocon.h"
  19. #ifdef RT_USING_PIN
  20. #define get_port(x) (x / 32)
  21. #define get_pin(x) (x % 32)
  22. #define PIN_MAX_VAL 63
  23. #define IRQ_MAX_VAL 8
  24. struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
  25. {
  26. {-1, 0, RT_NULL, RT_NULL},
  27. {-1, 0, RT_NULL, RT_NULL},
  28. {-1, 0, RT_NULL, RT_NULL},
  29. {-1, 0, RT_NULL, RT_NULL},
  30. {-1, 0, RT_NULL, RT_NULL},
  31. {-1, 0, RT_NULL, RT_NULL},
  32. {-1, 0, RT_NULL, RT_NULL},
  33. {-1, 0, RT_NULL, RT_NULL},
  34. };
  35. /* Configure pin mode. pin 0~63 means PIO0_0 ~ PIO1_31 */
  36. static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
  37. {
  38. int portx, piny, dir;
  39. uint32_t pin_cfg;
  40. if(pin > PIN_MAX_VAL)
  41. return;
  42. portx = get_port(pin);
  43. piny = get_pin(pin);
  44. switch(mode)
  45. {
  46. case PIN_MODE_OUTPUT:
  47. dir = kGPIO_DigitalOutput;
  48. pin_cfg = IOCON_FUNC0 | IOCON_DIGITAL_EN;
  49. break;
  50. case PIN_MODE_OUTPUT_OD:
  51. dir = kGPIO_DigitalOutput;
  52. pin_cfg = IOCON_FUNC0 | IOCON_OPENDRAIN_EN | IOCON_DIGITAL_EN;
  53. break;
  54. case PIN_MODE_INPUT:
  55. dir = kGPIO_DigitalInput;
  56. pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN;
  57. break;
  58. case PIN_MODE_INPUT_PULLUP:
  59. dir = kGPIO_DigitalInput;
  60. pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLUP;
  61. break;
  62. case PIN_MODE_INPUT_PULLDOWN:
  63. dir = kGPIO_DigitalInput;
  64. pin_cfg = IOCON_FUNC0 | IOCON_INPFILT_OFF | IOCON_DIGITAL_EN | IOCON_MODE_PULLDOWN;
  65. break;
  66. default: break;
  67. }
  68. CLOCK_EnableClock(kCLOCK_Iocon);
  69. IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
  70. GPIO_PortInit(GPIO, portx);
  71. gpio_pin_config_t pin_config = {(gpio_pin_direction_t)dir, 0};
  72. GPIO_PinInit(GPIO, portx, piny, &pin_config);
  73. CLOCK_DisableClock(kCLOCK_Iocon);
  74. }
  75. static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
  76. {
  77. int portx, piny;
  78. portx = get_port(pin);
  79. piny = get_pin(pin);
  80. if(pin > PIN_MAX_VAL)
  81. return;
  82. GPIO_PinWrite(GPIO, portx, piny, value);
  83. }
  84. static int lpc_pin_read(rt_device_t dev, rt_base_t pin)
  85. {
  86. int portx, piny, value;
  87. if(pin > PIN_MAX_VAL)
  88. return RT_ERROR;
  89. portx = get_port(pin);
  90. piny = get_pin(pin);
  91. value = (int)(GPIO_PinRead(GPIO, portx, piny));
  92. return value;
  93. }
  94. static void pin_irq_hdr(pint_pin_int_t pintr, uint32_t pmatch_status)
  95. {
  96. int irqno = 0;
  97. for(irqno = 0; irqno < IRQ_MAX_VAL; irqno ++)
  98. {
  99. if((irqno) == pintr)
  100. {
  101. break;
  102. }
  103. }
  104. if(irqno >= IRQ_MAX_VAL)
  105. return;
  106. if (pin_irq_hdr_tab[irqno].hdr)
  107. {
  108. pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
  109. }
  110. }
  111. void callback(pint_pin_int_t pintr, uint32_t pmatch_status)
  112. {
  113. pin_irq_hdr(pintr, pmatch_status);
  114. }
  115. static rt_err_t lpc_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
  116. rt_uint32_t mode, void (*hdr)(void *args), void *args)
  117. {
  118. int portx, piny, trigger_mode, pin_initx, pintsel, pin_cfg, i;
  119. if(pin > PIN_MAX_VAL)
  120. return RT_ERROR;
  121. portx = get_port(pin);
  122. piny = get_pin(pin);
  123. switch (mode)
  124. {
  125. case PIN_IRQ_MODE_RISING:
  126. trigger_mode = kPINT_PinIntEnableRiseEdge;
  127. break;
  128. case PIN_IRQ_MODE_FALLING:
  129. trigger_mode = kPINT_PinIntEnableFallEdge;
  130. break;
  131. case PIN_IRQ_MODE_RISING_FALLING:
  132. trigger_mode = kPINT_PinIntEnableBothEdges;
  133. break;
  134. case PIN_IRQ_MODE_HIGH_LEVEL:
  135. trigger_mode = kPINT_PinIntEnableHighLevel;
  136. break;
  137. case PIN_IRQ_MODE_LOW_LEVEL:
  138. trigger_mode = kPINT_PinIntEnableLowLevel;
  139. break;
  140. }
  141. /* Get inputmux_connection_t */
  142. pintsel = (pin + (0xC0U << 20));
  143. for(i = 0; i < IRQ_MAX_VAL; i++)
  144. {
  145. if(pin_irq_hdr_tab[i].pin == -1)
  146. {
  147. pin_initx = kPINT_PinInt0 + i;
  148. pin_irq_hdr_tab[i].pin = pin;
  149. pin_irq_hdr_tab[i].mode = trigger_mode;
  150. pin_irq_hdr_tab[i].hdr = hdr;
  151. pin_irq_hdr_tab[i].args = args;
  152. break;
  153. }
  154. }
  155. if(i >= IRQ_MAX_VAL)
  156. return RT_ERROR;
  157. /* open clk */
  158. CLOCK_EnableClock(kCLOCK_InputMux);
  159. CLOCK_EnableClock(kCLOCK_Iocon);
  160. /* AttachSignal */
  161. INPUTMUX_AttachSignal(INPUTMUX, i, (inputmux_connection_t)pintsel);
  162. pin_cfg = ((IOCON->PIO[portx][piny] &
  163. (~(IOCON_PIO_FUNC_MASK | IOCON_PIO_DIGIMODE_MASK | IOCON_PIO_FILTEROFF_MASK))) /* Mask bits to zero which are setting */
  164. | IOCON_PIO_FUNC(0) /* Selects pin function.: PORT18 (pin 28) is configured as PIO1_8 */
  165. | IOCON_PIO_DIGIMODE(1) /* Select Analog/Digital mode.: Digital mode. */
  166. | IOCON_PIO_FILTEROFF(0)); /* Controls input glitch filter.: Filter enabled. Noise pulses below approximately 10 ns are filtered out. */
  167. IOCON_PinMuxSet(IOCON, portx, piny, pin_cfg);
  168. /* PINT_PinInterruptConfig */
  169. PINT_PinInterruptConfig(PINT, (pint_pin_int_t)pin_initx, (pint_pin_enable_t)(pin_irq_hdr_tab[i].mode), callback);
  170. CLOCK_DisableClock(kCLOCK_InputMux);
  171. CLOCK_DisableClock(kCLOCK_Iocon);
  172. return RT_EOK;
  173. }
  174. static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
  175. {
  176. int i;
  177. if(pin > PIN_MAX_VAL)
  178. return RT_ERROR;
  179. for(i = 0; i < IRQ_MAX_VAL; i++)
  180. {
  181. if(pin_irq_hdr_tab[i].pin == pin)
  182. {
  183. pin_irq_hdr_tab[i].pin = -1;
  184. pin_irq_hdr_tab[i].hdr = RT_NULL;
  185. pin_irq_hdr_tab[i].mode = 0;
  186. pin_irq_hdr_tab[i].args = RT_NULL;
  187. break;
  188. }
  189. }
  190. return RT_EOK;
  191. }
  192. static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  193. rt_uint32_t enabled)
  194. {
  195. int irqn_type, i;
  196. if(pin > PIN_MAX_VAL)
  197. return RT_ERROR;
  198. for(i = 0; i < IRQ_MAX_VAL; i++)
  199. {
  200. if(pin_irq_hdr_tab[i].pin == pin)
  201. {
  202. switch(i)
  203. {
  204. case 0: irqn_type = PIN_INT0_IRQn; break;
  205. case 1: irqn_type = PIN_INT1_IRQn; break;
  206. case 2: irqn_type = PIN_INT2_IRQn; break;
  207. case 3: irqn_type = PIN_INT3_IRQn; break;
  208. case 4: irqn_type = PIN_INT4_IRQn; break;
  209. case 5: irqn_type = PIN_INT5_IRQn; break;
  210. case 6: irqn_type = PIN_INT6_IRQn; break;
  211. case 7: irqn_type = PIN_INT7_IRQn; break;
  212. default:break;
  213. }
  214. if(enabled)
  215. {
  216. /* PINT_EnableCallback */
  217. PINT_PinInterruptClrStatusAll(PINT);
  218. NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
  219. PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
  220. EnableIRQ((IRQn_Type)irqn_type);
  221. }
  222. else
  223. {
  224. /* PINT_DisableCallback */
  225. DisableIRQ((IRQn_Type)irqn_type);
  226. PINT_PinInterruptClrStatus(PINT, (pint_pin_int_t)(kPINT_PinInt0 + i));
  227. NVIC_ClearPendingIRQ((IRQn_Type)irqn_type);
  228. }
  229. break;
  230. }
  231. }
  232. if(i >= IRQ_MAX_VAL)
  233. return RT_ERROR;
  234. return RT_EOK;
  235. }
  236. const static struct rt_pin_ops _lpc_pin_ops =
  237. {
  238. lpc_pin_mode,
  239. lpc_pin_write,
  240. lpc_pin_read,
  241. lpc_pin_attach_irq,
  242. lpc_pin_detach_irq,
  243. lpc_pin_irq_enable,
  244. };
  245. int rt_hw_pin_init(void)
  246. {
  247. int result;
  248. PINT_Init(PINT);
  249. result = rt_device_pin_register("pin", &_lpc_pin_ops, RT_NULL);
  250. return result;
  251. }
  252. INIT_BOARD_EXPORT(rt_hw_pin_init);
  253. #endif