board.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114
  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-16 bluebear233 first version
  9. */
  10. #include <rtconfig.h>
  11. #include <rtthread.h>
  12. #include <rthw.h>
  13. #include "NuMicro.h"
  14. #include "drv_uart.h"
  15. #include "board.h"
  16. #ifdef __CC_ARM
  17. extern int Image$$RW_IRAM1$$ZI$$Limit;
  18. #elif __ICCARM__
  19. #pragma section="HEAP"
  20. #else
  21. extern int __bss_end;
  22. extern int __ram_top;
  23. #endif
  24. /**
  25. * This function will initial Clock tree.
  26. */
  27. static void clock_init(void)
  28. {
  29. /* Unlock protected registers */
  30. SYS_UnlockReg();
  31. SystemInit();
  32. /* Set XT1_OUT(PF.2) and XT1_IN(PF.3) to input mode */
  33. PF->MODE &= ~(GPIO_MODE_MODE2_Msk | GPIO_MODE_MODE3_Msk);
  34. /* Enable External XTAL (4~24 MHz) */
  35. CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
  36. /* Waiting for 12MHz clock ready */
  37. CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk);
  38. /* Switch HCLK clock source to HXT */
  39. CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HXT,CLK_CLKDIV0_HCLK(1));
  40. /* Set core clock as PLL_CLOCK from PLL */
  41. CLK_SetCoreClock(FREQ_192MHZ);
  42. /* Set both PCLK0 and PCLK1 as HCLK/4 */
  43. CLK->PCLKDIV = CLK_PCLKDIV_PCLK0DIV4 | CLK_PCLKDIV_PCLK1DIV4;
  44. SystemCoreClockUpdate();
  45. /* Lock protected registers */
  46. SYS_LockReg();
  47. }
  48. /**
  49. * This function will initial M487 board.
  50. */
  51. void rt_hw_board_init(void)
  52. {
  53. clock_init();
  54. #ifdef RT_USING_HEAP
  55. #ifdef __CC_ARM
  56. rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
  57. #elif __ICCARM__
  58. rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
  59. #else
  60. /* init memory system */
  61. rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
  62. #endif
  63. #endif /* RT_USING_HEAP */
  64. rt_hw_uart_init();
  65. #ifdef RT_USING_CONSOLE
  66. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  67. #endif
  68. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  69. NVIC_SetPriorityGrouping(7);
  70. #ifdef RT_USING_COMPONENTS_INIT
  71. rt_components_board_init();
  72. #endif
  73. }
  74. /**
  75. * This is the timer interrupt service routine.
  76. *
  77. */
  78. void SysTick_Handler(void)
  79. {
  80. /* enter interrupt */
  81. rt_interrupt_enter();
  82. rt_tick_increase();
  83. /* leave interrupt */
  84. rt_interrupt_leave();
  85. }
  86. void rt_hw_cpu_reset(void)
  87. {
  88. SYS_UnlockReg();
  89. SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
  90. }