drv_common.c 6.1 KB

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  1. /*
  2. * Copyright (c) 2006-2025, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-7 SummerGift first version
  9. */
  10. #include <drv_common.h>
  11. #include <bsp_api.h>
  12. #include "board.h"
  13. #ifdef RT_USING_PIN
  14. #include <drv_gpio.h>
  15. #endif
  16. #ifdef RT_USING_SERIAL
  17. #ifdef RT_USING_SERIAL_V2
  18. #include <drv_usart_v2.h>
  19. #else
  20. #error "Serial-v1 has been obsoleted, and please select serial-v2 as the default option"
  21. #endif
  22. #endif
  23. #ifdef SOC_SERIES_R9A07G0
  24. #include "gicv3.h"
  25. static uint64_t rtt_timer_delay;
  26. extern fsp_vector_t g_sgi_ppi_vector_table[BSP_CORTEX_VECTOR_TABLE_ENTRIES];
  27. static void SysTimerInterrupt(void);
  28. #endif
  29. #ifdef RT_USING_FINSH
  30. #include <finsh.h>
  31. static void reboot(uint8_t argc, char **argv)
  32. {
  33. #ifdef SOC_SERIES_R9A07G0
  34. R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
  35. R_BSP_SystemReset();
  36. #else
  37. NVIC_SystemReset();
  38. #endif
  39. }
  40. MSH_CMD_EXPORT(reboot, Reboot System);
  41. #endif /* RT_USING_FINSH */
  42. /* SysTick configuration */
  43. void rt_hw_systick_init(void)
  44. {
  45. #ifdef SOC_SERIES_R9A07G0
  46. SysTimerInterrupt();
  47. #else
  48. SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
  49. NVIC_SetPriority(SysTick_IRQn, 0xFF);
  50. #endif
  51. }
  52. /**
  53. * This is the timer interrupt service routine.
  54. *
  55. */
  56. void SysTick_Handler(void)
  57. {
  58. /* enter interrupt */
  59. rt_interrupt_enter();
  60. #ifdef SOC_SERIES_R9A07G0
  61. __set_CNTP_CVAL(__get_CNTP_CVAL() + rtt_timer_delay);
  62. #endif
  63. rt_tick_increase();
  64. /* leave interrupt */
  65. rt_interrupt_leave();
  66. }
  67. /**
  68. * @brief This function is executed in case of error occurrence.
  69. * @param None
  70. * @retval None
  71. */
  72. void _Error_Handler(char *s, int num)
  73. {
  74. /* USER CODE BEGIN Error_Handler */
  75. /* User can add his own implementation to report the HAL error return state */
  76. while (1)
  77. {
  78. }
  79. /* USER CODE END Error_Handler */
  80. }
  81. /**
  82. * This function will delay for some us.
  83. *
  84. * @param us the delay time of us
  85. */
  86. void rt_hw_us_delay(rt_uint32_t us)
  87. {
  88. #ifdef ARCH_ARM_CORTEX_M
  89. rt_uint32_t ticks;
  90. rt_uint32_t told, tnow, tcnt = 0;
  91. rt_uint32_t reload = SysTick->LOAD;
  92. ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
  93. told = SysTick->VAL;
  94. while (1)
  95. {
  96. tnow = SysTick->VAL;
  97. if (tnow != told)
  98. {
  99. if (tnow < told)
  100. {
  101. tcnt += told - tnow;
  102. }
  103. else
  104. {
  105. tcnt += reload - tnow + told;
  106. }
  107. told = tnow;
  108. if (tcnt >= ticks)
  109. {
  110. break;
  111. }
  112. }
  113. }
  114. #endif
  115. }
  116. #ifdef SOC_SERIES_R9A07G0
  117. static void SysTimerInterrupt(void)
  118. {
  119. uint64_t tempCNTPCT = __get_CNTPCT();
  120. /* Wait for counter supply */
  121. while (__get_CNTPCT() == tempCNTPCT)
  122. {
  123. R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MICROSECONDS);
  124. }
  125. /* generic timer initialize */
  126. /* set interrupt handler */
  127. g_sgi_ppi_vector_table[(int32_t) BSP_VECTOR_NUM_OFFSET +
  128. NonSecurePhysicalTimerInt] = SysTick_Handler;
  129. rtt_timer_delay = R_GSC->CNTFID0 / RT_TICK_PER_SECOND;
  130. /* set timer expiration from current counter value */
  131. __set_CNTP_CVAL(__get_CNTPCT() + rtt_timer_delay);
  132. /* configure CNTP_CTL to enable timer interrupts */
  133. __set_CNTP_CTL(1);
  134. R_BSP_IrqCfgEnable(NonSecurePhysicalTimerInt, (int32_t) BSP_VECTOR_NUM_OFFSET +
  135. NonSecurePhysicalTimerInt, RT_NULL);
  136. }
  137. #endif
  138. /**
  139. * This function will initial board.
  140. */
  141. rt_weak void rt_hw_board_init()
  142. {
  143. #ifdef SOC_SERIES_R9A07G0
  144. /* initialize hardware interrupt */
  145. rt_uint32_t redis_gic_base = platform_get_gic_dist_base();
  146. rt_int32_t cpu_id = rt_hw_cpu_id();
  147. arm_gic_redist_address_set(0, redis_gic_base, cpu_id);
  148. rt_hw_interrupt_init();
  149. #endif
  150. rt_hw_systick_init();
  151. /* Heap initialization */
  152. #if defined(RT_USING_HEAP)
  153. rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
  154. #endif
  155. /* Pin driver initialization is open by default */
  156. #ifdef RT_USING_PIN
  157. rt_hw_pin_init();
  158. #endif
  159. /* USART driver initialization is open by default */
  160. #ifdef RT_USING_SERIAL
  161. rt_hw_usart_init();
  162. #endif
  163. /* Set the shell console output device */
  164. #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
  165. rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
  166. #endif
  167. /* Board underlying hardware initialization */
  168. #ifdef RT_USING_COMPONENTS_INIT
  169. rt_components_board_init();
  170. #endif
  171. }
  172. FSP_CPP_HEADER
  173. #ifdef SOC_SERIES_R9A07G0
  174. void R_BSP_WarmStart(bsp_warm_start_event_t event) BSP_PLACE_IN_SECTION(".warm_start");
  175. #else
  176. void R_BSP_WarmStart(bsp_warm_start_event_t event);
  177. #endif
  178. FSP_CPP_FOOTER
  179. /*******************************************************************************************************************//**
  180. * This function is called at various points during the startup process. This implementation uses the event that is
  181. * called right before main() to set up the pins.
  182. *
  183. * @param[in] event Where at in the start up process the code is currently at
  184. **********************************************************************************************************************/
  185. void R_BSP_WarmStart (bsp_warm_start_event_t event)
  186. {
  187. if (BSP_WARM_START_RESET == event)
  188. {
  189. #if BSP_FEATURE_FLASH_LP_VERSION != 0
  190. /* Enable reading from data flash. */
  191. R_FACI_LP->DFLCTL = 1U;
  192. /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
  193. * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
  194. #endif
  195. }
  196. if (BSP_WARM_START_POST_C == event)
  197. {
  198. /* C runtime environment and system clocks are setup. */
  199. /* Configure pins. */
  200. R_IOPORT_Open(&g_ioport_ctrl, g_ioport.p_cfg);
  201. }
  202. }
  203. #if BSP_TZ_SECURE_BUILD
  204. BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ();
  205. /* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
  206. BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ()
  207. {
  208. }
  209. #endif